Solid-state imaging device and semiconductor device

Abstract

There is provided a solid-state imaging device including a laminated structure in which a first substrate and a second substrate having a smaller area than the first substrate are laminated, in which the first substrate includes: an electronic circuit including an imaging element; an inspection circuit configured to inspect the electronic circuit; a first bonding electrode for electrically and physically bonding with the second substrate, and provided in a first lamination region where the second substrate is to be laminated; and an inspection electrode provided in a region other than the first lamination region and electrically connected to the inspection circuit, and the second substrate includes: a logic circuit that controls the imaging element; and a second bonding electrode for bonding to the first bonding electrode of the first substrate.

Description

Technical Field

[0001] The present disclosure relates to a solid-state imaging device and a semiconductor device. Background Art

[0002] For example, in the manufacture of semiconductor devices such as solid-state imaging devices, wafers and chips are bonded and stacked. In this case, by preliminarily checking whether the electronic circuits provided on the wafers and chips are good and selectively stacking good wafers and good chips, the yield of the semiconductor device can be improved. An example of an inspection circuit for performing such an inspection is an inspection circuit described in the following Patent Document 1.

[0003] Citation List

[0004] Patent Literature

[0005] Patent Document 1: JP 2021-103760 A Summary of the invention

[0006] Technical issues

[0007] Therefore, before lamination as described above, the inspection is performed by bringing the needle tip of the inspection device into contact with the inspection electrode provided on the wafer, but the needle tip may leave a needle mark with unevenness on the inspection electrode of the inspection circuit. Then, when a good chip is bonded and laminated on the inspection electrode with such a needle mark, there is a high possibility that a poor connection will occur between the wafer and the chip due to the unevenness of the needle mark.

[0008] Therefore, the present disclosure proposes a solid-state imaging device and a semiconductor device capable of preventing the occurrence of bonding failure between a wafer (or chip) and a chip due to a needle mark remaining on an inspection electrode.

[0009] Solution to the problem

[0010] According to the present disclosure, a solid-state imaging device is provided, which includes a stacked structure in which a first substrate and a second substrate having an area smaller than that of the first substrate are stacked. In the solid-state imaging device, the first substrate includes: an electronic circuit including an imaging element; an inspection circuit configured to inspect the electronic circuit; a first bonding electrode for electrically and physically bonding with the second substrate and arranged in a first stacking region where the second substrate is to be stacked; and an inspection electrode arranged in a region outside the first stacking region and electrically connected to the inspection circuit, and the second substrate includes: a logic circuit for controlling the imaging element; and a second bonding electrode for bonding with the first bonding electrode of the first substrate.

[0011] In addition, according to the present disclosure, a semiconductor device is provided, which includes a stacked structure in which a first substrate and a second substrate having a smaller area than the first substrate are stacked. In the semiconductor device, the first substrate includes: an electronic circuit; an inspection circuit configured to inspect the electronic circuit; a first bonding electrode for electrically and physically bonding with the second substrate and arranged in a first stacking region where the second substrate is to be stacked; and an inspection electrode arranged in a region outside the first stacking region and electrically connected to the inspection circuit, and the second substrate includes a second bonding electrode for bonding with the first bonding electrode of the first substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 : is a block diagram showing an outline of a basic configuration of a CMOS image sensor as an example of an imaging device applicable to each embodiment of the present disclosure.

[0013] Figure 2 is a circuit diagram showing an example of a circuit configuration of a pixel applicable to each embodiment of the present disclosure.

[0014] Figure 3 : is a block diagram showing a configuration example of a column-parallel AD conversion unit applicable to each embodiment of the present disclosure.

[0015] Figure 4 It is an exploded perspective view showing an outline of a stacked chip structure of an imaging device.

[0016] Figure 5 This is a diagram showing a specific configuration example of a first semiconductor substrate of an imaging device to which the technology of the present disclosure can be applied.

[0017] Figure 6 This is a diagram showing a specific configuration example of a first semiconductor substrate of an imaging device to which the technology of the present disclosure can be applied.

[0018] Figure 7 : is an explanatory diagram (Part 1) for explaining the method of manufacturing the imaging device according to the first embodiment of the present disclosure.

[0019] Figure 8 2 is an explanatory diagram (Part 2) for explaining the method of manufacturing the imaging device according to the first embodiment of the present disclosure.

[0020] Fig. 9 : is an explanatory diagram (Part 3) for explaining the method of manufacturing the imaging device according to the first embodiment of the present disclosure.

[0021] Fig.10 : is an explanatory diagram (Part 4) for explaining the method of manufacturing the imaging device according to the first embodiment of the present disclosure.

[0022] Fig.11: is an explanatory diagram (Part 5) for explaining the method of manufacturing the imaging device according to the first embodiment of the present disclosure.

[0023] Fig.12 : is an explanatory diagram for explaining an imaging device according to a first embodiment of the present disclosure.

[0024] Fig.13 is an explanatory diagram for explaining an imaging device according to a second embodiment of the present disclosure.

[0025] Fig.14 : is an explanatory diagram for explaining an imaging device according to a third embodiment of the present disclosure.

[0026] Fig.15 : is an explanatory diagram for explaining a method of manufacturing an imaging device according to a fourth embodiment of the present disclosure.

[0027] Fig.16 : is an explanatory diagram for explaining an imaging device according to a fourth embodiment of the present disclosure.

[0028] Fig.17 are views showing application examples using each embodiment according to the disclosed technology.

[0029] Fig.18 is a block diagram showing the configuration of an example of a camera to which the technology according to the present disclosure can be applied. DETAILED DESCRIPTION

[0030] Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Note that in this specification and the accompanying drawings, constituent elements having substantially the same functional composition will be represented by the same reference numerals, and their redundant description will be omitted. In addition, in this specification and the accompanying drawings, multiple constituent elements having substantially the same or similar functional composition can be distinguished from each other by following different numbers or letters with the same reference numerals. However, in the case where it is not necessary to particularly distinguish each of the multiple constituent elements having substantially the same or similar functional composition, only the same reference numerals will be attached.

[0031] In addition, the drawings referred to in the following description are drawings for the purpose of facilitating the description and understanding of the embodiments of the present disclosure, and for the sake of clarity, the shapes, sizes, ratios, etc. shown in the drawings are sometimes different from the actual ones. In addition, considering the following description and known technologies, the devices shown in the drawings, etc. can be appropriately changed in design.

[0032] In the following description, “electrically connected” means that a plurality of elements are connected directly or indirectly via other elements.

[0033] Note that the description will be given in the following order.

[0034] 1. Background of the present disclosure

[0035] 1.1 Example of CMOS image sensor configuration

[0036] 1.2 Pixel Circuit Configuration Example

[0037] 1.3 Example of the structure of a column parallel analog-to-digital conversion unit

[0038] 1.4 Example of stacked structure

[0039] 1.5 Overview of Inspection

[0040] 1.6 Example of inspection circuit configuration

[0041] 1.7 Background

[0042] 2. First Implementation Method

[0043] 2.1 Manufacturing method

[0044] 2.2 Detailed structure

[0045] 3. Second Implementation Method

[0046] 4. Third Implementation Method

[0047] 5. Fourth Implementation Method

[0048] 5.1 Manufacturing method

[0049] 5.2 Detailed structure

[0050] 6. Summary

[0051] 7. Application examples

[0052] 8. Supplement

[0053] <<1. Background of the present disclosure>>

[0054] First, before explaining the embodiment of the present disclosure, the background that led the inventors to create the embodiment of the present disclosure will be explained. First, the schematic configuration of an imaging device (solid-state imaging device) to which the technology of the present disclosure can be applied will be explained in sequence.

[0055] <1.1 Example of CMOS Image Sensor Configuration>

[0056] First, the basic structure of an imaging device 1 to which the technology of the present disclosure can be applied will be described. Here, as the imaging device 1, a complementary metal oxide semiconductor (CMOS) image sensor, which is a type of imaging device of an XY address method, will be described as an example. A CMOS image sensor is an image sensor manufactured by applying or partially using a CMOS process. Figure 11 is a block diagram showing an outline of a basic configuration of a CMOS image sensor as an example of the imaging device 1 applicable to each embodiment of the present disclosure.

[0057] Figure 1 The imaging device 1 shown in the figure includes a pixel array unit (cell array) 11 and a peripheral circuit unit of the pixel array unit 11, wherein each pixel (cell) (imaging element) 2 including a photoelectric conversion unit is arranged two-dimensionally in the row direction and the column direction, that is, arranged in a matrix shape. Here, the row direction refers to the arrangement direction (horizontal direction) of the pixels 2 in the pixel row, and the column direction refers to the arrangement direction (vertical direction) of the pixels 2 in the pixel column. The pixel 2 performs photoelectric conversion to generate and accumulate a charge corresponding to the amount of light received.

[0058] exist Figure 1 In the example, examples of the peripheral circuit units of the pixel array unit 11 include a row selection unit 12, a constant current source unit 13, an analog-to-digital conversion unit 14, a horizontal transfer scanning unit 15, a signal processing unit 16 and a timing control unit 17.

[0059] In the pixel array unit 11, the control lines 321 to 32 n Each pixel row is wired along the row direction. m The vertical signal lines 311 to 312 are arranged along the column direction for each pixel column. m In the case of m Similarly, in the case where there is no need to distinguish between the control lines 321 to 322, it is described as the vertical signal line 31. n In the case of n This is suitably described as control line 32 .

[0060] When a signal is read out from the pixel 2, the control line 32 sends a drive signal for performing driving. Figure 1 , the control line 32 is shown as one wiring line, but the control line 32 is not limited to one and may include a plurality of wiring lines. One end of the control line 32 is connected to the output end corresponding to each row of the row selection unit 12.

[0061] Next, the respective circuit parts of the peripheral circuit unit of the pixel array unit 11, namely, the row selection unit 12, the constant current source unit 13, the analog-to-digital conversion unit 14, the horizontal transfer scanning unit 15, the signal processing unit 16 and the timing control unit 17 will be described.

[0062] The row selection unit 12 includes a shift register, an address decoder, etc., and controls scanning of a pixel row and an address of a pixel row when selecting each pixel 2 included in the pixel array unit 11. Although a specific configuration of the row selection unit 12 is not shown, the row selection unit 12 generally includes two scanning systems of a readout scanning system and a sweepout scanning system.

[0063] The readout scanning system selectively scans the pixels 2 of the pixel array unit 11 in units of rows so as to read out pixel signals from the pixels 2. The pixel signals read out from the pixels 2 are analog signals. The scan-out scanning system performs scan-out scanning on the readout rows for which the readout scanning is performed by the readout scanning system before the time corresponding to the shutter speed of the readout scanning.

[0064] By scanning performed by the sweep-out scanning system, unnecessary charges are scanned from the photoelectric conversion unit of the pixel 2 in the readout row, thereby resetting the photoelectric conversion unit. Then, since the sweep-out scanning system sweeps out (resets) the unnecessary charges, a so-called electronic shutter operation is performed. Here, the electronic shutter operation refers to an operation of discarding the charges of the photoelectric conversion unit and restarting exposure (starting accumulation of charges).

[0065] The constant current source unit 13 includes a plurality of current sources I, each of which includes, for example, a metal oxide semiconductor (MOS) transistor and is connected to the vertical signal lines 311 to 313 for each pixel column. m The constant current source unit 13 passes through the vertical signal lines 311 to 31 m Each of them supplies a bias current to each pixel 2 of a pixel row selectively scanned by the row selection unit 12.

[0066] The analog-to-digital conversion unit 14 includes, for example, a plurality of analog-to-digital converters provided for each pixel column, and is provided to correspond to the pixel columns of the pixel array unit 11, respectively. The analog-to-digital conversion unit 14 is a column-parallel type analog-to-digital conversion unit, which is used as a signal for each pixel column through the vertical signal lines 311 to 31 m Each pixel signal of the output analog signal is converted into an N-bit digital signal. Hereinafter, the analog-to-digital conversion unit 14 is referred to as a column-parallel analog-to-digital conversion unit 14.

[0067] As the analog-to-digital converter included in the column-parallel analog-to-digital conversion unit 14, for example, a single-slope type analog-to-digital converter as an example of a reference signal comparison type analog-to-digital converter can be used. Note that the present disclosure is not limited to such an example, and a successive approximation type analog-to-digital converter, a ΔΣ modulation type (ΔΣ modulation type) analog-to-digital converter, or the like can be used as the analog-to-digital converter included in the column-parallel analog-to-digital conversion unit 14.

[0068] The horizontal transfer scanning unit 15 includes a shift register, an address decoder, etc., and controls the scanning of the pixel columns and the addresses of the pixel columns when reading out the signals of the respective pixels 2 of the pixel array unit 11. Under the control of the horizontal transfer scanning unit 15, the pixel signals converted into digital signals by the column parallel analog-to-digital conversion unit 14 are read out to the horizontal transfer lines 18 having a width of 2N bits in units of pixel columns.

[0069] The signal processing unit 16 performs predetermined signal processing on the digital pixel signal supplied through the horizontal transmission line 18 to generate two-dimensional image data. For example, the signal processing unit 16 can perform signal processing such as correction of vertical line defects and point defects and signal clamping on the supplied pixel signal. In addition, the signal processing unit 16 can perform signal processing such as parallel to serial conversion, compression, encoding, addition, averaging, and intermittent operation on the supplied pixel signal. The signal processing unit 16 outputs the generated image data as an output signal of the imaging device 1 to the subsequent device.

[0070] The timing control unit 17 generates various timing signals, clock signals, control signals, etc., and performs drive control of the row selection unit 12, constant current source unit 13, column parallel analog-to-digital conversion unit 14, horizontal transfer scanning unit 15, signal processing unit 16, etc. based on the generated signals.

[0071] <1.2-Pixel Circuit Configuration Example>

[0072] Figure 2 2 is a circuit diagram showing an example of a circuit configuration of a pixel 2 applicable to each embodiment of the present disclosure. The pixel 2 includes, for example, a photodiode 21 as a photoelectric conversion unit. In addition to the photodiode 21, the pixel 2 also includes a transfer transistor 22, a reset transistor 23, an amplification transistor 24, and a selection transistor 25.

[0073] exist Figure 2 In the example of , four transistors, namely, the transfer transistor 22, the reset transistor 23, the amplification transistor 24, and the selection transistor 25, are formed using, for example, an N-channel MOS field effect transistor (FET). Hereinafter, the N-channel MOS field effect transistor is referred to as an NMOS transistor. Since the pixel 2 includes only NMOS transistors, it is possible to achieve optimization from the perspective of area efficiency and process reduction. Note that Figure 2 The combination of conductivity types of the transfer transistor 22 , the reset transistor 23 , the amplification transistor 24 , and the selection transistor 25 shown in is only an example, and the combination is not limited.

[0074] For the pixel 2, as the above-mentioned control line 32, a plurality of control lines are commonly wired to each pixel 2 of the same pixel row. The plurality of control lines are connected in units of pixel rows to output terminals corresponding to each pixel row of the row selection unit 12. The row selection unit 12 appropriately outputs a transfer signal TRG, a reset signal RST, and a selection signal SEL to the plurality of control lines.

[0075] The anode electrode of the photodiode 21 is connected to a low potential side power supply (for example, a ground potential), photoelectrically converts received light into charges (here, photoelectrons) having a charge amount corresponding to the light amount, and accumulates the charges. The cathode electrode of the photodiode 21 is electrically connected to the gate electrode of the amplifier transistor 24 via the transfer transistor 22. Here, the region electrically connected to the gate electrode of the amplifier transistor 24 is the floating diffusion region FD. The floating diffusion region FD is a charge-voltage conversion unit that converts charges into voltage.

[0076] With a high level (for example, V DD A transfer signal TRG activated by a voltage level (0.1V) is supplied from the row selection unit 12 to the gate electrode of the transfer transistor 22. The transfer transistor 22 becomes conductive in response to the transfer signal TRG, thereby transferring charges photoelectrically converted by the photodiode 21 and accumulated in the photodiode 21 to the floating diffusion region FD.

[0077] The reset transistor 23 is connected to a power source V that supplies a high potential side power supply voltage. DD The reset signal RST activated at a high level is supplied from the row selection unit 12 to the gate electrode of the reset transistor 23. The reset transistor 23 becomes conductive in response to the reset signal RST and discards the charge of the floating diffusion region FD to the power supply V DD to reset the floating diffusion region FD.

[0078] The gate electrode and the drain electrode of the amplifying transistor 24 are connected to the floating diffusion region FD and the power supply V DD The amplifier transistor 24 is used as an input unit of a source follower that reads out a signal obtained by photoelectric conversion in the photodiode 21. That is, the source electrode of the amplifier transistor 24 is connected to the vertical signal line 31 via the selection transistor 25. Then, the amplifier transistor 24 and the current source I connected to one end of the vertical signal line 31 constitute a source follower that converts the voltage of the floating diffusion region FD into the voltage of the vertical signal line 31.

[0079] The drain electrode and the source electrode of the selection transistor 25 are respectively connected to the source electrode of the amplifier transistor 24 and the vertical signal line 31. The selection signal SEL activated at a high level is supplied from the row selection unit 12 to the gate electrode of the selection transistor 25. The selection transistor 25 becomes conductive in response to the selection signal SEL, thereby transmitting the signal output from the amplifier transistor 24 to the vertical signal line 31 when the pixel 2 is in the selected state.

[0080] Note that, for the selection transistor 25, it is also possible to connect the power supply V DD A circuit is formed between the node of and the drain electrode of the amplifier transistor 24. Figure 2 In the example of FIG. 1 , a 4Tr configuration including four transistors (Tr), namely, a transfer transistor 22, a reset transistor 23, an amplifying transistor 24, and a selecting transistor 25 is described as an example of a pixel circuit of the pixel 2, but the present disclosure is not limited thereto. For example, a 3Tr configuration in which the selecting transistor 25 is omitted and the amplifying transistor 24 has the function of the selecting transistor 25 may be adopted, or a configuration of 5Tr or more obtained by increasing the number of transistors as needed may be adopted.

[0081] <1.3 Example of Configuration of Column Parallel Analog-to-Digital Conversion Unit>

[0082] Next, a configuration example of the column-parallel analog-to-digital conversion unit 14 will be described. Figure 3 1 is a block diagram showing an example of the configuration of a column-parallel analog-to-digital conversion unit 14 applicable to each embodiment of the present disclosure. The analog-to-digital conversion unit 14 in the imaging device 1 of the present disclosure includes columns corresponding to the vertical signal lines 311 to 31 m Here, the single slope type analog-to-digital converter 140 of the nth column will be described as an example.

[0083] The single slope type analog-to-digital converter 140 has a circuit configuration including a comparator 141, a counter circuit 142, and a latch circuit 143. The single slope type analog-to-digital converter 140 uses a reference signal of a so-called RAMP waveform (ramp waveform) in which a voltage value changes linearly with time. The reference signal of the ramp waveform is generated by a reference signal generating unit 19. The reference signal generating unit 19 can be configured using, for example, a digital-to-analog conversion circuit.

[0084] The comparator 141 uses the analog pixel signal read out from the pixel 2 as a comparison input, and uses the reference signal of the ramp waveform generated by the reference signal generating unit 19 as a reference input, and compares the two signals. Then, for example, when the reference signal is greater than the pixel signal, the output of the comparator 141 is a first state (e.g., a high level), and when the reference signal is equal to or less than the pixel signal, it is a second state (e.g., a low level). As a result, the comparator 141 outputs a pulse signal having a pulse width corresponding to the signal level of the pixel signal (specifically, corresponding to the amplitude of the signal level) as a comparison result.

[0085] The clock signal CLK is supplied from the timing control unit 17 to the counting circuit 142 at the same timing as the supply start timing of the reference signal with respect to the comparator 141. Then, the counting circuit 142 performs a counting operation in synchronization with the clock signal CLK to measure the period of the pulse width of the output pulse of the comparator 141, that is, the period from the start of the comparison operation to the end of the comparison operation. The counting result (count value) of the counting circuit 142 is a digital value obtained by digitizing the analog pixel signal.

[0086] The latch circuit 143 holds (latches) a digital value as a result of counting by the counting circuit 142. In addition, the latch circuit 143 obtains a difference between a count value of a D phase corresponding to a pixel signal at a signal level and a count value of a P phase corresponding to a pixel signal at a reset level, thereby performing correlated double sampling (CDS) as an example of noise removal processing. Then, the latch circuit 143 outputs the latched digital value to the horizontal transfer line 18 under the drive of the horizontal transfer scanning unit 15.

[0087] As described above, in the column-parallel analog-to-digital conversion unit 14 including a set of single-slope type analog-to-digital converters 140, a digital value is obtained from time information until the magnitude relationship between the reference signal, which is a linearly varying analog value generated by the reference signal generating unit 19, and the analog pixel signal output from the pixel 2 changes. Note that the analog-to-digital conversion unit 14 in which the single-slope type analog-to-digital converters 140 are arranged in a one-to-one relationship with the pixel columns has been exemplified in the above example, but an analog-to-digital conversion unit 14 in which the single-slope type analog-to-digital converters 140 are arranged in units of a plurality of pixel columns may also be employed.

[0088] <1.4 Example of stacked structure>

[0089] Next, an example of a stacked structure of a CMOS image sensor as the imaging device 1 having the above-described configuration will be described. The imaging device 1 having the above-described configuration has a stacked chip structure (stacked chip).

[0090] Figure 4is an exploded perspective view showing an outline of the stacked chip structure of the imaging device 1. Figure 4 4. The first semiconductor substrate 41 and the second semiconductor substrate 42 are shown as having the same size in FIG. 4, but in the imaging device 1 to which the embodiment of the present disclosure is applied, the size of the second semiconductor substrate 42 may actually be smaller than that of the first semiconductor substrate 41.

[0091] like Figure 4 As shown, the stacked chip structure of the imaging device 1 has a structure in which at least two semiconductor substrates, a first semiconductor substrate 41 and a second semiconductor substrate 42, are stacked and bonded. In this stacked structure, each pixel 2 of the pixel array unit 11, the control lines 321 to 32 n and vertical signal lines 311 to 31 m The first semiconductor substrate 41 is formed on the first layer.

[0092] In addition, on the second semiconductor substrate 42 of the second layer, a pixel control unit including a row selection unit 12, a constant current source unit 13, an analog-to-digital conversion unit 14, a horizontal transfer scanning unit 15, a signal processing unit 16, a timing control unit 17, a reference signal generation unit 19, etc. is formed. Figure 4 In order to avoid complexity, the signal processing unit 16 and the reference signal generating unit 19 are omitted. The pixel control unit is a peripheral circuit unit of the pixel array unit 11.

[0093] Then, the first semiconductor substrate 41 of the first layer and the second semiconductor substrate 42 of the second layer are electrically connected through connection portions 43 and 44 such as through chip vias (TCVs) and Cu-Cu hybrid bonding.

[0094] According to such a stacked structure, since the area can be made as large as the pixel array unit 11 formed by the first semiconductor substrate 41 which can be the first layer, the size of the first semiconductor substrate 41 and the size of the entire chip can be reduced. In addition, the process suitable for manufacturing the pixel 2 can be applied to the first semiconductor substrate 41 of the first layer, and the process suitable for manufacturing the pixel control unit can be applied to the second semiconductor substrate 42 of the second layer, so these processes can be optimized when manufacturing the imaging device 1.

[0095] Note that a stacked structure which is a two-layer structure formed by stacking the first semiconductor substrate 41 and the second semiconductor substrate 42 has been exemplified here, but the stacked structure is not limited to a two-layer structure and may be a structure of three or more layers.

[0096] <1.5 Inspection Overview>

[0097] When sorting good and bad products of the imaging device 1, the control lines 321 to 322 are usually checked. nand vertical signal lines 311 to 31 m Check whether there is any disconnection (breakage) in the wiring and whether there is a short circuit (short circuit) between adjacent wirings.

[0098] On the other hand, examples of stacking methods of stacked chips include a method of bonding wafers to wafers (WOW: wafer on wafer) and a method of bonding wafers to good chips (COW: chip on wafer). In the case of stacked chips in the COW method, unlike the case of stacked chips in the WOW method, the yield can be improved by selectively combining good products and good products.

[0099] Therefore, in the imaging device 1 to which the present disclosure can be applied, an inspection circuit is added to the first semiconductor substrate 41 as the sensor substrate on which the pixel array unit 11 is formed to enable inspection of the presence or absence of disconnection / short-circuit of wiring.

[0100] Figure 5 1 is a diagram showing a specific configuration example of a first semiconductor substrate 41 of an imaging device to which the present disclosure can be applied. In the first semiconductor substrate 41, a first wiring is formed to correspond to a first pixel row, and a second wiring is formed to correspond to a second pixel row. Hereinafter, the wiring formed to correspond to a pixel row is appropriately referred to as a row wiring. Here, the first row wiring formed to correspond to a pixel row refers to a control line 321 formed to correspond to a pixel row of the first row, and the second row wiring formed to correspond to a pixel row refers to a control line 321 formed to correspond to a pixel row of the nth row. n . Represented as control lines 322 to 32 n-1 A plurality of row wirings exist between the first row wiring and the second row wiring.

[0101] Furthermore, in the first semiconductor substrate 41, a first column wiring is formed to correspond to the first pixel column, and a second column wiring is formed to correspond to the second pixel column. Hereinafter, the wiring formed to correspond to the pixel column is appropriately referred to as a column wiring. The first column wiring formed to correspond to the pixel column refers to the vertical signal line 311 formed to correspond to the pixel column of the first column, and the second column wiring formed to correspond to the pixel column refers to the vertical signal line 311 formed to correspond to the pixel column of the mth column. m . It is represented by vertical signal lines 312 to 31 m-1 A plurality of column wirings exist between the first column wiring and the second column wiring.

[0102] like Figure 4 As shown, the first semiconductor substrate 41 is provided with wiring (control lines 321 to 32 n and vertical signal lines 311 to 31 m) and the connection parts 43A and 43B and the connection parts 44A and 44B of the pixel control unit formed on the second semiconductor substrate 42 as the second substrate. Here, in the case where the circuit of the pixel control unit to be connected exists only on one side in the vertical direction, it is sufficient to provide either the connection parts 43A or 43B. For example, the vertical signal lines 311 to 31 m The analog-to-digital conversion unit 14 is connected via the connection section 43A. Similarly, in the case where the circuit of the pixel control unit to be connected exists only on one side in the horizontal direction, it is sufficient to provide either the connection section 44A or the connection section 44B. n The row selection unit 12 is connected via the connection section 44A. Note that, hereinafter, in the case where the connection sections 43A and 43B do not need to be particularly distinguished, the connection sections 43A and 43B are collectively referred to as the connection section 43.

[0103] Furthermore, an inspection circuit 45A and a bias unit 45B corresponding to the inspection circuit 45A, and an inspection circuit 46A and an inspection circuit 46B corresponding to the inspection circuit 46A are provided on the first semiconductor substrate 41 .

[0104] In addition, electrodes associated with the inspection circuit 45A and the bias unit 45B, and the inspection circuit 46A and the bias unit 46B are provided on the first semiconductor substrate 41. That is, the first semiconductor substrate 41 is provided with electrodes 47A, 47C, 47D, and 49A connected to the inspection circuit 45A. In addition, the first semiconductor substrate 41 is provided with electrodes 48A, 48C, 48D, and 50A connected to the inspection circuit 46A. In addition, the first semiconductor substrate 41 is provided with electrodes 49B and 47B connected to the bias unit 45B. In addition, the first semiconductor substrate 41 is provided with electrodes 48B and 50B connected to the bias unit 46B.

[0105] Each electrode provided on the first semiconductor substrate 41 is a probe terminal for inspection in a wafer state.

[0106] The bias unit 45B includes a bias unit for biasing the vertical signal lines 311 to 31 m The bias unit 45B applies a predetermined voltage to the electrode 49B to connect the electrode 49B and the vertical signal lines 311 to 31 m For detecting the vertical signal lines 311 to 31 m The voltage application inspection circuit 45A is connected to the vertical signal lines 311 to 31 mThe far end relative to the bias unit 45B. For example, in the inspection circuit 45A, the voltage of the electrode 47A can be monitored from the electrode 47C. In addition, in the inspection circuit 45A, a predetermined voltage is applied to the electrode 49A to connect the electrode 49A and the vertical signal lines 311 to 31 m some or all of .

[0107] Similarly, for controlling lines 321 to 32 n Each bias unit 46B for applying a voltage and for detecting the control lines 321 to 32 n Each voltage applied inspection circuit 46A is connected to the control lines 321 to 32 n .

[0108] Note that the inspection circuits 45A and 46A and the bias units 45B and 46B arranged on the first semiconductor substrate 41 are not usually used after the first semiconductor substrate 41 and the second semiconductor substrate 42 are attached and stacked.

[0109] As described above, in the imaging device 1 to which the present disclosure can be applied, a circuit including inspection circuits 45A and 46A, bias units 45B and 46B, and electrodes 47A, 47B, 47C, 47D, 48A, 48B, 48C, 48D, 49A, 49B, 50A and 50B is added, thereby enabling inspection of the presence or absence of wiring disconnection / short circuit.

[0110] <1.6 Example of Inspection Circuit Configuration>

[0111] Next, a specific configuration example of the inspection circuit of the imaging device 1 to which the technology of the present disclosure can be applied will be described. Figure 6 4 is a diagram showing a specific configuration example of the configuration of the first semiconductor substrate 41a of the imaging device 1 to which the technology of the present disclosure can be applied. Figure 6 In, with Figure 5 The first semiconductor substrate 41a and the second semiconductor substrate 42 corresponding to the first semiconductor substrate 41 are stacked to form the imaging device 1. Figure 6 Omitted Figure 5 The pixels 2 and control lines 321 to 322 included in the pixel array unit 11 are shown in FIG. n . Similarly, in Figure 6 The appropriate omission Figure 5 The structure related to the pixel row (related to each control line 321 to 32 n related composition).

[0112] exist Figure 6 In the example, the connection portion 43A includes connection nodes N corresponding in number to the number of columns (m) of the pixel array unit 11. 1a , N2a , N 3a , N 4a ,…,N (m-2)a , N (m-1)a and N ma Similarly, the connection portion 43B includes connection nodes N corresponding in number to the number of columns (m) of the pixel array unit 11. 1b , N 2b , N 3b , N 4b ,…,N (m-2)b , N (m-1)b and N mb .

[0113] Each vertical signal line 311 to 31 m One end is connected to each connection node N one by one 1b ~N mb Similarly, each vertical signal line 311 to 31 m The other end is connected one-to-one to each connection node N 1a ~N ma .

[0114] The first semiconductor substrate 41 and the second semiconductor substrate 42 are connected via respective connection nodes N 1a ~N ma Or each connection node N 1b ~N mb Electrical connection.

[0115] The bias unit 45B includes switch elements SW1, SW2, SW3, SW4, . . . , SW5 as bias circuits, the number of which corresponds to the number of columns (m) of the pixel array unit 11. (m-2) , S.W. (m-1) and SW m Similar to pixel 2, each switch element SW1 to SW m Each of the switch elements SW1 to SW m One end (drain) is connected to electrode 47B, and the other end (source) is connected to node N 1b ~N mb One-to-one connection to vertical signal lines 311 to 31 m one end.

[0116] Switching elements SW1 to SW m The control terminals (gates) of the switch elements SW are connected to the electrode 49B. When a high voltage (for example, 3 [V]) is applied to the electrode 49B, each switch element SW 1b ~SW mb The electrode 47B is connected to each vertical signal line 311 to 31 m, and the voltage applied to the electrode 47B is applied to each vertical signal line 311 to 31 m That is, each of the switch elements SW1 to SW m can be regarded as the vertical signal lines 311 to 31 m Here, each switching element SW 1b ~SW mb A voltage drop occurs at the threshold value of , but the influence of the voltage drop can be suppressed by increasing the voltage applied to electrode 49B within the range allowed by the withstand voltage.

[0117] The inspection circuit 45A includes transmission elements TR1, TR2, TR3, TR4, . . . , TR (m-2) , TR (m-1) and TR m Similar to the pixel 2, each of the transmission elements TR1 to TRm includes, for example, an NMOS transistor. Each of the vertical signal lines 311 to 31 m Connect via node N1 a ~N ma One-to-one connection to each transmission element TR1~TR m of the gate.

[0118] That is, each transmission element TR1 to TR m can be regarded as inputting the vertical signal lines 311 to 31 m In addition, each transmission element TR1~TR m It functions as a switch that is controlled to be conductive or non-conductive according to a voltage input (applied) to the gate.

[0119] In addition, each transmission element TR1~TR m The series connection is made, with electrode 47A connected to one end of the series connection and electrode 47C connected to the other end.

[0120] More specifically, in the transmission elements TR1 to TR m For example, the configuration in Figure 6 The drain of the transmission element TR1 at the middle left end is connected to the electrode 47A, and its source is connected to the drain of the transmission element TR2 adjacent to the transmission element TR1. The source of the transmission element TR2 is connected to the drain of the transmission element TR3 adjacent to the transmission element TR2, and the source of the transmission element TR3 is connected to the drain of the transmission element TR4 adjacent to the transmission element TR3. As described above, each of the transmission elements TR1 to TR4 is connected to the transmission element TR2. (m-1) The source of the transmission element TR is sequentially connected to the drain of the adjacent transmission element. (m-1) The source is connected to the Figure 6 The transmission element TR at the middle rightm The drain of the transmission element TR m The source is connected to electrode 47C.

[0121] With such a configuration, the electrode 47B is connected to each of the transmission elements TR1 to TR m of the gate.

[0122] In the following, Figure 6 As shown, each transistor (transmission element TR1 to TR m ) A mode in which adjacent transistors are connected in sequence through the connection of the drain and source is called a series connection. In a series connection, the output is determined by the logical product of each gate state relative to the voltage applied to the gate of each transistor. That is, when at least one of the transistors in the series connection is disconnected (non-conductive), both ends of the series connection become non-conductive.

[0123] In addition, a mode in which a plurality of transistors are connected so that the drain and source of each transistor are connected in common and the gate of each transistor is connected independently is called a parallel connection. In a parallel connection, the output is determined by the logical sum of the states of each gate relative to the voltage applied to the gate of each transistor. That is, when at least one of the transistors connected in parallel is turned on, both ends of the parallel connection (between the commonly connected source and drain) become conductive.

[0124] <1.7 Background>

[0125] Next, the creation background that led to the presently disclosed embodiments created by the present inventors will be described.

[0126] As described above, examples of stacking methods of stacked chips include a method of bonding wafers together (WOW) and a method of bonding wafers and good chips together (COW). In the case of stacked chips in the COW method, unlike the case of stacked chips in the WOW method, the yield can be improved by selectively combining good products and good products.

[0127] Therefore, in order to sort good products before bonding, for example, the above-mentioned inspection circuit and the inspection electrode electrically connected to the inspection circuit are provided on the wafer. Then, in the manufacturing stage of the imaging device, the needle tip of the inspection device is brought into contact with the inspection electrode of the wafer to apply a voltage having a predetermined potential and measure the voltage, and the needle tip leaves a needle mark having unevenness on the inspection electrode.

[0128] When a good chip is bonded to the inspection electrode having such a needle mark to form a stacked chip, the surface flatness of the wafer is impaired due to the unevenness of the needle mark, which increases the possibility of bonding failure between the wafer and the chip.

[0129] Therefore, the inventors have created an embodiment of the present disclosure in view of this situation. Specifically, since in the case of stacked chips in the COW manner as described above, the wafer and the good chip are bonded to each other, there is an unbonded area on the wafer side where the chip is not bonded. Therefore, the inventors conceived of avoiding poor bonding between the wafer and the chip by setting an inspection electrode in the unbonded area. That is, in the embodiment of the present disclosure, since the inspection electrode for good product sorting of the wafer is set in the unbonded area relative to the chip on the wafer, even when the needle mark caused by the inspection remains in the inspection electrode, the occurrence of poor bonding between the wafer and the chip due to the needle mark can be avoided. In the following, the details of these embodiments of the present disclosure created by the inventors will be explained in sequence.

[0130] <<2. First Implementation Method>>

[0131] <2.1 Manufacturing method>

[0132] First, refer to Figures 7 to 11 A method of manufacturing the imaging device 1 according to the first embodiment of the present disclosure is described. Figures 7 to 11 1 is an explanatory diagram for explaining a method for manufacturing the imaging device 1 according to the present embodiment. Specifically, Figure 7 FIG. 2 shows a plan view of the substrate 200 during the manufacturing process of the imaging device 1. Figures 8 to 10 In FIG. 1 , a cross-sectional view of the substrate 200 during the manufacturing process of the imaging device 1 and a plan view corresponding to the cross-sectional view are shown on the lower side and the upper side, respectively. Fig.11 A cross-sectional view of the imaging device 1 during the manufacturing process of the imaging device 1 is shown.

[0133] First, if Figure 7 As shown, a substrate (first substrate) 200 formed of a wafer is manufactured. In the substrate 200, a pixel array unit 11 including a plurality of pixels 2 arranged two-dimensionally in a matrix is ​​provided on a surface (back surface 200b: see Figure 8 ) side. In addition, Figure 7 As shown, a plurality of bonding electrodes (first bonding electrodes) 202 for electrically and physically bonding the substrate 200 and the chip 400 are provided in a stacking region (first stacking region) on the front face 200a where the chip 400 is to be stacked. In addition, for example, an inspection circuit 206 for detecting wiring failure (disconnection, short circuit) and the like of the electronic circuit including the pixel array unit 11 is provided on the substrate 200. In addition, on the front face 200a of the substrate 200, an inspection electrode 204 electrically connected to the inspection circuit 206 is provided in a region other than the stacking region where the chip 400 is to be stacked.

[0134] In the present embodiment, the bonding electrode 202 is preferably made of copper (Cu) having high conductivity to ensure physical bonding and electrical connection with the chip 400. In addition, in the present embodiment, the inspection electrode 204 is also preferably made of copper because the number of processes can be reduced by simultaneously forming the inspection electrode 204 on the front face 200a when forming the bonding electrode 202.

[0135] Furthermore, in the present embodiment, the inspection circuit 206 is not limited to the inspection circuit that detects wiring defects (disconnection, short circuit) and the like of the electronic circuit including the pixel array unit 11 as described above. In the present embodiment, it is sufficient that the inspection circuit 206 is an inspection circuit that can inspect good and defective products of the electronic circuit provided on the substrate 200 side.

[0136] Next, if Figure 8 As shown, the inspection is performed by bringing the tip 700 of the inspection device into contact with the inspection electrode 204 provided on the front surface 200a of the substrate 200. Fig. 9 As shown, due to the contact of the needle tip 700, a needle mark 702 having concave and convex parts remains on the inspection electrode 204. Specifically, the needle mark 702 includes a concave part of the inspection electrode 204 caused by the needle tip 700 being pressed and a convex part which is a protrusion of the inspection electrode 204 caused by the needle tip 700 being pressed.

[0137] Next, a chip 400 to be stacked on the substrate 200 is prepared. The chip 400 has a smaller area than the substrate 200 and is provided with, for example, a logic circuit for controlling the pixel array unit 11. In addition, a plurality of bonding electrodes (second bonding electrodes) 402 (see FIG. 1 ) for electrically and physically bonding the substrate 200 and the chip 400 are provided on the surface of the chip 400 facing the substrate 200. Fig.10 ). Specifically, the bonding electrode 402 is bonded to the bonding electrode 202, thereby electrically and physically bonding the substrate 200 and the chip 400. Therefore, the bonding electrode 402 is preferably made of copper having high conductivity to ensure physical bonding and electrical connection with the substrate 200.

[0138] Next, if Fig.10 As shown, the chip 400 is bonded to the stacking area on the front face 200a where the chip 400 is to be stacked. At this time, the bonding electrode 202 and the bonding electrode 402 are bonded so that the relative position of the chip 400 with respect to the substrate 200 is accurately fixed at a predetermined position. As described above, in the present embodiment, the inspection electrode 204 is provided in the non-bonded area between the substrate 200 and the chip 400, so even when the needle mark 702 remains in the inspection electrode 204, the occurrence of poor bonding between the substrate 200 and the wafer 400 caused by the needle mark 702 can be avoided.

[0139] Next, if Fig.11 As shown in the upper part of FIG. 2 , an insulating film 500 is deposited on the front face 200a of the substrate 200 to cover the chip 400, thereby flattening the surface of the insulating film 500. The insulating film 500 may be made of, for example, an oxide film or a low dielectric material. Then, as shown in FIG. Fig.11 As shown in the middle of FIG. 5 , the substrate 200 is turned over, and the support substrate 600 is bonded to the planarized surface of the insulating film 500. Fig.11 As shown in the lower part of , a color filter 602 , an on-chip lens 604 , and the like are formed on the back surface 200 b of the substrate 200 .

[0140] <2.2 Detailed structure>

[0141] Next, we will refer to Fig.12 The detailed structure of the image forming apparatus 1 according to the present embodiment will be described. Fig.12 1 is an explanatory diagram for explaining the imaging device 1 according to the present embodiment, and specifically shows a cross-sectional view of the imaging device 1 .

[0142] like Fig.12 As shown, in the imaging device 1 according to the present embodiment, the substrate 200 includes a semiconductor layer 210 made of silicon or the like and a wiring layer 212 stacked on the semiconductor layer 210 and including wirings made of, for example, aluminum (Al) or the like and an insulating film made of an oxide film or the like. Then, the wiring layer 212 faces the chip 400.

[0143] In addition, if Fig.12 As shown, in the imaging device 1 according to the present embodiment, the pixel array unit 11 including a plurality of pixels 2 arranged two-dimensionally in a matrix is ​​provided in the semiconductor layer 210. In addition, the color filter 602, the on-chip lens 604, etc. are provided on the back surface 200b of the semiconductor layer 210 so as to correspond to the position of the pixel array unit 11.

[0144] In addition, if Fig.12 As shown, in a stacking region on the wiring layer 212 where the chip 400 having a smaller area than the substrate 200 is to be stacked, a plurality of bonding electrodes 202 for electrically and physically bonding the substrate 200 and the chip 400 are provided. In addition, the wiring layer 212 of the substrate 200 includes an inspection circuit 206. In addition, an inspection electrode 204 electrically connected to the inspection circuit 206 is provided in a region other than the stacking region on the wiring layer 212 where the chip 400 is to be stacked.

[0145] In addition, the chip 400 is provided with, for example, a logic circuit for controlling the pixel array unit 11. In addition, a plurality of bonding electrodes 402 for electrically and physically bonding the substrate 200 and the chip 400 are provided on the surface of the chip 400 facing the substrate 200.

[0146] In addition, if Fig.12 As shown, the bonding electrode 202 and the bonding electrode 402 are bonded so that the chip 400 is stacked and bonded on the wiring layer 212. Furthermore, the insulating film 500 is provided on the wiring layer 212 to cover the chip 400. Then, the supporting substrate 600 is bonded onto the insulating film 500.

[0147] In addition, if Fig.12 As shown, the external connection electrode 220 is provided inside the wiring layer 212 in the thickness direction of the wiring layer 212, and is provided in a region other than the stacking region where the chip 400 is to be stacked. The external connection electrode 220 is an electrode for connecting the imaging device 1 to an external device. In addition, the substrate 200 has a groove 230 that exposes the external connection electrode 220 from the wiring layer 212 and the semiconductor layer 210.

[0148] In this embodiment, the external connection electrode 220 is preferably made of the same material as the wiring in the wiring layer 212, and is preferably made of, for example, aluminum. In this way, since the external connection electrode 220 can be formed simultaneously with the wiring in the wiring layer 212, the increase in the number of manufacturing processes of the imaging device 1 can be suppressed.

[0149] As described above, according to this embodiment, the inspection electrode 204 is set in the unbonded area between the substrate 200 and the chip 400, so even when the needle mark 702 remains in the inspection electrode 204, the occurrence of poor bonding between the substrate 200 and the wafer 400 caused by the needle mark 702 can be avoided.

[0150] <<3. Second Implementation Plan>>

[0151] Next, we will refer to Fig.13 A detailed structure of an imaging device 1 according to a second embodiment of the present disclosure will be described. Fig.13 1 is an explanatory diagram for explaining the image forming apparatus 1 according to the present embodiment, and specifically shows a cross-sectional view of the image forming apparatus 1. Note that description of common points of the embodiments explained so far will be omitted here.

[0152] In the above first embodiment, a single chip 400 is stacked on the substrate 200, but the embodiments of the present disclosure are not limited thereto, and a plurality of chips 400 may be stacked on the substrate 200. Therefore, a second embodiment of the present disclosure in which a plurality of chips 400 are stacked on the substrate 200 will be described.

[0153] Specifically, Fig.13 As shown, a chip (third substrate) 410 stacked on the substrate 200 has an area smaller than the substrate 200. The chip 410 may be provided with, for example, a memory cell (not shown) including a memory element.

[0154] In addition, similar to the chip 400, the chip 410 is provided with a plurality of bonding electrodes (fourth bonding electrodes) 412 for electrically and physically bonding the substrate 200 and the chip 410 on the surface facing the substrate 200. In addition, on the front face 200a of the substrate 200, in a stacking region (second stacking region) where the chip 410 is to be stacked other than the stacking region where the chip 400 is to be stacked, a plurality of bonding electrodes (third bonding electrodes) 208 for electrically and physically bonding the substrate 200 and the chip 410 are provided.

[0155] In the present embodiment, the bonding electrodes 208 and 412 are preferably made of copper having high conductivity to ensure physical bonding and electrical connection between the substrate 200 and the chip 410. In this way, since the bonding electrode 208 can be formed simultaneously with the bonding electrode 202 and the inspection electrode 204, an increase in the number of manufacturing processes of the imaging device 1 can be suppressed.

[0156] Furthermore, also in the present embodiment, the inspection electrode 204 is provided in a region other than the stacking region where the chips 400 and 410 are to be stacked on the front face 200 a of the substrate 200 .

[0157] As described above, according to this embodiment, the inspection electrode 204 is arranged in the unbonded area between the substrate 200 and each of the chips 400 and 410, so even when the needle mark 702 remains in the inspection electrode 204, the occurrence of poor bonding between the substrate 200 and the chips 400 and 410 caused by the needle mark 702 can be avoided.

[0158] <<4. Third Implementation Plan>>

[0159] Next, we will refer to Fig.14 A detailed structure of an imaging device 1 according to a third embodiment of the present disclosure will be described. Fig.14 1 is an explanatory diagram for explaining the image forming apparatus 1 according to the present embodiment, and specifically shows a cross-sectional view of the image forming apparatus 1. Note that description of common points of the embodiments explained so far will be omitted here.

[0160] Although the imaging device 1 having a stacked structure of the substrate 200 and the chip 400 is described in the above-mentioned first embodiment, the embodiments of the present disclosure are not limited thereto, and a stacked structure of a plurality of substrates 200 and chips 400 stacked on each other may be adopted. Therefore, a third embodiment of the present disclosure will be described, which is an imaging device 1 having a stacking method of stacking chips by bonding wafer, wafer, and chip (WOWOC: wafer on wafer on chip).

[0161] like Fig.14As shown, in the imaging device 1 according to the present embodiment, a substrate (first semiconductor substrate) 200 formed of a wafer and a substrate (second semiconductor substrate) 300 formed of a wafer are stacked on each other. The substrate 300 may be provided with a storage unit (not shown) including a storage element, for example.

[0162] Similar to the first embodiment, the substrate 200 includes a semiconductor layer 210 and a wiring layer 212 stacked on the semiconductor layer 210 and including wiring and an insulating film. Then, the pixel array unit 11 is provided in the semiconductor layer 210, and the color filter 602, the on-chip lens 604, etc. are provided on the back side 200b of the semiconductor layer 210. In addition, as Fig.14 As shown, the external connection electrode 220 is provided inside the wiring layer 212 in the thickness direction of the wiring layer 212. In addition, the substrate 200 has a groove 230 that exposes the external connection electrode 220 from the wiring layer 212 and the semiconductor layer 210.

[0163] The substrate 300 stacked on the front face 200a side of the substrate 200 includes a semiconductor layer 310 made of silicon and two wiring layers 312 and 314 stacked on both faces of the semiconductor layer 310. Each of the wiring layers 312 and 314 includes wiring and an insulating film. The wiring layer 312 on the substrate 200 side is provided with, for example, an inspection circuit 306 for detecting wiring defects (disconnection, short circuit) and the like of the electronic circuit provided on the substrate 300. Note that the inspection circuit 306 can be electrically connected to the electronic circuit provided on the substrate 200 to detect wiring defects (disconnection, short circuit) and the like of the electronic circuit provided on the substrate 200.

[0164] In addition, if Fig.14 As shown, in the stacking region where the chip 400 is to be stacked on the wiring layer 314 on the chip 400 side, a plurality of bonding electrodes 302 for electrically and physically bonding the substrate 300 and the chip 400 are provided. In the present embodiment, the bonding electrode 302 is preferably made of copper having high conductivity to ensure physical bonding and electrical connection between the substrate 300 and the chip 410. In addition, on the wiring layer 314 on the chip 400 side, an inspection electrode 304 electrically connected to the inspection circuit 306 is provided in a region other than the stacking region where the chip 400 is to be stacked. In the present embodiment, the inspection electrode 304 is preferably made of copper. In this way, since the inspection electrode 304 can be formed simultaneously with the bonding electrode 302, an increase in the number of manufacturing processes of the imaging device 1 can be suppressed.

[0165] In addition, if Fig.14As shown, the substrate 300 includes a through electrode 320 that penetrates the wiring layer 314, the semiconductor layer 310, and the wiring layer 312. The through electrode 320 is provided to be connected to the bonding electrode 302, and electrically connects the chip 400 and the substrates 300 and 200 via the bonding electrode 402 of the chip 400. In addition, the through electrode 320 is provided to be connected to the inspection electrode 304, and electrically connects the inspection electrode 304 and the inspection circuit 306.

[0166] As described above, according to this embodiment, the inspection electrode 304 is set in the unbonded area between the substrate 300 and the chip 400, so even when the needle mark 702 remains in the inspection electrode 304, the occurrence of poor bonding between the substrate 300 and the wafer 400 caused by the needle mark 702 can be avoided.

[0167] <<5. Fourth Implementation Plan>>

[0168] Although the bonding electrode 202 and the inspection electrode 204 are disposed on the same surface (layer) in the above-mentioned first embodiment, the embodiments of the present disclosure are not limited thereto, and the bonding electrode 202 and the inspection electrode 204 may be disposed on different surfaces (layers). Therefore, a fourth embodiment of the present disclosure in which the bonding electrode 202 and the inspection electrode 204 are disposed on different surfaces will be described.

[0169] <5.1 Manufacturing method>

[0170] First, refer to Fig.15 A method of manufacturing the image forming apparatus 1 according to the present embodiment will be described. Fig.15 1 is an explanatory diagram showing a method of manufacturing the imaging device 1 according to the present embodiment, and specifically shows a cross-sectional view of the substrate 200 during the manufacturing process of the imaging device 1 .

[0171] First, if Fig.15 As shown in the upper part of , a substrate (first substrate) 200 formed of a wafer is manufactured similarly to the above-mentioned embodiments. The substrate 200 is provided with a pixel array unit 11 on the back surface 200b side. In addition, the substrate 200 is provided with an inspection circuit 206.

[0172] In addition, if Fig.15 As shown in the upper part of the figure, a plurality of auxiliary electrodes 202a for electrically bonding the substrate 200 and the chip 400 are provided in the stacking region on the front face 200a where the chip 400 is to be stacked. In addition, on the front face 200a of the substrate 200, an inspection electrode 204a electrically connected to the inspection circuit 206 is provided in the region other than the stacking region where the chip 400 is to be stacked.

[0173] In this embodiment, the auxiliary electrode 202a and the inspection electrode 204a are preferably made of the same material as the wiring in the wiring layer 212, and are preferably made of, for example, aluminum. In this way, since the auxiliary electrode 202a and the inspection electrode 204a can be formed simultaneously with the wiring in the wiring layer 212, an increase in the number of manufacturing processes of the imaging device 1 can be suppressed.

[0174] Next, if Fig.15 As shown in the upper part of FIG. 1 , the inspection is performed by bringing the needle tip 700 of the inspection device into contact with the inspection electrode 204a provided on the front surface 200a of the substrate 200. At this time, due to the contact of the needle tip 700, a needle mark having unevenness remains on the inspection electrode 204a.

[0175] Next, if Fig.15 As shown in the middle of the figure, an insulating film is further deposited to fill the needle marks and cover the auxiliary electrode 202a and the inspection electrode 204a, thereby flattening the surface of the insulating film. In addition, a plurality of bonding electrodes 202b for electrically bonding the substrate 200 and the chip 400 are formed in the stacking region on the front face 200a where the chip 400 is to be stacked. The bonding electrodes 202b are electrically connected to the above-mentioned auxiliary electrodes 202a.

[0176] Next, if Fig.15 As shown in the lower part of , the chip 400 is bonded to the stacking region on the front face 200a where the chip 400 is to be stacked. At this time, the bonding electrode 202b and the bonding electrode 402 are bonded so that the relative position of the chip 400 with respect to the substrate 200 is accurately fixed at a predetermined position.

[0177] As described above, in this embodiment, the inspection electrode 204a is not provided on the surface of the stacked chip 400, so even when the needle mark 702 remains in the inspection electrode 204a, the occurrence of poor bonding between the substrate 200 and the chip 400 caused by the needle mark 702 can be avoided.

[0178] <5.2 Detailed structure>

[0179] Next, we will refer to Fig.16 The detailed structure of the image forming apparatus 1 according to the present embodiment will be described. Fig.16 1 is an explanatory diagram for explaining the image forming apparatus 1 according to the present embodiment, and specifically shows a cross-sectional view of the image forming apparatus 1. Note that description of common points of the embodiments explained so far will be omitted here.

[0180] like Fig.16As shown, in the present embodiment, the bonding electrode 202b and the inspection electrode 204a are provided at different heights in the thickness direction of the substrate 200. Specifically, the bonding electrode 202b is provided on the surface of the wiring layer 212 of the substrate 200 facing the chip 400, and the inspection electrode 204a is provided inside the wiring layer 212 in the thickness direction of the wiring layer 212. More specifically, the inspection electrode 204a is covered with an insulating film.

[0181] Furthermore, in the present embodiment, the auxiliary electrode 202a and the inspection electrode 204a are preferably located at the same height as the external connection electrode 220 in the thickness direction of the wiring layer 212. In this way, since the auxiliary electrode 202a and the inspection electrode 204a can be formed simultaneously with the external connection electrode 220, an increase in the number of manufacturing processes of the imaging device 1 can be suppressed.

[0182] As described above, according to the present embodiment, the inspection electrode 204a is not provided on the surface of the stacked chip 400, and therefore even when the needle mark 702 remains in the inspection electrode 204a, the occurrence of poor bonding between the substrate 200 and the chip 400 caused by the needle mark 702 can be avoided. In addition, even if the surface flatness of the insulating film deposited on the inspection electrode 204a is impaired due to the needle mark 702 of the inspection electrode 204a, since the inspection electrode 204a is not provided on the surface of the stacked chip 400, the occurrence of poor bonding between the substrate 200 and the wafer 400 can be avoided.

[0183] <<6. Conclusion>>

[0184] As described above, according to the various embodiments of the present disclosure, the inspection electrode 204 is arranged in the unbonded area between the substrate 200 and the chip 400, so even when the needle mark 702 remains in the inspection electrode 204, the occurrence of poor bonding between the substrate 200 and the chip 400 caused by the needle mark 702 can be avoided.

[0185] Note that, as each embodiment of the present disclosure described above, an example in which a wafer and a chip are bonded together (COW) has been described, but the embodiments of the present disclosure are not limited thereto, and a chip and a chip may be bonded together.

[0186] In addition, the imaging device 1 according to the embodiment of the present disclosure can be manufactured by using the method, device and conditions used in manufacturing a general semiconductor device. That is, the imaging device 1 according to the present embodiment can be manufactured using the existing semiconductor device manufacturing process.

[0187] Note that examples of the above methods include physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD). Examples of PVD methods include vacuum vapor deposition, electron beam (EB) vapor deposition, various sputtering methods (magnetron sputtering, radio frequency direct current (RF-DC) coupled bias sputtering, electron cyclotron resonance (ECR) sputtering, facing target sputtering, high frequency sputtering, etc.), ion plating, laser ablation, molecular beam epitaxy (MBE), and laser transfer. In addition, examples of CVD methods include plasma CVD, thermal CVD, organometallic (MO) CVD, and optical CVD. In addition, examples of other methods include electrolytic plating, electroless plating and spin coating; dipping; casting; microcontact printing; drop casting; various printing methods such as screen printing, inkjet printing, offset printing, gravure printing and flexographic printing; imprinting; spraying; and various coating methods such as air blade coater, blade coater, rod coater, knife coater, extrusion coater, reverse roll coater, transfer roll coater, gravure coater, kiss coating, cast coating, spray coating, slit hole coating and calendar coating. In addition, examples of patterning methods include chemical etching such as shadow mask, laser transfer and photolithography; and physical etching using ultraviolet rays, lasers, etc. In addition, examples of planarization techniques include chemical mechanical polishing (CMP), laser planarization and reflow.

[0188] Note that, as each embodiment of the present disclosure described above, an example applicable to the imaging device 1 has been described, but the embodiments of the present disclosure are not limited thereto and may be applicable to other semiconductor devices.

[0189] <<7. Application Examples>>

[0190] Next, application examples of the technology of the present disclosure will be described. Fig.17 1 is a diagram showing an application example using each embodiment according to the disclosed technology. The above-mentioned imaging device 1 to which the disclosed technology is applied can be used in various cases of sensing light such as visible light, infrared light, ultraviolet light, and X-rays as follows.

[0191] - A device for taking images for viewing, which is a digital camera, a portable device with a camera function, or the like.

[0192] -Devices used for traffic, used for safe driving such as automatic stopping, identifying the driver's condition, etc., the devices are vehicle-mounted sensors that capture images of the front, rear, surroundings, interior, etc. of the vehicle, surveillance cameras that monitor moving vehicles and roads, ranging sensors that measure the distance between vehicles, etc.

[0193] - Devices for home appliances, such as televisions, refrigerators, or air conditioners, to capture images of user gestures and operate the device based on the gestures.

[0194] - A device for medical care, which is an endoscope or a device for performing angiography by receiving infrared light, etc.

[0195] - Devices used for security, such as surveillance cameras for crime prevention purposes or cameras for personal authentication, etc.

[0196] - A device for beauty care, which is a skin measuring instrument for photographing the skin or a microscope for photographing the scalp, etc.

[0197] - A device for sports, such as a sports camera or a wearable camera for sports applications, etc.

[0198] - Devices used for agriculture, such as cameras for monitoring the condition of fields or crops.

[0199] Next, an application example of the technology according to the present disclosure to a camera will be described. Fig.18 1 is a block diagram showing a configuration of an example of a camera 100 to which the technology of the present disclosure can be applied. Fig.18 , the camera 100 includes an optical unit 101, an imaging unit 102, an image processing section 103, a frame memory 104, a central processing unit (CPU) 105, a read-only memory (ROM) 106, a random access memory (RAM) 107, a memory 108, an operation unit 109, a display unit 110, and a power supply unit 111. Among them, the image processing section 103, the frame memory 104, the CPU 105, the ROM 106, the RAM 107, the memory 108, the operation unit 109, the display unit 110, and the power supply unit 111 are communicably connected to each other via a bus 120.

[0200] The memory 108 is a storage medium capable of storing data in a nonvolatile manner, and for example, a flash memory or a hard disk drive may be applicable. The CPU 105 controls the overall operation of the camera 100 using the RAM 107 as a working memory according to a program pre-stored in the ROM 106 or the memory 108 .

[0201] The operation unit 109 includes various operation means for the user to operate the camera 100, and transmits a control signal corresponding to the user's operation to the CPU 105. The display unit 110 includes a display device using a liquid crystal display (LCD) or an organic electroluminescence (EL) and a drive circuit that drives the display device. For example, the display unit 110 causes the display device to display a screen corresponding to a display signal transmitted from the CPU 105 via the bus 120. The power supply unit 111 supplies power to each unit of the camera 100.

[0202] The optical unit 101 includes one or more lenses and mechanisms such as an aperture and a focus, and causes light from a subject to be incident on the imaging unit 102. The imaging unit 102 includes pixels 2 according to the disclosed technology, and the pixel array unit 11 is irradiated with light incident from the optical unit 101. In the pixel array unit 11, each pixel 2 outputs a pixel signal corresponding to the irradiated light. The imaging unit 102 supplies image data based on the pixel signal output from each pixel 2 to the image processing unit 103.

[0203] The image processing section 103 includes, for example, a digital signal processor (DSP), and performs predetermined image processing such as white balance processing and gamma correction processing on the image data supplied from the imaging unit 102 using the frame memory 104. The image data subjected to the image processing by the image processing section 103 is stored in the memory 108, for example.

[0204] When the imaging device 1 according to the disclosed technology is applied to the imaging unit 102, the wiring formed for each pixel row or each pixel column can be inspected with a minimum of additional circuits, so that the increase in chip area can be suppressed. Therefore, using the imaging device 1 according to the disclosed technology as the imaging unit 102 can contribute to further miniaturization of the camera 100. In addition, since the first semiconductor substrate 41 can be inspected separately, the yield of the imaging device 1 can be improved, and the cost of the camera 100 can be reduced.

[0205] <<8.Supplement>>

[0206] Although the preferred embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings, the technical scope of the present disclosure is not limited to these examples. Obviously, a person with ordinary knowledge in the technical field of the present disclosure can find various changes and modifications within the scope of the technical ideas recorded in the claims, and it should be understood that these changes and modifications naturally belong to the technical scope of the present disclosure.

[0207] In addition, the effects described in this specification are only illustrative or exemplary and are not limiting. That is, in addition to or as a substitute for the above effects, the technology according to the present disclosure can show other effects that are obvious to those skilled in the art from the description of this specification.

[0208] Note that the present technology may also have the following configurations.

[0209] (1) A solid-state imaging device includes a stacked structure in which a first substrate and a second substrate having a smaller area than the first substrate are stacked, wherein:

[0210] The first substrate comprises:

[0211] an electronic circuit comprising an imaging element;

[0212] an inspection circuit configured to inspect the electronic circuit;

[0213] a first bonding electrode for electrically and physically bonding with the second substrate and provided in a first stacking region where the second substrate is to be stacked; and

[0214] an inspection electrode which is provided in a region outside the first stacking region and is electrically connected to the inspection circuit, and

[0215] The second substrate comprises:

[0216] a logic circuit that controls the imaging element; and

[0217] The second bonding electrode is used to bond with the first bonding electrode of the first substrate.

[0218] (2) The solid-state imaging device according to (1), wherein the first and second bonding electrodes contain copper.

[0219] (3) The solid-state imaging device according to (1) or (2), wherein the first bonding electrode and the inspection electrode are provided on a surface of the first substrate facing the second substrate.

[0220] (4) The solid-state imaging device according to (3), wherein the inspection electrode contains copper.

[0221] (5) The solid-state imaging device according to (1) or (2), wherein the first bonding electrode and the inspection electrode are provided at different heights in the thickness direction of the first substrate.

[0222] (6) The solid-state imaging device according to (5), wherein the inspection electrode contains aluminum.

[0223] (7) The solid-state imaging device according to any one of (1) to (3), further including a third substrate having a smaller area than the first substrate and stacked on the first substrate, wherein

[0224] The first substrate includes

[0225] a third bonding electrode for electrically and physically bonding with the third substrate and provided in a second stacking region outside the first stacking region on which the third substrate is to be stacked,

[0226] The third substrate includes

[0227] A fourth bonding electrode for bonding with the third bonding electrode of the first substrate and the inspection electrode are provided in a region other than the second stacking region.

[0228] (8) The solid-state imaging device according to (1) or (2), wherein

[0229] The first substrate comprises:

[0230] a semiconductor layer; and

[0231] A wiring layer is provided on the semiconductor layer.

[0232] (9) The solid-state imaging device according to (8), wherein the first bonding electrode and the inspection electrode are provided on a surface of the wiring layer that faces the second substrate.

[0233] (10) The solid-state imaging device according to (8), wherein

[0234] A first bonding electrode is provided on a surface of the wiring layer facing the second substrate, and

[0235] The inspection electrode is provided inside the wiring layer in a thickness direction of the wiring layer.

[0236] (11) The solid-state imaging device according to (10), wherein

[0237] The first substrate comprises:

[0238] an external connection electrode provided in a region other than the first stacking region inside the wiring layer in a thickness direction of the wiring layer; and

[0239] A groove is formed to expose the external connection electrode from the wiring layer and the semiconductor layer.

[0240] (12) The solid-state imaging device according to (11), wherein

[0241] The external connection electrode is located at the same height as the inspection electrode in the thickness direction of the wiring layer.

[0242] (13) The solid-state imaging device according to (1) or (2), wherein

[0243] The first substrate comprises:

[0244] a first semiconductor substrate including the imaging element; and

[0245] a second semiconductor substrate stacked on the first semiconductor substrate,

[0246] The first bonding electrode is provided on a surface of the second semiconductor substrate facing the second substrate, and

[0247] The second substrate and the first semiconductor substrate are electrically connected via a through electrode penetrating the second semiconductor substrate.

[0248] (14) The solid-state imaging device according to (13), wherein

[0249] The first semiconductor substrate includes the inspection circuit,

[0250] The inspection electrode is provided on a surface of the second semiconductor substrate facing the second substrate, and

[0251] The inspection electrode and the inspection circuit are electrically connected via the through-electrode.

[0252] (15) The solid-state imaging device according to (13) or (14), wherein the second semiconductor substrate includes a memory element.

[0253] (16) The solid-state imaging device according to any one of (1) to (15), further including an insulating film covering the second substrate stacked in the first stacking region.

[0254] (17) The solid-state imaging device according to any one of (1) to (16), further including an on-chip lens provided on a surface of the first substrate opposite to a surface facing the second substrate.

[0255] (18) The solid-state imaging device according to any one of (1) to (17), wherein the first substrate includes a pixel array unit including a plurality of the imaging elements two-dimensionally arranged in a matrix.

[0256] (19) The solid-state imaging device according to any one of (1) to (18), wherein the inspection circuit is an inspection circuit that detects a wiring defect in the electronic circuit.

[0257] (20) A semiconductor device comprising a stacked structure including a first substrate and a second substrate having a smaller area than the first substrate, wherein:

[0258] The first substrate comprises:

[0259] Electronic circuits;

[0260] an inspection circuit configured to inspect the electronic circuit;

[0261] a first bonding electrode for electrically and physically bonding with the second substrate and provided in a first stacking region where the second substrate is to be stacked; and

[0262] an inspection electrode which is provided in a region outside the first stacking region and is electrically connected to the inspection circuit, and

[0263] The second substrate includes a second bonding electrode for bonding with the first bonding electrode of the first substrate.

[0264] Reference numerals list

[0265] 1 Imaging device

[0266] 2 pixels

[0267] 11 Pixel Array Unit

[0268] 12 row selection unit

[0269] 13 Constant current source unit

[0270] 14 Analog-to-digital conversion unit

[0271] 15 Horizontal transfer scanning unit

[0272] 16 Signal Processing Unit

[0273] 17 Timing control unit

[0274] 18 Horizontal transmission lines

[0275] 19 Reference signal generating unit

[0276] 21 Photodiode

[0277] 22 Pass transistor

[0278] 23 Reset transistor

[0279] 24 Amplifier transistor

[0280] 25 Select transistor

[0281] 31 vertical signal line

[0282] 32 control lines

[0283] 41, 41a first semiconductor substrate

[0284] 42 second semiconductor substrate

[0285] 43, 44 Connection

[0286] 45 Check the circuit

[0287] 46 Bias Unit

[0288] 47, 48, 49, 50 Electrodes

[0289] 100 Camera

[0290] 101 Optical Unit

[0291] 102 Imaging Unit

[0292] 103 Image Processing Department

[0293] 104 Frame Memory

[0294] 105 CPU

[0295] 106 ROM

[0296] 107 RAM

[0297] 108 Memory

[0298] 109 Operating unit

[0299] 110 Display unit

[0300] 111 Power supply unit

[0301] 120 Bus

[0302] 140 Single Slope ADC

[0303] 141 Comparator

[0304] 142 Counting Circuit

[0305] 143 Latch Circuit

[0306] 200, 300 substrates

[0307] 200a front

[0308] 200b Back

[0309] 202, 202b, 208, 302, 402, 412 Bonding electrodes

[0310] 202a Auxiliary electrode

[0311] 204, 204a, 304 Check electrodes

[0312] 206, 306 Check the circuit

[0313] 210, 310 Semiconductor layer

[0314] 212, 312, 314 wiring layer

[0315] 220 External connection electrode

[0316] 230 Groove

[0317] 320 Through Electrode

[0318] 400, 410 chips

[0319] 500 Insulation Film

[0320] 600 Support substrate

[0321] 602 Color Filter

[0322] 604 On-chip lens

[0323] 700 Needle Tip

[0324] 702 Needle Mark

Claims

1. A solid-state imaging device, comprising a stacked structure including a first substrate and a second substrate having a smaller area than the first substrate, wherein: The first substrate comprises: an electronic circuit comprising an imaging element; an inspection circuit configured to inspect the electronic circuit; a first bonding electrode for electrically and physically bonding with the second substrate and provided in a first stacking region where the second substrate is to be stacked; and an inspection electrode which is provided in a region outside the first stacking region and is electrically connected to the inspection circuit, and The second substrate comprises: a logic circuit that controls the imaging element; and The second bonding electrode is used to bond with the first bonding electrode of the first substrate.

2. The solid-state imaging device according to claim 1, wherein The first and second bonding electrodes include copper.

3. The solid-state imaging device according to claim 1, wherein The first bonding electrode and the inspection electrode are provided on a surface of the first substrate facing the second substrate.

4. The solid-state imaging device according to claim 3, wherein The inspection electrode includes copper.

5. The solid-state imaging device according to claim 1, wherein The first bonding electrode and the inspection electrode are provided at different heights in the thickness direction of the first substrate.

6. The solid-state imaging device according to claim 5, wherein The inspection electrode includes aluminum.

7. The solid-state imaging device according to claim 1, further comprising a third substrate having a smaller area than the first substrate and stacked on the first substrate, wherein The first substrate includes a third bonding electrode for electrically and physically bonding with the third substrate and provided in a second stacking region outside the first stacking region on which the third substrate is to be stacked, The third substrate includes a fourth bonding electrode for bonding with the third bonding electrode of the first substrate, and The inspection electrode is provided in a region other than the second stacking region.

8. The solid-state imaging device according to claim 1, wherein The first substrate comprises: a semiconductor layer; and A wiring layer is provided on the semiconductor layer.

9. The solid-state imaging device according to claim 8, wherein The first bonding electrode and the inspection electrode are provided on the surface of the wiring layer facing the second substrate.

10. The solid-state imaging device according to claim 8, wherein A first bonding electrode is provided on a surface of the wiring layer facing the second substrate, and The inspection electrode is provided inside the wiring layer in a thickness direction of the wiring layer.

11. The solid-state imaging device according to claim 10, wherein The first substrate comprises: an external connection electrode provided in a region other than the first stacking region inside the wiring layer in a thickness direction of the wiring layer; and A groove is formed to expose the external connection electrode from the wiring layer and the semiconductor layer.

12. The solid-state imaging device according to claim 11, wherein The external connection electrode is located at the same height as the inspection electrode in the thickness direction of the wiring layer.

13. The solid-state imaging device according to claim 1, wherein The first substrate comprises: a first semiconductor substrate including the imaging element; and a second semiconductor substrate stacked on the first semiconductor substrate, The first bonding electrode is provided on a surface of the second semiconductor substrate facing the second substrate, and The second substrate and the first semiconductor substrate are electrically connected via a through electrode penetrating the second semiconductor substrate.

14. The solid-state imaging device according to claim 13, wherein The first semiconductor substrate includes the inspection circuit, The inspection electrode is provided on a surface of the second semiconductor substrate facing the second substrate, and The inspection electrode and the inspection circuit are electrically connected via the through-electrode.

15. The solid-state imaging device according to claim 13, wherein The second semiconductor substrate includes a memory element. 16 . The solid-state imaging device according to claim 1 , further comprising an insulating film covering the second substrate stacked in the first stacking region. 17 . The solid-state imaging device according to claim 1 , further comprising an on-chip lens provided on a surface of the first substrate opposite to a surface facing the second substrate.

18. The solid-state imaging device according to claim 1, wherein The first substrate includes a pixel array unit, and the pixel array unit includes a plurality of imaging elements arranged two-dimensionally in a matrix.

19. The solid-state imaging device according to claim 1, wherein The inspection circuit is an inspection circuit for detecting a wiring defect in the electronic circuit.

20. A semiconductor device comprising a stacked structure including a first substrate and a second substrate having a smaller area than the first substrate, wherein: The first substrate comprises: Electronic circuits; an inspection circuit configured to inspect the electronic circuit; a first bonding electrode for electrically and physically bonding with the second substrate and provided in a first stacking region where the second substrate is to be stacked; and an inspection electrode which is provided in a region outside the first stacking region and is electrically connected to the inspection circuit, and The second substrate includes a second bonding electrode for bonding with the first bonding electrode of the first substrate.

Images