Method for fabricating solid-state nanopore array and solid-state nanopore array device and application thereof

Abstract

The application provides a preparation method and application of a solid-state nanopore array and a solid-state nanopore array device, which comprises the following steps: forming first and second direction nanometer strips in a first and a second film layer and a third and a fourth film layer by combining a film coating process and an etching process, and then performing selective etching at the intersection of the first and second nanometer strips, so as to form a required solid-state nanopore array in a functional material layer. Compared with the existing method for preparing a solid-state nanopore array, the preparation method has the advantages of rapid and efficient large-area preparation, low cost and the like, and the pore diameter and array size of the formed solid-state nanopore can be accurately controlled by adjusting process parameters. In addition, the preparation method is suitable for various solid materials and is fully compatible with the existing CMOS process technology, so that large-scale manufacturing of the solid-state nanopore array device can be realized. In addition, the solid-state nanopore array device can be used for high-throughput analysis and detection of electrochemical signals and biological molecules such as DNA or protein.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of micro-nano structure preparation, in particular to a preparation method and application of a solid-state nanopore array and a solid-state nanopore array device. BACKGROUND

[0002] Solid-state nanopore arrays have wide applications in the field of nanotechnology and nanoscience, especially in the fields of nano-electronics, nano-biology, nano-sensors, etc. For example, they can be used as components of single-molecule biosensors, and through controlling the size and chemical properties of the pores, high-sensitivity detection of biological molecules (such as DNA, proteins, etc.) can be achieved. In addition, solid-state nanopore arrays can also be used in the fields of nanofluidic hydrodynamics, nanofiltration membranes, nano-electronic devices, etc.

[0003] In 2001, researchers at Harvard University used focused ion beam (FIB) to process the first solid-state nanopore on a SiNx film. In 2003, Storm used the electron beam of a transmission electron microscope (TEM) to prepare a nanopore with a pore size of about 20 nm on a 30 nm thick silicon oxide film. However, both FIB and TEM methods face the problems of high cost and low processing efficiency in the process of processing solid-state nanopores. As the main method for processing solid-state nanopores at present, electron beam lithography (EBL) can realize small-scale nanopore arrays, and relying on semiconductor basic processes makes it highly reproducible, but it still has the problems of high cost and low efficiency.

[0004] In order to solve the cost problem, researchers have considered using electrochemical methods, such as dielectric breakdown (CBD) method or electrochemical etching method to prepare nanopore arrays. However, the dielectric breakdown (CBD) method cannot determine the position of the nanopore distribution, and the electrochemical etching method cannot realize the processing demand of controllable scale of nanopore arrays. Other methods such as chemical etching or metal-assisted chemical etching cannot realize the preparation of nanopore arrays with controllable scale, size and shape. The device of laser etching process is also relatively complex, and the nanopore array prepared by the nanobubble-based electrodeposition method has uneven geometry, size and distribution of nanopores, which is difficult to control, and the method of using AFM to process nanopores has low success rate and poor repeatability.

[0005] Therefore, how to develop a solid-state nanopore array with low cost, mass production, controllable size and shape, and controllable array scale, as well as a process of solid-state nanopore array device has become a challenge. SUMMARY

[0006] In view of the above-mentioned disadvantages of the prior art, the purpose of the present application is to provide a solid-state nanopore array and a preparation method and application of a solid-state nanopore array device, which are used to solve the problems of high cost, low efficiency, inability to achieve large-scale preparation, uneven geometry, size and distribution of nanopores, and poor repeatability in the preparation process of the solid-state nanopore array in the prior art.

[0007] To achieve the above-mentioned purpose and other related purposes, the present application provides a preparation method of a solid-state nanopore array, comprising the following steps:

[0008] S1: providing a substrate, and forming a functional material layer requiring nanopore preparation on the front surface of the substrate;

[0009] S2: performing a deposition process on the functional material layer to form a first thin film layer;

[0010] S3: performing first dry etching on the first thin film layer in a first direction of the first thin film layer to form a plurality of first grooves;

[0011] S4: performing a deposition process on the first thin film layer to form a first sacrificial layer, the first sacrificial layer covering the bottom and sidewall of the first groove and the top of the first thin film layer, and etching to remove the first sacrificial layer covering the bottom of the first groove and the top of the first thin film layer;

[0012] S5: forming a second thin film layer on the first thin film layer, the second thin film layer covering the bottom of the first groove and the second thin film layer having the same height as the first thin film layer, so that the first sacrificial layer is exposed as a first nanostrip;

[0013] S6: performing a deposition process on the first thin film layer and the second thin film layer to form a third thin film layer, and performing second dry etching on the third thin film layer in a second direction of the third thin film layer to form a plurality of second grooves;

[0014] S7: performing a deposition process on the third thin film layer to form a second sacrificial layer, the second sacrificial layer covering the bottom and sidewall of the second groove and the top of the third thin film layer, and etching to remove the second sacrificial layer covering the bottom of the second groove and the top of the third thin film layer;

[0015] S8: forming a fourth thin film layer on the third thin film layer, the fourth thin film layer covering the bottom of the second groove and the fourth thin film layer having the same height as the third thin film layer, so that the second sacrificial layer is exposed as a second nanostrip;

[0016] S9: performing etching at the intersection of the first nanostrip and the second nanostrip to form a first etching cavity;

[0017] S10: performing dry etching on the functional material layer based on the first etching cavity to form a solid nanopore array in the functional material layer.

[0018] Optionally, after forming the solid nanopore array in the functional material layer, the method further comprises a step of removing the first thin film layer, the second thin film layer, the third thin film layer, the fourth thin film layer, the first nanometer strip and the second nanometer strip.

[0019] Optionally, an included angle θ between the first direction and the second direction ranges from 0 < θ < 180°.

[0020] Optionally, the deposition process is one of physical vapor deposition, chemical vapor deposition or atomic layer deposition.

[0021] Optionally, the first sacrificial layer comprises at least one of silicon oxide, hafnium oxide, titanium nitride, magnesium oxide, zinc oxide and aluminum oxide, and the second sacrificial layer comprises at least one of silicon oxide, hafnium oxide, titanium nitride, magnesium oxide, zinc oxide and aluminum oxide.

[0022] Optionally, the material of the functional material layer comprises at least one of metal, non-metal, metal compound and non-metal compound thin film, and a thickness d of the functional material layer ranges from 0 < d ≤ 1 μm.

[0023] Optionally, the material of the first thin film layer is consistent with that of the second thin film layer, and the material of the third thin film layer is consistent with that of the fourth thin film layer.

[0024] Optionally, an etching depth of the dry etching on the functional material layer is not less than the thickness of the functional material layer.

[0025] The application further provides a preparation method of a solid nanopore array device, which comprises the following steps:

[0026] S101: providing a substrate, forming a functional material layer, in which a nanopore is needed to be prepared, on a front surface of the substrate, and forming a mask layer on a back surface of the substrate;

[0027] S102: performing a deposition process on the functional material layer to form a first thin film layer;

[0028] S103: performing first dry etching on the first thin film layer along a first direction of the first thin film layer to form a plurality of first grooves;

[0029] S104: performing a deposition process on the first thin film layer to form a first sacrificial layer covering the bottom and sidewall of the first recess and the top of the first thin film layer, and etching the first sacrificial layer covering the bottom of the first recess and the top of the first thin film layer;

[0030] S105: forming a second thin film layer on the first thin film layer, the second thin film layer covering the bottom of the first recess and the second thin film layer having the same height as the first thin film layer, so that the first sacrificial layer is exposed as a first nano strip;

[0031] S106: performing a deposition process on the first thin film layer and the second thin film layer to form a third thin film layer, and performing a second dry etching on the third thin film layer along a second direction of the third thin film layer to form a plurality of second recesses;

[0032] S107: performing a deposition process on the third thin film layer to form a second sacrificial layer covering the bottom and sidewall of the second recess and the top of the third thin film layer, and etching the second sacrificial layer covering the bottom of the second recess and the top of the third thin film layer;

[0033] S108: forming a fourth thin film layer on the third thin film layer, the fourth thin film layer covering the bottom of the second recess and the fourth thin film layer having the same height as the third thin film layer, so that the second sacrificial layer is exposed as a second nano strip;

[0034] S109: performing a deposition process on the third thin film layer and the fourth thin film layer to form a first patterned layer, the first patterned layer having a plurality of third recesses, and the third recesses exposing a window region;

[0035] S110: performing an etching process on the intersection of the first nano strip and the second nano strip in the window region to form a second etching cavity;

[0036] S111: performing a dry etching on the functional material layer at the window region based on the second etching cavity to form a solid nanopore array;

[0037] S112: performing a registration process on the back surface of the substrate, and etching the substrate and the mask layer using an etching process to expose the solid nanopore array of the window region;

[0038] S113: removing the first thin film layer, the second thin film layer, the third thin film layer, the fourth thin film layer, the first nano strip, the second nano strip, and the first patterned layer to form the solid nanopore array device.

[0039] Optionally, an angle θ between the first direction and the second direction ranges from 0 < θ < 180°.

[0040] Optionally, the material forming the functional material layer comprises at least one of a metal, a non-metal, a metal compound and a non-metal compound thin film, and a thickness d of the functional material layer ranges from 0 < d ≤ 1 μm.

[0041] Optionally, the first sacrificial layer comprises at least one of silicon oxide, hafnium oxide, titanium nitride, magnesium oxide, zinc oxide and aluminum oxide, and the second sacrificial layer comprises at least one of silicon oxide, hafnium oxide, titanium nitride, magnesium oxide, zinc oxide and aluminum oxide.

[0042] Optionally, the first thin film layer and the second thin film layer are of the same material, and the third thin film layer and the fourth thin film layer are of the same material.

[0043] Optionally, a dry etching depth of the functional material layer is not less than a thickness of the functional material layer.

[0044] The application further provides a solid-state nanopore array device prepared by the method.

[0045] The application further provides an application of the solid-state nanopore array device in electrochemical signal analysis, high-throughput analysis and detection of biological molecules such as DNA and proteins.

[0046] As described above, the solid-state nanopore array, the preparation method of the solid-state nanopore array device and the application thereof have the following beneficial effects: the preparation method of the solid-state nanopore array combines deposition process film plating and dry etching process to form first nanometer strips along a first direction in a first thin film layer and a second thin film layer, form second nanometer strips along a second direction in a third thin film layer and a fourth thin film layer, and then perform selective etching at intersection points of the first nanometer strips and the second nanometer strips, so as to form a required solid-state nanopore array pattern in a functional material layer. Compared with existing FIB, EBL, TEM and CBD methods, the preparation method has advantages of rapid efficiency, large-area preparation and low cost, and can accurately control a pore size and an array scale of the formed nanopore through process parameter adjustment and has high repeatability. The preparation method of the solid-state nanopore array device based on the solid-state nanopore array can be applied to various solid materials and is fully compatible with existing CMOS process technology, so that large-scale integrated manufacturing of the solid-state nanopore array device is realized, thereby significantly reducing preparation cost. In addition, the solid-state nanopore array device can also realize high-throughput analysis and detection of electrochemical signals and biological molecules such as DNA or proteins. BRIEF DESCRIPTION OF DRAWINGS

[0047] Figure 1 A flow chart showing a preparation method of a solid nanopore array in an embodiment of the present application.

[0048] Figure 2 A structural diagram showing a structure after forming a substrate and a functional material layer in a solid nanopore array in an embodiment of the present application.

[0049] Figure 3 A structural diagram showing a structure after forming a first thin film layer in a solid nanopore array in an embodiment of the present application.

[0050] Figure 4 A structural diagram showing a structure after forming a first groove in a solid nanopore array in an embodiment of the present application.

[0051] Figure 5 A structural diagram showing a structure after forming a first sacrificial layer in a solid nanopore array in an embodiment of the present application.

[0052] Figure 6 A structural diagram showing a structure after forming a second thin film layer in a solid nanopore array in an embodiment of the present application.

[0053] Figure 7 A structural diagram showing a structure after forming a third thin film layer in a solid nanopore array in an embodiment of the present application.

[0054] Figure 8 A structural diagram showing a structure after forming a second groove and a second sacrificial layer in a solid nanopore array in an embodiment of the present application.

[0055] Figure 9 A structural diagram showing a structure after forming a fourth thin film layer in a solid nanopore array in an embodiment of the present application.

[0056] Figure 10 A structural diagram showing a structure after forming a first etching cavity in a solid nanopore array in an embodiment of the present application.

[0057] Figure 11 A structural diagram showing a structure of a solid nanopore array in an embodiment of the present application.

[0058] Figure 12 A flow chart showing a preparation method of a solid nanopore array device in an embodiment of the present application.

[0059] Figure 13 A structural diagram showing a structure after forming a mask layer in a solid nanopore array device in an embodiment of the present application.

[0060] Figure 14A structure schematic diagram after forming a first patterning layer in a solid nanopore array device in an embodiment of the present application is shown.

[0061] Figure 15 A structure schematic diagram after forming a second etching cavity in a solid nanopore array device in an embodiment of the present application is shown.

[0062] Figure 16 A structure schematic diagram after forming a nanopore in a solid nanopore array device in an embodiment of the present application is shown.

[0063] Figure 17 A structure schematic diagram after forming an etching groove in a solid nanopore array device in an embodiment of the present application is shown.

[0064] Figure 18 A structure schematic diagram of a solid nanopore array device in an embodiment of the present application is shown.

[0065] Figure 19 A structure schematic diagram of a single-hole / dual-hole solid nanopore array device in an embodiment of the present application when performing a conductivity test and a biomolecule detection analysis is shown.

[0066] Figure 20 A schematic diagram of a conductivity result of a single-hole / dual-hole solid nanopore array device in an embodiment of the present application is shown.

[0067] Figure 21 A schematic diagram of a current-time relationship of a single-hole / dual-hole solid nanopore array device in an embodiment of the present application is shown.

[0068] Figure 22 A signal statistics schematic diagram of a single-hole / dual-hole solid nanopore array device in an embodiment of the present application is shown.

[0069] BRIEF DESCRIPTION OF DRAWINGS

[0070] 10, substrate; 11, functional material layer; 12, first thin film layer; 13, first recess; 14, first sacrificial layer; 15, second thin film layer; 16, third thin film layer; 17, second recess; 18, second sacrificial layer; 19, fourth thin film layer; 20, first etching cavity; 21, nanopore array; 22, mask layer; 23, first patterning layer; 24, window region; 25, second etching cavity; 26, etching groove; S1-S10, steps; S101-S113, steps. DETAILED DESCRIPTION

[0071] Following along with the specific examples below, one skilled in the art can easily obtain a comprehensive understanding of other advantages and functions of the present application from the disclosure herein. The present application can also be implemented or applied in other different specific embodiments, and various modifications or changes can be made to the details herein based on different perspectives and applications without departing from the spirit of the present application.

[0072] For the convenience of description, spatial relationship words such as "under", "below", "lower", "underneath", "above", "upper" and the like can be used herein to describe the relationship of one element or feature to other elements or features shown in the drawings. It will be understood that these spatial relationship words are intended to include other orientations of the device in use or operation in addition to the orientations depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers can also be present.

[0073] It needs to be understood that the use of words such as "first", "second" and the like to define parts is only for the convenience of distinguishing the above-mentioned parts, and the above-mentioned words have no special meaning unless otherwise stated, and therefore cannot be understood as a limitation on the scope of protection of the present application.

[0074] Embodiment 1

[0075] The embodiment of the present application provides a preparation method of a solid nanopore array, as shown in the figure, which shows a process flow chart of the preparation method of the solid nanopore array, comprising the following steps: Figure 1 The embodiment of the present application provides a preparation method of a solid nanopore array, as shown in the figure, which shows a process flow chart of the preparation method of the solid nanopore array, comprising the following steps:

[0076] S1: providing a substrate, and forming a functional material layer requiring to be prepared with a nanopore on the front surface of the substrate;

[0077] S2: performing a deposition process on the functional material layer to form a first thin film layer;

[0078] S3: performing a first dry etching on the first thin film layer in a first direction of the first thin film layer to form a plurality of first grooves;

[0079] S4: performing a deposition process on the first thin film layer to form a first sacrificial layer, the first sacrificial layer covering the bottom and sidewall of the first groove and the top of the first thin film layer, and etching to remove the first sacrificial layer covering the bottom of the first groove and the top of the first thin film layer;

[0080] S5: forming a second thin film layer on the first thin film layer, the second thin film layer covering the bottom of the first groove and the second thin film layer having the same height as the first thin film layer, so as to expose the first sacrificial layer as a first nanobelt;

[0081] S6: performing a deposition process on the first thin film layer and the second thin film layer to form a third thin film layer, and performing a second dry etching on the third thin film layer along a second direction of the third thin film layer to form a plurality of second grooves;

[0082] S7: performing a deposition process on the third thin film layer to form a second sacrificial layer, the second sacrificial layer covering the bottom and sidewall of the second grooves and the top of the third thin film layer, and etching to remove the second sacrificial layer covering the bottom of the second grooves and the top of the third thin film layer;

[0083] S8: forming a fourth thin film layer on the third thin film layer, the fourth thin film layer covering the bottom of the second grooves and the fourth thin film layer having the same height as the third thin film layer, so as to expose the second sacrificial layer as a second nano strip;

[0084] S9: performing an etching process at the intersection of the first nano strip and the second nano strip to form a first etching cavity;

[0085] S10: performing a dry etching on the functional material layer based on the first etching cavity to form a solid-state nanopore array in the functional material layer.

[0086] The preparation method of the solid-state nanopore array will be further described below with reference to the accompanying drawings, and it should be noted that the above sequence does not strictly represent the preparation method of the solid-state nanopore array protected by the present application, and the skilled in the art can change the actual preparation steps, as follows:

[0087] In step S1, please refer to Figure 1 and Figure 2 , a substrate is provided, and a functional material layer in which a nanopore needs to be prepared is formed on the front surface of the substrate.

[0088] Specifically, as Figure 2As shown in the embodiment of the present application, a substrate is provided, the substrate has a front surface and a back surface arranged oppositely, and the material of the substrate can be a silicon-based material, which can be in a circular, square or any other desired shape. In addition, the material of the substrate can also include other elemental semiconductors (such as germanium), or other compound semiconductors (such as silicon carbide, gallium arsenide, indium arsenide, indium phosphide, etc.), which are not particularly limited here. The substrate is placed in an ultrasonic cleaning machine, the liquid in the ultrasonic cleaning machine is an ethanol solution with a volume fraction of 60% to 75%, and the ultrasonic cleaning time is 5 minutes to 15 minutes, so as to ensure that the stains on the substrate can be effectively removed. Then, the glass is rinsed with deionized water, the water temperature is controlled at 25°C to 45°C, and then the substrate 10 is subjected to multi-angle air blowing drying treatment, so as to form a functional material layer on the surface of the substrate, so that the nano-pores formed subsequently are distributed in the functional material layer.

[0089] As an example, the material forming the functional material layer includes at least one of a metal, a non-metal, a metal compound and a non-metal compound thin film, and the thickness d of the functional material layer is in a range of 0 < d ≤ 1 μm.

[0090] Specifically, the material of the functional material layer can be a semiconductor material, such as silicon oxide, silicon nitride and the like, or a metal material, such as a metal chromium and copper and the like. In order to ensure the quality of the solid nano-pore array formed, the thickness of the functional material layer should not be greater than the diameter of the nano-pores formed, and in the embodiment, the thickness d of the functional material layer is in a range of 0 < d ≤ 1 μm, for example, can be 0.1 μm, 0.3 μm, 0.5 μm or 1 μm, of course, the range of the thickness d of the functional material layer is not limited to this, and can be set according to actual needs.

[0091] In step S2, referring to Figure 1 and Figure 3 , a deposition process is performed on the functional material layer to form a first thin film layer.

[0092] Specifically, as shown in Figure 3 , one of physical vapor deposition, chemical vapor deposition or atomic layer deposition is used to form the first thin film layer on the functional material layer, and preferably, the process for forming the first thin film layer is a chemical vapor deposition process; the material of the first thin film layer includes polysilicon or other suitable materials such as silicon oxide, and of course, the material of the first thin film layer is not limited to this. In the embodiment, the material of the first thin film layer is preferably polysilicon, and it should be noted that the first thin film layer is used as a mask for forming a solid nano-pore array, and will be removed in subsequent processes. The thickness of the first thin film layer needs to be determined according to the thickness of the functional material layer and the etching selectivity ratio of the material used when etching to form the solid nano-pore array, and the specific range is not limited here.

[0093] In step S3, referring to Figure 1 and Figure 4 , a first dry etching is performed on the first thin film layer along the first direction of the first thin film layer to form a plurality of first grooves.

[0094] As an example, the method of forming the plurality of first grooves includes dry etching or other suitable methods; specifically, in the present embodiment, the method of forming the plurality of first grooves includes: after growing the first thin film layer, disposing a photoresist mask layer on the first thin film layer, exposing and developing the photoresist mask layer, patterning the photoresist mask layer corresponding to the positions of the first grooves, as shown in Figure 4 , etching the first thin film layer along the first direction of the first thin film layer through the patterned photoresist mask layer to obtain a plurality of first grooves penetrating through the first thin film layer to expose the functional material layer, and then removing the photoresist mask layer.

[0095] As an example, the plurality of first grooves are arranged in parallel, the shape of the plurality of first grooves is designed as a strip shape as shown in Figure 4 , and there is a certain distance between adjacent grooves, for example, which can be 1 μm, 5 μm, 8 μm or 10 μm, and the arrangement period of the plurality of first grooves ultimately determines the density and scale of the solid nanopore array, so the distance between adjacent grooves can be designed according to the required density of the solid nanopore array, which is not particularly limited here.

[0096] In step S4, referring to Figure 1 and Figure 5 , a deposition process is performed on the first thin film layer to form a first sacrificial layer, the first sacrificial layer covers the bottom and sidewall of the first grooves and the top of the first thin film layer, and the first sacrificial layer covering the bottom of the first grooves and the top of the first thin film layer is etched and removed.

[0097] As an example, one of physical vapor deposition, chemical vapor deposition or atomic layer deposition is used to form the first sacrificial layer on the first thin film layer, preferably, the process of forming the first sacrificial layer is an atomic layer deposition process; the material of the first sacrificial layer includes at least one of silicon oxide, hafnium oxide, titanium nitride, magnesium oxide, zinc oxide, aluminum oxide, of course, the material of the first sacrificial layer is not limited to this, but in order to distinguish from the first thin film layer, in the present embodiment, the material of the first sacrificial layer is preferably aluminum oxide. The thickness of the first sacrificial layer generally needs to be consistent with the diameter of the formed nanopore, of course, the thickness of the first sacrificial layer is not limited to this, and can be set according to actual needs.

[0098] In step S5, referring to Figure 1 and Figure 6, the second film layer covers the bottom of the first recess and the top of the first film layer, and then a CMP process is performed on the top of the first film layer, so that the second film layer at the bottom of the first recess has the same height as the first film layer, and the first sacrificial layer is exposed as a first nanometer strip.

[0099] As an example, the second film layer is formed on the first film layer by using one of physical vapor deposition, chemical vapor deposition or atomic layer deposition, preferably, in the embodiment, the process of forming the second film layer is a chemical vapor deposition process; the material of the second film layer includes polysilicon or other suitable materials such as silicon oxide, and in the embodiment, the material of the second film layer is preferably consistent with the material of the first film layer, so as to facilitate removal in subsequent processes. Of course, the material of the first film layer is not limited thereto, and can be set according to actual needs.

[0100] Specifically, as shown in Figure 6 , the formed second film layer covers the bottom of the first recess and the top of the first film layer, and then a CMP process is performed on the top of the first film layer, so that the second film layer at the bottom of the first recess has the same height as the first film layer, and the first sacrificial layer is exposed as a first nanometer strip. That is, the first sacrificial layer on the sidewall of the first recess is covered by the first film layer and the second film layer, and the surfaces of the first sacrificial layer, the first film layer and the second film layer are uniform and flat, which is beneficial to improve the yield of the formed solid nanopore array.

[0101] In other embodiments, the process of forming the second film layer in step S5 can also be replaced by spin-coating a flowable material, for example, spin-coating SOG (spin on glass coating) or H-SiOx material in the first recess, and then performing an annealing process or a high-temperature heating process to form a hard material layer, which is uniform and flat with the surfaces of the first sacrificial layer and the first film layer, and the exposed first sacrificial layer is a first nanometer strip.

[0102] In step S6, please refer to Figure 1 and Figure 7 , a deposition process is performed on the first film layer and the second film layer to form a third film layer, and a second dry etching is performed on the third film layer along a second direction of the third film layer to form a plurality of second recesses.

[0103] Specifically, the third thin film layer is formed on the first thin film layer and the second thin film layer by using one of physical vapor deposition, chemical vapor deposition or atomic layer deposition, and preferably, the process of forming the third thin film layer is a chemical vapor deposition process; the material of the third thin film layer includes polysilicon or other suitable materials such as silicon oxide, and of course, the material of the third thin film layer is not limited to this. In this embodiment, the material of the third thin film layer is preferably polysilicon. The thickness of the third thin film layer can be consistent with the thickness of the first thin film layer, and the specific thickness is not limited here. It should be noted that the third thin film layer also serves as a mask for the subsequent formation of the solid nanopore array, and the third thin film layer also needs to be removed in the subsequent process.

[0104] As an example, the method of forming the plurality of second grooves includes dry etching or other suitable methods; specifically, in this embodiment, the method of forming the plurality of second grooves includes: after growing the third thin film layer, disposing a photoresist mask layer on the third thin film layer, exposing and developing the photoresist mask layer, patterning the photoresist mask layer corresponding to the positions of the second grooves, as shown in Figure 7 , etching the third thin film layer along the second direction of the third thin film layer through the patterned photoresist mask layer to obtain a plurality of second grooves penetrating through the third thin film layer to expose the first thin film layer and the first sacrificial layer, and then removing the photoresist mask layer.

[0105] As an example, the plurality of second grooves are arranged in parallel, the shape of the plurality of second grooves is designed as a strip shape as shown in Figure 7 , and there is a certain distance between adjacent grooves, and the period of the plurality of second grooves ultimately determines the density and scale of the nanopore array, so the distance between adjacent grooves can be designed according to the required density of the nanopore array, and is not particularly limited here.

[0106] As an example, the angle θ between the first direction and the second direction ranges from 0 < θ < 180°, for example, it can be 5°, 45°, 90°, 135° or 175°. Specifically, the angle between the first direction and the second direction will directly affect the shape of the final nanopore. And the closer the angle of the angle is to 90°, the closer the shape of the final nanopore is to a standard square or circle.

[0107] In step S7, referring to Figure 1 and Figure 8 , a deposition process is performed on the third thin film layer to form a second sacrificial layer, the second sacrificial layer covers the bottom and sidewall of the second groove and the top of the third thin film layer, and the second sacrificial layer covering the bottom of the second groove and the top of the third thin film layer is etched and removed.

[0108] As an example, the second sacrificial layer is formed on the third thin film layer using one of physical vapor deposition, chemical vapor deposition or atomic layer deposition, preferably, the process of forming the second sacrificial layer is an atomic layer deposition process; the material of the second sacrificial layer includes at least one of silicon oxide, hafnium oxide, titanium nitride, magnesium oxide, zinc oxide, aluminum oxide, and the material of the second sacrificial layer is not limited to this. In this embodiment, the material of the second sacrificial layer is preferably an aluminum oxide layer. The thickness of the second sacrificial layer generally needs to be consistent with the diameter of the nanohole to be formed, and the thickness of the second sacrificial layer is not limited to this and can be set according to actual needs.

[0109] In step S8, referring to Figure 1 and Figure 9 , a fourth thin film layer is formed on the third thin film layer, the fourth thin film layer covers the bottom of the second groove and the fourth thin film layer and the third thin film layer have the same height, so that the second sacrificial layer is exposed as a second nanobelt.

[0110] As an example, the fourth thin film layer is formed on the third thin film layer using one of physical vapor deposition, chemical vapor deposition or atomic layer deposition, preferably, the process of forming the fourth thin film layer is a chemical vapor deposition process; the material of the fourth thin film layer includes polysilicon or other suitable materials such as silicon oxide, and in this embodiment, the material of the fourth thin film layer is preferably consistent with the material of the third thin film layer, so as to facilitate removal in subsequent processes, and the material of the fourth thin film layer is not limited to this and can be set according to actual needs.

[0111] Specifically, as shown in Figure 9 , the fourth thin film layer formed covers the bottom of the second groove and the top of the third thin film layer, and then a CMP process is performed on the top of the third thin film layer, so that the third thin film layer at the bottom of the first groove has the same height as the fourth thin film layer, so that the second sacrificial layer is exposed as a second nanobelt. That is, the second sacrificial layer on the sidewall of the second groove is covered by the third thin film layer and the fourth thin film layer, and the surfaces of the second sacrificial layer, the third thin film layer and the fourth thin film layer are uniform and flat, which is beneficial to improve the yield of the solid nanohole array formed.

[0112] In other embodiments, the process of forming the fourth thin film layer in step S8 can also be replaced by spin-coating a flowable material, for example, spin-coating SOG (spin on glass coating) or H-SiOx material in the second groove, and then performing an annealing process or a high-temperature heating process to form a hard material layer. The hard material layer is uniform and flat with the surfaces of the second sacrificial layer and the third thin film layer, and the second sacrificial layer exposed can serve as a second nanobelt.

[0113] In step S9, referring to Figure 1 and Figure 10 , a wet etching process is performed at the intersection of the first nanometer strip and the second nanometer strip to form a first etching cavity.

[0114] Specifically, in the embodiment, a wet etching process is performed at the intersection of the first nanometer strip and the second nanometer strip, so as to remove the first sacrificial layer and the second sacrificial layer at the intersection, as shown in Figure 10 , a first etching cavity is formed at the intersection of the first nanometer strip and the second nanometer strip, which is located in the first film layer and the second film layer. In the subsequent process, the first film layer with the first etching cavity is used as a mask for etching the functional material layer, so as to realize etching of the functional material layer.

[0115] In step S10, referring to Figure 1 and Figure 11 , dry etching is performed on the functional material layer based on the first etching cavity to form a solid-state nanopore array in the functional material layer.

[0116] As an example, after the nanopore array is formed in the functional material layer, a step of removing the first film layer, the second film layer, the third film layer, the fourth film layer, the first nanometer strip and the second nanometer strip is further included.

[0117] Specifically, the first film layer with the first etching cavity is used as a mask for etching the functional material layer, and the functional material layer is etched at the position of the first etching cavity, so as to form a plurality of nanopores in the functional material layer. After the plurality of nanopores are formed, the first film layer, the second film layer, the third film layer, the fourth film layer, the first nanometer strip and the second nanometer strip need to be removed, and only the substrate and the functional material layer are retained. At this time, the plurality of nanopores in the functional material layer constitute a solid-state nanopore array.

[0118] Specifically, as shown in the figure, the solid-state nanopore array formed in the embodiment has a two-dimensional periodic point array arrangement, and the etching depth of the solid-state nanopore array is generally not less than the thickness of the functional material layer. For example, the etching depth of the nanopores in the solid-state nanopore array is less than the thickness of the functional material layer, which can be set according to actual needs.

[0119] In the embodiment of the present application, the first nanometer strip along the first direction is formed in the first thin film layer and the second thin film layer by combining the deposition process and the dry etching process, the second nanometer strip along the second direction is formed in the third thin film layer and the fourth thin film layer, and then the selective etching is performed at the intersection of the first nanometer strip and the second nanometer strip, so that the required solid-state nanopore array pattern is formed in the functional material layer. Compared with the existing FIB, EBL, TEM and CBD methods, the preparation method has the advantages of rapid and efficient, large-area preparation, low cost and the like, and the pore diameter and array size of the formed nanopore can be accurately controlled through process parameter adjustment, and the method has high repeatability.

[0120] Embodiment 2

[0121] The embodiment of the present application provides a preparation method of a solid-state nanopore array device, as shown in the following process flow diagram of the preparation method of the solid-state nanopore array device. Figure 12 The preparation method of the solid-state nanopore array device comprises the following steps:

[0122] S101: providing a substrate, forming a functional material layer in which a nanopore needs to be prepared on the front surface of the substrate, and forming a mask layer on the back surface of the substrate;

[0123] S102: performing a deposition process on the functional material layer to form a first thin film layer;

[0124] S103: performing a first dry etching on the first thin film layer along a first direction of the first thin film layer to form a plurality of first grooves;

[0125] S104: performing a deposition process on the first thin film layer to form a first sacrificial layer, the first sacrificial layer covering the bottom and sidewall of the first groove and the top of the first thin film layer, and etching and removing the first sacrificial layer covering the bottom of the first groove and the top of the first thin film layer;

[0126] S105: forming a second thin film layer on the first thin film layer, the second thin film layer covering the bottom of the first groove and the second thin film layer having the same height as the first thin film layer, so that the first sacrificial layer is exposed as a first nanometer strip;

[0127] S106: performing a deposition process on the first thin film layer and the second thin film layer to form a third thin film layer, and performing a second dry etching on the third thin film layer along a second direction of the third thin film layer to form a plurality of second grooves;

[0128] S107: performing a deposition process on the third thin film layer to form a second sacrificial layer, the second sacrificial layer covering the bottom and sidewall of the second recess and the top of the third thin film layer, and etching to remove the second sacrificial layer covering the bottom of the second recess and the top of the third thin film layer;

[0129] S108: forming a fourth thin film layer on the third thin film layer, the fourth thin film layer covering the bottom of the second recess and the fourth thin film layer having the same height as the third thin film layer, so that the second sacrificial layer is exposed as a second nano strip;

[0130] S109: performing a deposition process on the third thin film layer and the fourth thin film layer to form a first patterned layer, the first patterned layer having a plurality of third recesses, and the third recesses exposing a window region;

[0131] S110: performing an etching process on the intersection of the first nano strip and the second nano strip in the window region to form a second etching cavity;

[0132] S111: performing a dry etching process on the functional material layer at the window region based on the second etching cavity to form a solid nanopore array;

[0133] S112: performing a registration process on the back surface of the substrate, and etching the substrate and the mask layer using an etching process to expose the solid nanopore array of the window region;

[0134] S113: removing the first thin film layer, the second thin film layer, the third thin film layer, the fourth thin film layer, the first nano strip, the second nano strip, and the first patterned layer to form the solid nanopore array device.

[0135] The preparation method of the solid nanopore array device will be further described below in combination with the accompanying drawings, as follows:

[0136] Among them, steps S101-S108 are consistent with the contents of steps S1-S8 in the preparation method of the solid nanopore array, and have been described in detail in the foregoing, which will not be repeated here.

[0137] Among them, please refer to Figure 12 and Figure 13 In step S101, a mask layer is also formed on the back surface of the substrate.

[0138] As an example, the mask layer is formed on the back surface of the substrate by one of physical vapor deposition, chemical vapor deposition or atomic layer deposition, preferably, the process of forming the mask layer is an atomic layer deposition process; the mask layer comprises a silicon nitride layer or a silicon dioxide layer, of course, the material of the mask layer is not limited thereto. In the embodiment, the material of the mask layer is preferably a silicon nitride layer. The thickness of the mask layer can be set according to actual needs.

[0139] Specifically, as shown in Figure 13 , the mask layer formed covers the back surface of the substrate, and the mask layer serves as a mask plate for the back surface alignment process subsequently performed on the back surface of the substrate.

[0140] In step S109, referring to Figure 12 and Figure 14 , a deposition process is performed on the third thin film layer to form a first patterned layer, the first patterned layer has a plurality of third grooves, and the third grooves expose the window region.

[0141] Specifically, the first patterned layer is formed on the third thin film layer by one of physical vapor deposition, chemical vapor deposition or atomic layer deposition, preferably, the process of forming the first patterned layer is a chemical vapor deposition process; the material of the first patterned layer comprises polysilicon or other suitable materials such as silicon oxide, of course, the material of the first patterned layer is not limited thereto.

[0142] As an example, the method of forming the first patterned layer comprises dry etching or other suitable methods; specifically, in the embodiment, the method of forming the first patterned layer comprises: sequentially growing a fifth thin film layer and a photoresist mask layer on the third thin film layer, exposing and developing the photoresist mask layer, patterning the photoresist mask layer corresponding to the positions of the third grooves, as shown in Figure 14 , etching the fifth thin film layer through the patterned photoresist mask layer to obtain the first patterned layer penetrating through the fifth thin film layer, and then removing the photoresist mask layer, the third grooves exposing the window region.

[0143] In step S110, referring to Figure 12 and Figure 15 , an etching process is performed on the intersection of the first nanometer strip and the second nanometer strip in the window region to form a second etching cavity.

[0144] Specifically, in the embodiment, a wet etching process is performed on the intersection of the first nanometer strip and the second nanometer strip at the window region, so as to remove the first nanometer strip and the second nanometer strip at the window region, as shown in Figure 15As shown, a second etching cavity is formed at the exposed window region, which is located in the first thin film layer and the second thin film layer. In a subsequent process, the first thin film layer and the second thin film layer with the second etching cavity are used as a mask to etch the functional material layer, so as to realize etching of the functional material layer.

[0145] In step S111, referring to Figure 12 and Figure 16 , dry etching is performed on the functional material layer of the window region based on the second etching cavity, so as to form a solid nanopore array in the functional material.

[0146] Specifically, the first thin film layer with the second etching cavity is used as a mask to etch the functional material layer, so as to form a solid nanopore array in the window region of the functional material layer.

[0147] In step S112, referring to Figure 12 and Figure 17 , a registration process is performed on the back surface of the substrate, and an etching process is used to etch the substrate and the mask layer, so as to expose the solid nanopore array of the window region.

[0148] Specifically, an etching process is used to etch the back surface of the substrate, so as to form the etching groove, which exposes the solid nanopore array in the functional material layer. Specifically, as shown in Figure 17 in this embodiment, an alkaline solution is selected to etch the back surface of the substrate, which can be a KOH solution with a concentration of 30%, and of course, TMAH can also be used to remove the silicon substrate and the mask layer.

[0149] In step S113, referring to Figure 12 and Figure 18 , the first thin film layer, the second thin film layer, the third thin film layer, the fourth thin film layer, the first nanometer strip, the second nanometer strip and the first patterned layer are removed, so as to form the solid nanopore array device.

[0150] Specifically, after forming a plurality of nanopores at the window region and completing the registration process, the first thin film layer, the second thin film layer, the third thin film layer, the fourth thin film layer, the first nanometer strip, the second nanometer strip and the first patterned layer need to be removed, and only the mask layer, the substrate and the functional material layer are reserved, so as to form the solid nanopore array device.

[0151] In the embodiment of the present application, the pore diameter and array size of the formed nanopore can be accurately controlled by adjusting the process parameters, and the nanopore array device with different window regions can be selectively designed according to actual needs to realize customization of the solid-state nanopore array device with different numbers of nanopores. The preparation method is suitable for various solid materials and can be completely compatible with the existing CMOS process technology to realize large-scale integrated manufacturing of the solid-state nanopore array device, thereby significantly reducing the preparation cost.

[0152] Embodiment 3

[0153] The embodiment also provides a solid-state nanopore array device obtained by the preparation method of the solid-state nanopore array device mentioned in the above content.

[0154] Embodiment 4

[0155] The embodiment also provides an application of the solid-state nanopore array device in electrochemical signal analysis, high-throughput analysis and detection of biological molecules such as DNA and proteins. Specifically, the single-hole / double-hole solid-state nanopore array device is obtained by the preparation method of the solid-state nanopore array device in the above embodiment two, the diameter of the nanopore is about 40 nm, and the conductivity test and biological molecule detection analysis are performed based on the obtained single-hole / double-hole solid-state nanopore array device, as shown in Figure 19 , which shows a structure schematic diagram of the single-hole / double-hole solid-state nanopore array device in the embodiment of the present application when performing the conductivity test and biological molecule detection analysis, wherein, Figure 19 a is a single-hole solid-state nanopore array device, Figure 19 b is a double-hole solid-state nanopore array device. Under the driving of the ion current, the DNA molecule moves from the cathode to the anode through the nanopore in the solid-state nanopore array device, thereby obtaining the blocking current signal.

[0156] The test solution is selected as 1.8M LiCl solution, and the conductivity of the single-hole / double-hole solid-state nanopore array device is as shown in Figure 20 . According to Figure 20 , the conductivity of the single-hole solid-state nanopore array device is about 247nS, and the conductivity of the double-hole solid-state nanopore array device is about 458nS.

[0157] The single-hole / double-hole solid-state nanopore array device is used for detecting and analyzing the DNA molecule, wherein the DNA molecule is selected as phiX174 DNA molecule with a concentration of about 3nM. Specifically, under a constant bias voltage of 60mV, the current-time relationship curve of the single-hole / double-hole solid-state nanopore array device within 100s after the signal is stable is obtained, as shown in Figure 21 . Figure 22The signal statistics diagram corresponding to the single-hole / dual-hole solid-state nanopore array device is shown. Through calculation, the capture rate of the single-hole solid-state nanopore array device per unit time is 0.25 / s, and the capture rate of the dual-hole solid-state nanopore array device per unit time is 0.66 / s. Therefore, it can be known that the dual-hole solid-state nanopore array device has higher capture rate and higher detection flux.

[0158] In summary, the solid-state nanopore array, the preparation method and application of the solid-state nanopore array device have the following beneficial effects: the preparation method of the solid-state nanopore array combines the deposition process film plating and the dry etching process to form the first nanometer strip along the first direction in the first thin film layer and the second thin film layer, to form the second nanometer strip along the second direction in the third thin film layer and the fourth thin film layer, and then to perform selective etching at the intersection of the first nanometer strip and the second nanometer strip, so as to form the required solid-state nanopore array pattern in the functional material layer. Compared with the existing FIB, EBL, TEM and CBD methods, the preparation method has the advantages of rapid and efficient, large-area preparation, low cost, and accurate control of the pore size and array size of the formed nanopore through process parameter adjustment, and high repeatability. The preparation method of the solid-state nanopore array device based on the solid-state nanopore array can be applied to various solid materials and is fully compatible with the existing CMOS process technology, realizing large-scale integrated manufacturing of the solid-state nanopore array device, so that the preparation cost can be significantly reduced. In addition, the solid-state nanopore array device can also realize high-throughput analysis and detection of electrochemical signals, DNA or protein molecules and the like. Therefore, the present application effectively overcomes the shortcomings of the prior art and has high industrial utilization value.

[0159] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.

Claims

1. A method for fabricating a solid-state nanoporous array, characterized in that, The method for preparing the solid-state nanopore array includes the following steps: S1: Provide a substrate, and form a functional material layer on the front side of the substrate to be used to prepare nanopores; S2: A first thin film layer is formed on the functional material layer by a deposition process; S3: Perform a first dry etching along the first direction of the first thin film layer to form a plurality of first grooves; S4: A first sacrificial layer is formed on the first thin film layer by a deposition process. The first sacrificial layer covers the bottom and sidewalls of the first groove and the top of the first thin film layer. The first sacrificial layer covering the bottom of the first groove and the top of the first thin film layer is removed by etching. S5: A second thin film layer is formed on the first thin film layer. The second thin film layer covers the bottom of the first groove and has the same height as the first thin film layer. That is, the first sacrificial layer located on the side wall of the first groove is covered by the first thin film layer and the second thin film layer, and the first sacrificial layer is used as the first nanostrip. S6: A third thin film layer is formed by deposition on the first thin film layer and the second thin film layer. A second dry etching is performed on the third thin film layer along the second direction to form a plurality of second grooves. The included angle θ between the first direction and the second direction is in the range of 0 < θ < 180°. S7: A second sacrificial layer is formed on the third thin film layer by a deposition process. The second sacrificial layer covers the bottom and sidewalls of the second groove and the top of the third thin film layer. The second sacrificial layer covering the bottom of the second groove and the top of the third thin film layer is removed by etching. S8: A fourth thin film layer is formed on the third thin film layer. The fourth thin film layer covers the bottom of the second groove and has the same height as the third thin film layer. That is, the second sacrificial layer located on the side wall of the second groove is covered by the third thin film layer and the fourth thin film layer, and the second sacrificial layer is used as the second nanostrip. S9: An etching process is performed at the intersection of the first nanostrip and the second nanostrip to form a first etching cavity; S10: Dry etching is performed on the functional material layer based on the first etching cavity to form a solid nanopore array in the functional material layer.

2. The method for preparing a solid-state nanopore array according to claim 1, characterized in that: After forming the solid nanopore array in the functional material layer, the method further includes the step of removing the first thin film layer, the second thin film layer, the third thin film layer, the fourth thin film layer, the first nanostrip, and the second nanostrip.

3. The method for fabricating a solid-state nanopore array according to claim 1, characterized in that: The deposition process is one of physical vapor deposition, chemical vapor deposition, or atomic layer deposition.

4. The method for fabricating a solid-state nanopore array according to claim 1, characterized in that: The first sacrificial layer includes at least one of silicon oxide, hafnium oxide, titanium nitride, magnesium oxide, zinc oxide, and aluminum oxide, and the second sacrificial layer includes at least one of silicon oxide, hafnium oxide, titanium nitride, magnesium oxide, zinc oxide, and aluminum oxide.

5. The method for preparing a solid-state nanopore array according to any one of claims 1 to 4, characterized in that: The material forming the functional material layer includes at least one of metal, non-metal, metal compound and non-metal compound thin film, and the thickness d of the functional material layer is in the range of 0 < d ≤ 1 μm.

6. The method for fabricating a solid-state nanopore array according to claim 5, characterized in that: The first thin film layer is made of the same material as the second thin film layer, and the third thin film layer is made of the same material as the fourth thin film layer.

7. The method for preparing a solid-state nanopore array according to claim 5, characterized in that: The etching depth of the functional material layer by dry etching is not less than the thickness of the functional material layer.

8. A method for fabricating a solid-state nanopore array device, characterized in that, The fabrication method of the solid-state nanopore array device includes the following steps: A substrate is provided, on the front side of the substrate a functional material layer for fabricating nanopores is formed, and on the back side of the substrate a mask layer is formed; A first thin film layer is formed on the functional material layer by a deposition process; A plurality of first grooves are formed by first dry etching along a first direction of the first thin film layer; A first sacrificial layer is formed by deposition on the first thin film layer. The first sacrificial layer covers the bottom and sidewalls of the first groove and the top of the first thin film layer. The first sacrificial layer covering the bottom of the first groove and the top of the first thin film layer is removed by etching. A second thin film layer is formed on the first thin film layer. The second thin film layer covers the bottom of the first groove and has the same height as the first thin film layer. That is, the first sacrificial layer located on the sidewall of the first groove is covered by the first thin film layer and the second thin film layer, and the first sacrificial layer is used as the first nanostrip. A third thin film layer is formed by deposition on the first thin film layer and the second thin film layer. A second dry etching is performed on the third thin film layer along the second direction to form a plurality of second grooves. The included angle θ between the first direction and the second direction is in the range of 0 < θ < 180°. A second sacrificial layer is formed by deposition on the third thin film layer. The second sacrificial layer covers the bottom and sidewalls of the second groove and the top of the third thin film layer. The second sacrificial layer covering the bottom of the second groove and the top of the third thin film layer is removed by etching. A fourth thin film layer is formed on the third thin film layer. The fourth thin film layer covers the bottom of the second groove and has the same height as the third thin film layer. That is, the second sacrificial layer located on the sidewall of the second groove is covered by the third thin film layer and the fourth thin film layer, and the second sacrificial layer serves as the second nanostrip. A first patterned layer is formed by deposition on the third and fourth thin film layers. The first patterned layer has a plurality of third grooves, and the third grooves expose the window area. An etching process is performed at the intersection of the first nanostrip and the second nanostrip in the window region to form a second etching cavity; Based on the second etching cavity, the functional material layer at the window region is dry etched to form a solid nanopore array; A registration process is performed on the back side of the substrate, and an etching process is used to etch the substrate and the mask layer to expose the solid-state nanopore array in the window region. The solid-state nanopore array device is formed by removing the first thin film layer, the second thin film layer, the third thin film layer, the fourth thin film layer, the first nanostrip, the second nanostrip, and the first patterned layer.

9. The method for fabricating a solid-state nanopore array device according to claim 8, characterized in that: The material forming the functional material layer includes at least one of metal, non-metal, metal compound and non-metal compound thin film, and the thickness d of the functional material layer is in the range of 0 < d ≤ 1 μm.

10. The method for fabricating a solid-state nanopore array device according to claim 8, characterized in that: The first sacrificial layer includes at least one of silicon oxide, hafnium oxide, titanium nitride, magnesium oxide, zinc oxide, and aluminum oxide, and the second sacrificial layer includes at least one of silicon oxide, hafnium oxide, titanium nitride, magnesium oxide, zinc oxide, and aluminum oxide.

11. The method for fabricating a solid-state nanopore array device according to claim 8, characterized in that: The first thin film layer is made of the same material as the second thin film layer, and the third thin film layer is made of the same material as the fourth thin film layer.

12. The method for fabricating a solid-state nanopore array device according to claim 8, characterized in that: The etching depth of the functional material layer by dry etching is not less than the thickness of the functional material layer.

13. A solid-state nanopore array device, characterized in that, The solid-state nanopore array device is obtained by the fabrication method of the solid-state nanopore array device according to any one of claims 8 to 12.

14. The application of the solid-state nanopore array device of claim 13 in electrochemical signal analysis, high-throughput analysis and detection of biomolecules.

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