Noise test information generation and noise evaluation method, device, medium and product

Abstract

The present application discloses a method, device, medium and product for generating noise test information and evaluating noise, relating to the technical field of servers, including: performing noise tests on test circuit boards corresponding to different circuit board parameter groups to obtain noise values, and generating total noise test information based on the circuit board parameter groups, their corresponding noise affected objects, noise source regions, and noise values. When evaluating the noise impact of a circuit board, the noise value of the circuit board to be evaluated can be determined in the total noise test information based on the circuit board parameter group, noise affected object, and noise source region of the circuit board to be evaluated, and then noise evaluation information is generated based on the noise value and the maximum noise threshold to indicate whether to adjust the circuit board to be evaluated. In this way, in the case of determining to make adjustments, the total noise test information can be used as a reference to adjust the circuit board instead of using fixed circuit board parameters to design the circuit, which can reduce the occurrence of the problem of waste of hardware resources.

Description

Technical Field

[0001] This application relates to the technical field of servers, and particularly to methods, devices, media, and products for generating noise test information and evaluating noise. Background Art

[0002] In the technical field of servers, a server includes a Printed Circuit Board (PCB). During the switching process of the power supply on the PCB, rapid voltage and current changes will occur, which will interfere with other components on the PCB, that is, power supply noise.

[0003] Currently, in order to reduce the impact of noise on other components on the PCB, the layout of devices on the PCB is generally designed according to general design rules. In this way, using the same design rules for different PCBs will result in waste of hardware resources. Summary of the Invention

[0004] This application provides methods, devices, electronic devices, storage media, and program products for generating noise test information and evaluating noise, so as to at least solve the problem of waste of hardware resources in related technologies.

[0005] This application provides a method for generating noise test information, including:

[0006] Obtaining at least one noise-affected object and at least one noise source area;

[0007] Pairing any one of the at least one noise-affected object with any one of the at least one noise source area respectively to obtain at least one noise factor combination;

[0008] Generating a plurality of circuit board parameter groups corresponding to each noise factor combination according to the noise-affected object and the noise source area in each noise factor combination, and the circuit board parameters in the pre-constructed circuit board parameter pool that match the noise factor combination;

[0009] Performing noise tests on the test circuit boards corresponding to each circuit board parameter group respectively to obtain noise values corresponding to each circuit board parameter group;

[0010] Generating total noise test information according to each noise factor combination, the plurality of circuit board parameter groups corresponding to each noise factor combination respectively, and the noise values corresponding to each circuit board parameter group, so as to evaluate whether the noise of the circuit board is within a preset noise range.

[0011] This application also provides a device for generating noise test information, including:

[0012] A first acquisition module, configured to acquire at least one noise-affected object and at least one noise source area;

[0013] A combination module, configured to respectively combine any one of the at least one noise-affected object and any one of the at least one noise source area in pairs to obtain at least one noise factor combination;

[0014] A first generation module, configured to generate multiple circuit board parameter groups corresponding to each noise factor combination according to the noise-affected object and the noise source area in each noise factor combination, and the circuit board parameters in a pre-constructed circuit board parameter pool that match the noise factor combination;

[0015] A test module, configured to respectively perform noise tests on the test circuit boards corresponding to each circuit board parameter group to obtain noise values corresponding to each circuit board parameter group;

[0016] The first generation module is further configured to generate total noise test information according to each noise factor combination, the multiple circuit board parameter groups respectively corresponding to each noise factor combination, and the noise values corresponding to each circuit board parameter group, so as to evaluate whether the noise of the circuit board is within a preset noise range.

[0017] This application further provides an electronic device, including: a memory, configured to store a computer program; a processor, configured to implement the steps of any one of the above noise test information generation methods when executing the computer program.

[0018] This application further provides a computer-readable storage medium, in which a computer program is stored, and wherein the computer program implements the steps of any one of the above noise test information generation methods when executed by a processor.

[0019] This application further provides a computer program product, including a computer program, and the computer program implements the steps of any one of the above noise test information generation methods when executed by a processor.

[0020] Through this application, since in general design rules, a relatively large circuit board parameter threshold is usually given, and technicians design circuits based on the relatively large circuit board parameter threshold, the problem of wasting hardware resources often occurs. However, this application can indicate whether the circuit board meets the noise regulations corresponding to the circuit board based on the actual total noise test information, thereby guiding technicians to make adjustments, so that the circuit board design of each project can meet the personalized regulations of the project, that is, a more accurate circuit board parameter can be used to layout the circuit board instead of using the specified circuit board parameter threshold for design, which can reduce the occurrence of the problem of wasting hardware resources.

[0021] The present application provides a noise evaluation method, including:

[0022] Obtaining a circuit board parameter group, a noise influence object, a noise source area, and a maximum noise threshold corresponding to the circuit board to be evaluated;

[0023] Determining a noise value corresponding to the circuit board to be evaluated from the pre-obtained total noise test information according to the circuit board parameter group, the noise influence object, and the noise source area, wherein the total noise test information is generated according to the above-mentioned noise test information generation method;

[0024] Determining a noise test result according to the noise value corresponding to the circuit board to be evaluated and the maximum noise threshold;

[0025] After performing an operation corresponding to the noise test result according to the noise test result, generating noise evaluation information of the circuit board to be evaluated, wherein the noise evaluation information is used to indicate whether to adjust the circuit board to be evaluated.

[0026] The present application further provides a noise evaluation device, including:

[0027] A second obtaining module, configured to obtain a circuit board parameter group, a noise influence object, a noise source area, and a maximum noise threshold corresponding to the circuit board to be evaluated;

[0028] A determining module, configured to determine a noise value corresponding to the circuit board to be evaluated from the pre-obtained total noise test information according to the circuit board parameter group, the noise influence object, and the noise source area, wherein the total noise test information is generated according to the above-mentioned noise test information generation method; determining a noise test result according to the noise value corresponding to the circuit board to be evaluated and the maximum noise threshold;

[0029] A second generating module, configured to generate noise evaluation information of the circuit board to be evaluated after performing an operation corresponding to the noise test result according to the noise test result, wherein the noise evaluation information is used to indicate whether to adjust the circuit board to be evaluated.

[0030] The present application further provides an electronic device, including: a memory, configured to store a computer program; a processor, configured to implement the steps of any one of the above-mentioned noise evaluation methods when executing the computer program.

[0031] The present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program implements the steps of any one of the above-mentioned noise evaluation methods when being executed by a processor.

[0032] The present application further provides a computer program product, including a computer program, wherein the computer program implements the steps of any one of the above-mentioned noise evaluation methods when being executed by a processor.

[0033] Through this application, during the process of evaluating a circuit board, the circuit board parameter group, noise influence object, noise source area, and maximum noise threshold of the current circuit board (i.e., the circuit board to be evaluated) can be obtained first. Furthermore, based on the circuit board parameter group, noise influence object, and noise source area, the noise value corresponding to the circuit board to be evaluated can be determined from the pre-obtained total noise test information. In this way, real-time noise testing is not required, and the evaluation efficiency can be improved. In addition, according to the noise value corresponding to the circuit board to be evaluated and the maximum noise threshold corresponding to the circuit board to be evaluated, the noise test result can be determined, and then the noise evaluation information can be generated according to the noise test result to indicate whether the technical personnel need to adjust the evaluated circuit board, so as to accurately adjust the circuit board parameters instead of directly using larger circuit board parameters to design the circuit board, which can reduce the occurrence of hardware resource waste problems. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] To more clearly illustrate the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0035] Figure 1 It is a schematic structural diagram of a noise test system provided by an embodiment of the present application;

[0036] Figure 2 It is a schematic flowchart of a method for generating noise test information provided by an embodiment of the present application;

[0037] Figure 3 It is a schematic diagram of the positional relationship between a noise hole and a trace provided by an embodiment of the present application;

[0038] Figure 4 It is a schematic diagram of the positional relationship between a power plane and a trace provided by an embodiment of the present application;

[0039] Figure 5 It is a schematic diagram of a noise interference cross-section provided by an embodiment of the present application;

[0040] Figure 6 It is a schematic diagram of the distance relationship between a trace and different noise source areas of a power supply provided by an embodiment of the present application;

[0041] Figure 7 It is another schematic diagram of the distance relationship between a trace and different noise source areas of a power supply provided by an embodiment of the present application;

[0042] Figure 8 It is a schematic flowchart of a noise evaluation method provided by an embodiment of the present application;

[0043] Figure 9 A circuit schematic diagram of a power supply provided by an embodiment of the present application;

[0044] Figure 10 A circuit board layout schematic diagram of a power supply provided by an embodiment of the present application;

[0045] Figure 11 A structural schematic diagram of a noise test information generation device provided by an embodiment of the present application;

[0046] Figure 12 A structural schematic diagram of a noise evaluation device provided by an embodiment of the present application;

[0047] Figure 13 A structural schematic diagram of an electronic device provided by an embodiment of the present application. Detailed implementation manners

[0048] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present application.

[0049] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0050] In order to enable those skilled in the art of the present technology to better understand the solution of the present application, the present application will be further described in detail below in conjunction with the accompanying drawings and specific implementation manners.

[0051] The embodiments of the present application can be implemented by a noise test system, such as Figure 1As shown, the noise test system may include a target device, a noise measuring instrument, a power supply, and a circuit board. The target device may be a computer device, such as a desktop computer or a laptop computer. The noise measuring instrument may be a frequency-domain noise measuring instrument and a time-domain noise measuring instrument. Both the power supply and the circuit board may be printed circuit boards (PCBs). The power supply is used to generate noise to test the noise impact of the power supply on the test circuit board. The noise measuring instrument is used to measure the noise on the test circuit board. The circuit board may be a test circuit board, a verification circuit board, and a circuit board to be evaluated. The power supply may be a separate power circuit board, electrically connected to the circuit board, or the power supply may also be located on the circuit board.

[0052] Embodiments of the present application provide a noise test generation method, which can be executed by the above-mentioned target device, such as Figure 2 As shown, the method may specifically include the following steps:

[0053] Step S201, obtain at least one noise impact object and at least one noise source area.

[0054] Among them, the noise impact object may be a trace, a signal hole, etc. on the circuit board. The trace may also be called a signal trace, which is a path for transmitting data or control signals. The signal hole may be a via for transferring current or signals from one layer of the circuit board to another layer.

[0055] The noise source area may be a field-effect transistor (FET) area (which may also be called a field-effect transistor node), a phase area (which may also be called a phase node), an inductor area, etc. in the power supply. The field-effect transistor area may be an area including a field-effect transistor. The phase area may be an area where the phase of the signal changes. The inductor area may be an area where the inductor is located.

[0056] Specifically, a technician can input the noise impact object and the noise source area to be tested on the target device. The target device can then obtain at least one noise impact object and at least one noise source area.

[0057] Step S202, combine any one of the at least one noise impact object and any one of the at least one noise source area in pairs to obtain at least one noise factor combination.

[0058] Specifically, the target device can combine the noise - affected objects and the noise - source regions pairwise to obtain at least one noise - factor combination. For example, if the noise - affected objects include traces, and the noise - source regions include the field - effect transistor region and the phase region, after pairwise combination, the obtained noise - factor combinations can include [trace, field - effect transistor region] and [trace, phase region].

[0059] Step S203: Generate multiple circuit - board parameter groups corresponding to each noise - factor combination according to the noise - affected objects and the noise - source regions in each noise - factor combination, and the circuit - board parameters in the pre - constructed circuit - board parameter pool that match the noise - factor combination.

[0060] Among them, the circuit - board parameter pool can include one or more elements such as the spacing between the noisy vias and the traces, the number of ground layers (GND) between the power plane and the traces, the spacing between the power plane and the traces, the number of ground layers between the power plane and the traces, the spacing between the noisy vias and the traces, the inductance, the spacing between the noisy vias and the signal vias, etc. The noisy vias are the vias on the power supply that have a noise - generating effect on the circuit board. The power plane is an important part of the printed circuit board, mainly used to provide a stable power supply and a low - impedance path to ensure that each component in the circuit can obtain the required operating voltage. The power plane is usually a large - area copper layer that covers the entire or part of the PCB layer.

[0061] For example, Figure 3 shows the positional relationship between the noisy vias and the traces. Among them, the trace can be between two ground layers, and the noisy via can pass through two ground layers. Figure 4 shows the positional relationship between the power plane and the traces. The trace can be between the power plane and the ground layer. As Figure 5 shown, the power supply transmits current to the load through the power plane and the noisy vias (the current transmission path can refer to the arrow indication in Figure 5 ). During the process of transmitting current, the generated noise will also have a noise - generating effect on the traces on the test circuit board through the power plane and the noisy vias. In Figure 5 , D1, D2, and D3 can be the respective spacings between the noisy vias and 3 traces.

[0062] Step 1: Select at least one circuit - board parameter from the circuit - board parameter pool that matches both the target noise - affected object and the target noise - source region included in the target noise - factor combination.

[0063] Among them, the target noise - factor combination is any one of the multiple noise - factor combinations.

[0064] Specifically, when the target device determines that the target noise-affected object is a trace and the target noise source area is a field-effect transistor area, one or more elements among the distance between the noise hole and the trace and the number of ground layers between the power plane and the trace are selected as circuit board parameters that match both the target noise-affected object and the target noise source area. When it is determined that the target noise-affected object is a trace and the target noise source area is a phase area, one or more elements among the distance between the power plane and the trace, the number of ground layers between the power plane and the trace, and the distance between the noise hole and the trace are selected as circuit board parameters that match both the target noise-affected object and the target noise source area. When it is determined that the target noise-affected object is a trace or a signal hole and the target noise source area is an inductor area, the inductor is selected as a circuit board parameter that matches both the target noise-affected object and the target noise source area. When it is determined that the target noise-affected object is a signal hole and the target noise source area is a field-effect transistor area or a phase area, the distance between the noise hole and the signal hole is selected as a circuit board parameter that matches both the target noise-affected object and the target noise source area.

[0065] Since the types of circuit board parameters corresponding to different combinations of noise factors also vary, further according to the combination of noise factors, the corresponding circuit board parameters can be selected from the circuit board parameter pool, and the corresponding circuit board parameter groups can be generated. This can not only avoid the problem of resource waste caused by each group of circuit board parameters using all circuit board parameters, but also ensure the comprehensiveness (i.e., subsequent combination of noise values extracted from different sub-noise test information) and accuracy of the test.

[0066] Step 2: According to each type of circuit board parameter, obtain the parameter value generation rule corresponding to each type of circuit board parameter.

[0067] Among them, the parameter value generation rule includes an initial parameter value, a step size, and the number of parameter values.

[0068] Specifically, the target device may store the first correspondence between the circuit board parameters and the parameter value generation rules. In this way, after the target device determines the circuit board parameters that match both the target noise-affected object and the target noise source area, for each type of circuit board parameter, the parameter value generation rule corresponding to the circuit board parameter can be determined according to the circuit board parameter and the first correspondence.

[0069] Step 3: According to the parameter value generation rule corresponding to each type of circuit board parameter and the preset permutation and combination rule, generate multiple circuit board parameter groups corresponding to the target noise factor combination.

[0070] Specifically, taking the target circuit board parameters (any circuit board parameters that match both the target noise-affected object and the target noise source area) as an example, the target device can use the initial parameter value included in the parameter value generation rule corresponding to the target circuit board parameters as the starting value, and use the step size as the adjustment value to adjust this starting value multiple times to obtain the same number of parameter values as included in the parameter value generation rule corresponding to the target circuit board parameters (the difference between adjacent parameter values is the step size included in the parameter value generation rule corresponding to the target circuit board parameters).

[0071] Step S204: Perform noise tests on the test circuit boards corresponding to each circuit board parameter group respectively to obtain the noise values corresponding to each circuit board parameter group.

[0072] Specifically, technicians can design a test circuit board corresponding to each circuit board parameter group and connect it to the above-mentioned noise test system, that is, the circuit board in the noise test system is the test circuit board. In this way, technicians can input a control instruction to the target device. After the target device obtains the control instruction, it can perform a noise test on the test circuit board according to the preset test process to obtain the noise value corresponding to this circuit board parameter group. Correspondingly, the target device can complete the noise test process according to the following specific steps:

[0073] Step 1: Adjust the state of the power supply connected to the target test circuit board to perform a noise test on the target test circuit board.

[0074] Among them, the target test circuit board is the test circuit board corresponding to the second circuit board parameter group, and the second circuit board parameter group is any one of the multiple circuit board parameter groups corresponding to each noise factor combination.

[0075] Step 2: Send a test instruction to the noise measuring instrument connected to the target test circuit board to instruct the noise measuring instrument to monitor and feedback the target noise test information of the target test circuit board.

[0076] Step 3: Analyze the target noise test information to obtain the target noise value corresponding to the second circuit board parameter group.

[0077] Specifically, taking the target test circuit board as an example, the target device can adjust the state of the power supply connected to the target test circuit board. For example, turn on the power supply so that it can output current to the target test circuit board. And the target device can send a test instruction to the noise measuring instrument. After receiving the test instruction, the noise measuring instrument can start measuring the noise of the noise-affected object in the target test circuit board to detect the target noise test information of the target test circuit board and feedback it to the target device. The target device can analyze the target noise test information to determine the noise value.

[0078] For example, Figure 6 and Figure 7 both respectively show the circuit board layout of the power supply. In a power supply such as Figure 6 and Figure 7 shown, its noise source regions include the field effect transistor region (the field effect transistor node in Figure 6 ), and the phase region (the phase node in Figure 6 ). Additionally, the circuit board of the power supply may also include multiple nodes such as an input inductor, a power input node, a capacitor, a resistor, a Boot Net, a Phase Net, a ground, an output inductor, a power output, etc. When the target noise-affected object is a trace and the target noise source region is the field effect transistor region, the distance from the trace on the target test circuit board to the field effect transistor region is less than the distance from the trace on the target test circuit board to the phase region. As shown in Figure 6 , S1 is the distance from the trace on the target test circuit board to the field effect transistor region (the black bolded box), and S2 is the distance from the trace on the target test circuit board to the phase region. Since both the field effect transistor region and the phase region of the power supply can affect the trace with noise, therefore, in the case where the target noise source region is the field effect transistor region, through the above trace layout method, the noise influence of the phase region on the trace can be reduced, and thus the determined target noise value is more accurate. For example, S2 can be greater than 30 mil (an imperial unit, 1 mil is equal to one thousandth of an inch).

[0079] Conversely, in the same circuit board structure, when the target noise-affected object is a trace and the target noise source region is the phase region, the distance from the trace on the target test circuit board to the field effect transistor region is greater than the distance from the trace on the target test circuit board to the phase region. As shown in Figure 7 , S3 is the distance from the trace on the target test circuit board to the field effect transistor region (the field effect transistor node in Figure 7 ), and S4 is the distance from the trace on the target test circuit board to the phase region (the phase node in Figure 7 , shown as a black bolded box). Since both the field effect transistor region and the phase region of the power supply can affect the trace with noise, therefore, in the case where the target noise source region is the phase region, through the above trace layout method, the noise influence of the field effect transistor region on the trace can be reduced, and thus the determined target noise value is more accurate. For example, S3 can be greater than 30 mil.

[0080] Step S205: Generate total noise test information based on each noise factor combination, the multiple circuit board parameter groups respectively corresponding to each noise factor combination, and the noise values corresponding to each circuit board parameter group, so as to evaluate whether the noise of the circuit board is within the preset noise range.

[0081] Among them, the total noise test information can be composed of one or more data tables.

[0082] Step 1: Generate sub-noise test information corresponding to the target noise factor combination according to each circuit board parameter group among the multiple circuit board parameter groups corresponding to the target noise factor combination and its corresponding noise value.

[0083] Among them, the sub-noise test information can be in the form of a table.

[0084] Step 2: Generate total noise test information according to the sub-noise test information corresponding to each noise factor combination.

[0085] Specifically, for the target noise factor combination, the target device can use a circuit board parameter group and the noise value corresponding to the circuit board parameter group as a piece of noise test data. In this way, the target device can generate a piece of noise test data corresponding to each circuit board parameter group among the multiple circuit board parameter groups corresponding to the target noise factor combination according to each circuit board parameter group among the multiple circuit board parameter groups corresponding to the target noise factor combination and its corresponding noise value. These noise test data constitute the sub-noise test information corresponding to the target noise factor combination.

[0086] Based on the above method, the target device can determine the sub-noise test information corresponding to each noise factor combination for each noise factor. Furthermore, the target device can generate total noise test information in the following two ways:

[0087] Method 1: jointly determine the sub-noise test information corresponding to all noise factor combinations as the total noise test information.

[0088] Method 2

[0089] Step 1: When it is determined that there are multiple to-be-processed noise factor combinations including the target noise influence object, generate parent noise test information corresponding to the target noise influence object according to the sub-noise test information corresponding to each to-be-processed noise factor combination.

[0090] Among them, the parent noise test information can be in the form of a table.

[0091] Step 1 can specifically include:

[0092] Step a, in the current processing round, extract a noise value corresponding to the current processing round from the sub-noise test information corresponding to each noise factor combination to be processed, and combine them to obtain a noise value combination corresponding to the current processing round. After completing the last processing round, multiple noise value combinations are obtained.

[0093] Step b, calculate the total noise value corresponding to the target noise value combination according to all the noise values included in the target noise value combination.

[0094] Among them, the target noise value combination is any one of the multiple noise value combinations.

[0095] Step c, generate the parent noise test information corresponding to the target noise affected object according to each noise value combination and the total noise value corresponding to each noise value combination.

[0096] Specifically, the target device can first determine whether there are multiple noise factor combinations to be processed including the target noise affected object in the above-mentioned noise factor combinations. If so, it can perform permutation and combination operations on the noise values in the sub-noise test information corresponding to each noise factor combination to be processed to generate multiple noise value combinations. Furthermore, for each noise value combination, the target device can calculate the total noise value corresponding to each noise value combination according to the following formula (1).

[0097] Among them, step b can adopt the following expression:

[0098] Formula (1)

[0099] Among them, T is the total noise value corresponding to the target noise value combination, A i is the noise value extracted from the i-th noise factor combination to be processed, n is the number of noise factor combinations to be processed, and i is an integer less than or equal to n and greater than 0.

[0100] Example 1, when the noise affected object is a trace and the noise source regions include a field effect transistor region and a phase region, the above formula (1) can be transformed into:

[0101] Formula (2)

[0102] Among them, is a noise value in the sub-noise test information corresponding to [trace, field effect transistor region], is a noise value in the sub-noise test information corresponding to [trace, phase region].

[0103] Example 2, when the object affected by noise is a trace, and the noise source region includes a field effect transistor region, a phase region, and an inductor region, the above formula (1) can be transformed into:

[0104] Formula (3)

[0105] Wherein, is a noise value in the sub-noise test information corresponding to [trace, field effect transistor region], is a noise value in the sub-noise test information corresponding to [trace, phase region], is a noise value in the sub-noise test information corresponding to [trace, inductor region].

[0106] Step 2, determine the sub-noise test information corresponding to all combinations of noise factors and the parent noise test information corresponding to all objects affected by noise together as the total noise test information.

[0107] In some optional embodiments, in order to improve the accuracy of the total noise test information, a verification operation can be performed first to determine whether the above total noise test information is accurate, and an update operation is performed when it is determined that the total noise test information is inaccurate. The specific steps can be as follows:

[0108] Step 1, obtain a first circuit board parameter group, a first object affected by noise, and a first noise source region corresponding to the verification circuit board.

[0109] Step 2, determine a first noise value corresponding to the verification circuit board in the total noise test information according to the first circuit board parameter group, the first object affected by noise, and the first noise source region.

[0110] Step 3, perform a noise test on the verification circuit board to obtain a second noise value.

[0111] Step 4, determine whether to update the total noise test information according to the first noise value and the second noise value.

[0112] Step 5, when it is determined to update the total noise test information, add the noise compensation circuit board parameters corresponding to the first object affected by noise to the circuit board parameter pool for re-performing the noise test to update the total noise test information.

[0113] Wherein, when the first object affected by noise is a trace, the noise compensation circuit board parameter is the dielectric thickness between the ground layer and the power plane, or when the first object affected by noise is a signal hole, the noise compensation circuit board parameter is the distance from the power plane to the signal hole. For example, the dielectric thickness can refer to H shown in Figure 5 as shown in.

[0114] Specifically, the target device can first design a verification circuit board, and the technical personnel can input the circuit board parameters, the first noise-affected object, and the first noise source area of the verification circuit board into the target device. In this way, the target device can obtain the first circuit board parameter group, the first noise-affected object, and the first noise source area corresponding to the verification circuit board. Then, the target device can determine the first sub-noise test information that matches both the first noise-affected object and the first noise source area in the total test information. Furthermore, according to each circuit board parameter value included in the first circuit board parameter group, the target device can find the first noise value corresponding to the first circuit board parameter group in the first sub-noise test information. The target device tests the verification circuit board in a manner similar to step S204 to obtain the actual second noise value. Finally, the target device can compare whether the absolute value of the difference between the first noise value and the second noise value is less than a preset threshold. If so, it can be determined that there is no need to update the total noise test information (i.e., the verification passes); if not, it can be determined to update the total noise test information (i.e., the verification fails). In the case of determining to update, the target device can add the noise compensation circuit board parameters to the circuit board parameter pool. Subsequently, the test method from step S201 to step S205 can be followed again to obtain a new total noise test information.

[0115] The technical personnel can design multiple verification circuit boards for different tests and update the total noise test information multiple times to obtain more accurate and comprehensive total noise test information, which can make the subsequent evaluation more reasonable and accurate. In addition, since the noise compensation circuit board parameters are factors with less impact on noise, if they are added to the circuit board parameter pool as a factor for testing at the beginning, it will result in a large amount of testing and consume more resources. Therefore, this solution chooses to use the verification circuit board for verification. Only when the verification fails will the test be retested. In the case of a successful verification, there is no need to update the total noise test information, thus ensuring accuracy while reducing the amount of testing.

[0116] In some alternative embodiments, for any noise-affected object, the target device may, after performing multiple verification operations corresponding to the noise-affected object, count the proportion of successful verifications and the proportion of failed verifications. Moreover, for each verification operation, the absolute value of the difference between the measurement result of the noise meter and the result obtained from the total noise test information may be recorded. Furthermore, the target device may calculate a total verification value based on the proportion of successful verifications, the proportion of failed verifications, and the absolute value of the difference corresponding to each verification operation. When the total verification value is greater than a preset verification threshold, the noise compensation circuit board parameters corresponding to the noise-affected object may be added to the circuit board parameter pool. Alternatively, when the total verification value is less than or equal to the preset verification threshold, it may be determined not to update the total noise test information.

[0117] Among them, to calculate the total verification value based on the proportion of successful verifications, the proportion of failed verifications, and the difference corresponding to each verification operation, the following expression may be used:

[0118] Formula (4)

[0119] Among them, is the total verification value, is the first weight value, used to indicate the importance of successful verification to the total verification value, is the second weight value, used to indicate the importance of failed verification to the total verification value, is the third weight value, used to indicate the importance of the absolute value of the difference to the total verification value, is the proportion of successful verifications, is the proportion of failed verifications, q is the number of verification operations, e z is the absolute value of the difference corresponding to the z-th verification operation.

[0120] In this way, with the advantages of the above verification process, further evaluating whether to update the total noise test information through the total verification value of multiple tests can improve the accuracy of the total noise test information, and thus can improve the accuracy of the subsequent evaluation results of the circuit board.

[0121] The noise test information generation method provided by the embodiments of the present application. Since the object affected by noise is the component on the circuit board affected by noise, and the noise source area is the area where noise is generated on the power supply. Furthermore, by combining the object affected by noise and the noise source area, a noise factor combination can be obtained. According to the object affected by noise and the noise source area in the noise factor combination, and the circuit board parameter pool, multiple circuit board parameter groups can be generated. In this way, after performing noise tests on the test circuit boards corresponding to each circuit board parameter value, noise values can be obtained. Finally, according to the noise factor combination, the circuit board parameter groups corresponding to the noise factor combination, and the noise values corresponding to the circuit board parameter groups, total noise test information can be obtained. In this way, by comprehensively testing the circuit boards corresponding to different circuit board parameter groups in advance, the noise effects under different designs can be obtained.

[0122] In general design rules, usually a relatively large circuit board parameter threshold is given, and technicians design the circuit board based on this. However, when designing the circuit with a relatively large circuit board parameter threshold, the problem of wasting hardware resources often occurs. However, in the present application, based on the actual total noise test information, it can be indicated whether the circuit board meets the noise regulations corresponding to the circuit board, so as to guide technicians to make adjustments, which can make the circuit board design of each project meet the personalized regulations of the project. That is, the circuit board can be laid out with relatively accurate circuit board parameters instead of using the specified circuit board parameter threshold for design, which can reduce the occurrence of the problem of wasting hardware resources.

[0123] In addition, when technicians need to evaluate a circuit board in the follow-up, they can directly evaluate whether the noise of the circuit board meets the regulations (that is, evaluate whether the noise of the circuit board is within the preset noise range) through the total noise test information, and give corresponding indication information. During the evaluation process, there is no need to perform real-time noise tests anymore, but the corresponding noise value can be directly found from the total noise test information, which can improve the evaluation efficiency.

[0124] The embodiments of the present application provide a noise evaluation method, which can be executed by the above-mentioned target device, such as Figure 8 shown. The method specifically may include the following steps:

[0125] Step S801, obtain the circuit board parameter group, the object affected by noise, the noise source area, and the maximum noise threshold corresponding to the circuit board to be evaluated.

[0126] Step S802, determine the noise value corresponding to the circuit board to be evaluated in the pre-obtained total noise test information according to the circuit board parameter group, the object affected by noise, and the noise source area.

[0127] Among them, the total noise test information is generated according to steps S201 to S205. It can also be obtained by re-updating after performing the verification operation.

[0128] Specifically, when there is one noise-affected object and one noise source area, the target device can determine, according to the noise-affected object and the noise source area corresponding to the circuit board to be evaluated, the second sub-noise test information in the total noise test information that matches both the noise-affected object and the noise source area corresponding to the circuit board to be evaluated. Furthermore, according to the circuit board parameter group corresponding to the circuit board to be evaluated, the target device can determine the noise value that matches the circuit board parameter group in the second sub-noise test information, that is, determine the noise value corresponding to the circuit board to be evaluated.

[0129] Alternatively, when there are multiple noise-affected objects or multiple noise source areas, the target device can perform permutations and combinations on the noise-affected objects and the noise source areas to obtain multiple combinations of noise-affecting factors corresponding to the circuit board to be evaluated. For each combination of noise-affecting factors, the target device can, according to the noise-affected object and the noise source area included in the combination of noise-affecting factors, find in the total noise test information the third sub-noise test information that matches both the noise-affected object and the noise source area included in the combination of noise-affecting factors, and the first parent noise test information that matches the noise-affected object included in the combination of noise-affecting factors. Furthermore, according to the circuit board parameter group corresponding to the circuit board to be evaluated, the target device can find in the third sub-noise test information the noise value that matches all the circuit board parameters in the circuit board parameter group corresponding to the circuit board to be evaluated. In this way, for each combination of noise-affecting factors, the target device can find in the total noise test information the noise value corresponding to the combination of noise-affecting factors. Furthermore, the target device can combine the noise values corresponding to each combination of noise-affecting factors into a noise value combination, and find in the first parent noise test information the total noise value that matches each noise value in the noise value combination, that is, determine the noise value corresponding to the circuit board to be evaluated.

[0130] The specific processing of steps S801 to S802 can refer to the above process of finding the first noise value, and will not be elaborated here.

[0131] Step S803, determine the noise test result according to the noise value corresponding to the circuit board to be evaluated and the maximum noise threshold.

[0132] Specifically, the target device can determine whether the noise value corresponding to the circuit board to be evaluated is less than or equal to the maximum noise threshold. If so, it can determine that the noise test result is passed; if not, it can determine that the noise test result is not passed.

[0133] Step S804: After performing an operation corresponding to the noise test result based on the noise test result, generate noise evaluation information for the circuit board to be evaluated.

[0134] Among them, the noise evaluation information is used to indicate whether to adjust the circuit board to be evaluated.

[0135] Specifically, the target device can determine whether to adjust the circuit board to be evaluated according to the noise test result, and directly output the noise test result when it is determined that no adjustment is required, or output the noise test result and give adjustment opinions when it is determined that adjustment is required. Accordingly, the target device can perform the following specific steps:

[0136] Step 1: When the noise test result fails, select at least one circuit board parameter group with a noise value less than or equal to the maximum noise threshold from the total noise test information according to the maximum noise threshold, the noise-affected object, and the noise source area.

[0137] Step 2: Determine at least one recommended circuit board parameter group according to each circuit board parameter group with a noise value less than or equal to the maximum noise threshold and the circuit board parameter group corresponding to the circuit board to be evaluated.

[0138] Step 3: Generate noise evaluation information according to the noise test result and each recommended circuit board parameter group.

[0139] Step 4: When the noise test result passes, directly determine the noise test result as the noise evaluation information.

[0140] Specifically, when the target device determines that the noise test result passes, it can directly determine the noise test result as the noise evaluation information. In this way, the technical personnel can know that the current circuit board to be evaluated meets the noise regulations. Or, when the target device determines that the noise test result fails, it determines the circuit board parameter group with a noise value less than or equal to the maximum noise threshold in the second sub-noise test information (hereinafter simply referred to as the candidate circuit board parameter group).

[0141] The target device can calculate the difference value between the circuit board parameter group corresponding to the circuit board to be evaluated and each candidate circuit board parameter group. Furthermore, the target device can determine whether there is a candidate circuit board parameter group with a difference value less than the preset threshold between the circuit board parameter groups corresponding to the circuit board to be evaluated. If so, the target device can use the candidate circuit board parameter group with a difference value less than the preset threshold as the recommended circuit board parameter group. If not, the target device can select the candidate circuit board parameter group with the smallest difference value as the recommended circuit board parameter group.

[0142] The above process of calculating the difference value can adopt the calculation formula of Euclidean distance. For example, the following formula (5) or formula (6) can be adopted:

[0143] Formula (5)

[0144] Where V is the difference value, k is the number of circuit board parameters in the circuit board parameter group corresponding to the circuit board to be evaluated (the same as the number of circuit board parameters in the candidate circuit board parameter group), is the i-th circuit board parameter in the candidate circuit board parameter group, is the i-th circuit board parameter in the circuit board parameter group corresponding to the circuit board to be evaluated.

[0145] Formula (6)

[0146] Where V is the difference value, k is the number of circuit board parameters in the circuit board parameter group corresponding to the circuit board to be evaluated, is the i-th circuit board parameter in the candidate circuit board parameter group, is the i-th circuit board parameter in the circuit board parameter group corresponding to the circuit board to be evaluated, is the weight value corresponding to the i-th circuit board parameter.

[0147] In this way, by selecting the candidate circuit board parameter group with a smaller difference value, when the technician adjusts the circuit, it can not only ensure that the influence of the noise value is within the specified range, but also improve the convenience of adjusting the circuit board. And by further introducing the weight value corresponding to the circuit board parameter, the recommended circuit board parameter can be selected more flexibly. For the circuit board parameter with a smaller weight value, the probability of adjustment can be reduced, and for the circuit board parameter with a larger weight value, the probability of adjustment can be increased. In this way, the process of adjusting the circuit board can be focused on a small number of circuit board parameters, improving the adjustment efficiency and operation simplicity.

[0148] In some alternative embodiments, the target device can also directly determine all circuit board parameter groups with a noise value less than or equal to the maximum noise threshold as the recommended circuit board parameter groups. In this way, a wider selection range can be given, allowing the technician to adjust the design of the circuit board to be evaluated based on this.

[0149] The noise assessment method provided by the embodiments of the present application can, during the process of assessing a circuit board, first obtain the circuit board parameter group, noise impact object, noise source area, and maximum noise threshold of the current circuit board (i.e., the circuit board to be evaluated). Furthermore, based on the circuit board parameter group, noise impact object, and noise source area, the noise value corresponding to the circuit board to be evaluated can be determined from the pre-obtained total noise test information. In this way, real-time noise testing is not required, and the assessment efficiency can be improved. Additionally, according to the noise value corresponding to the circuit board to be evaluated and the maximum noise threshold corresponding to the circuit board to be evaluated, the noise test result can be determined, and then noise assessment information can be generated based on the noise test result to indicate whether a technician should adjust the evaluated circuit board, thereby enabling precise adjustment of circuit board parameters instead of directly using relatively large circuit board parameters for circuit board design, and reducing the occurrence of hardware resource waste problems.

[0150] Taking the noise impact object as a trace and the noise source area including the field effect transistor area and the phase area as an example, the process of the noise test information generation method will be described in detail below.

[0151] The circuit diagram of the power supply can be as Figure 9 shown. The power supply includes an input inductor, an input capacitor, multiple ground points, a power pulse width adjustment controller, an upper field effect transistor, a lower field effect transistor, an output inductor, a transformer inductor (with a transformer node 1 and a transformer node 2 on both sides of the transformer inductor), an output capacitor, a phase node, a low-voltage load, a return point, and other multiple nodes. Among them, the transformer node 1 is connected to the output inductor, the transformer node 2 is connected to the next phase, the high voltage remains high after passing through the input inductor, and after passing through the transformer inductor, a low voltage is output, and the low voltage can be output to the low-voltage load. The circuit board layout diagram of the power supply can be as Figure 10 shown, including a field effect transistor node, a phase node, an input inductor, a power input node, a capacitor, a resistor, a startup network, a phase network, a ground, an output inductor, a transformer node 1, a transformer node 2, a power output, and other multiple nodes. Among them, the thick black wireframe indicates the noise source area.

[0152] Step 1, according to the trace, and the field effect transistor area and the phase area, two noise factor combinations can be determined, namely [trace, field effect transistor area] and [trace, phase area].

[0153] Step 2, according to the determined [trace, field effect transistor area] and [trace, phase area], the circuit board parameters corresponding to [trace, field effect transistor area] include the spacing between the noise hole and the trace, and the number of ground layers between the power plane and the trace, and the circuit board parameters corresponding to [trace, phase area] include the spacing between the power plane and the trace, and the number of ground layers between the power plane and the trace.

[0154] Step 3: Generate the circuit board parameter groups as shown in Table 1 and Table 2. Table 1 includes multiple circuit board parameter groups corresponding to [trace, field effect transistor region], and Table 2 includes multiple circuit board parameter groups corresponding to [trace, phase region]. One row of data in the table corresponds to one circuit board parameter group.

[0155] Table 1

[0156]

[0157] Table 2

[0158]

[0159] Step 4: Conduct noise tests on the test circuit boards corresponding to each circuit board parameter group in Table 1 and Table 2 respectively, and obtain the noise values corresponding to each circuit board parameter group.

[0160] Step 5: Generate a noise test table corresponding to [trace, field effect transistor region], refer to Table 3, and a noise test table corresponding to [trace, phase region] (i.e., sub-noise test information corresponding to the noise factor combination), refer to Table 4.

[0161] Table 3

[0162]

[0163] Table 4

[0164]

[0165] Step 6: Arrange and combine the noise values in the third column of Table 3 and the noise values in the third column of Table 4 to obtain Table 5. Each row in Table 5 is a noise value combination.

[0166] Table 5

[0167]

[0168] Step 7: Calculate the total noise value corresponding to each noise value according to the above formula (2).

[0169] Table 6

[0170]

[0171] The above Table 3, Table 4 and Table 6 together constitute the total noise test information.

[0172] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0173] An embodiment of the present application further provides a noise test information generation device, as Figure 11 shown, including:

[0174] A first acquisition module 1110, configured to acquire at least one noise-affected object and at least one noise source area;

[0175] A combination module 1120, configured to respectively combine any one of the at least one noise-affected object and any one of the at least one noise source area in pairs to obtain at least one noise factor combination;

[0176] A first generation module 1130, configured to generate a plurality of circuit board parameter groups corresponding to each noise factor combination according to the noise-affected object and the noise source area in each noise factor combination, and the circuit board parameters in the pre-constructed circuit board parameter pool that match the noise factor combination;

[0177] A test module 1140, configured to perform noise tests on the test circuit boards corresponding to each circuit board parameter group respectively to obtain the noise values corresponding to each circuit board parameter group;

[0178] The first generation module 1130 is further configured to generate total noise test information according to each noise factor combination, the plurality of circuit board parameter groups respectively corresponding to each noise factor combination, and the noise values corresponding to each circuit board parameter group, so as to evaluate whether the noise of the circuit board is within a preset noise range.

[0179] In some optional embodiments, the first generation module 1130 is specifically configured to:

[0180] Select at least one circuit board parameter that matches both the target noise-affected object and the target noise source area included in the target noise factor combination from the circuit board parameter pool, where the target noise factor combination is any one of the plurality of noise factor combinations;

[0181] According to each circuit board parameter, obtain the parameter value generation rule corresponding to each circuit board parameter;

[0182] Generate a plurality of circuit board parameter groups corresponding to the target noise factor combination according to the parameter value generation rule corresponding to each circuit board parameter and the preset permutation and combination rule.

[0183] In some alternative embodiments, the noise test information generating device may further include a verification module 1150:

[0184] Obtain a first circuit board parameter set, a first noise-affected object, and a first noise source area corresponding to the verification circuit board;

[0185] Determine a first noise value corresponding to the verification circuit board in the total noise test information according to the first circuit board parameter set, the first noise-affected object, and the first noise source area;

[0186] Perform a noise test on the verification circuit board to obtain a second noise value;

[0187] Determine whether to update the total noise test information according to the first noise value and the second noise value;

[0188] When it is determined to update the total noise test information, add the noise compensation circuit board parameters corresponding to the first noise-affected object to the circuit board parameter pool for re-performing the noise test to update the total noise test information.

[0189] In some alternative embodiments, the test module 1140:

[0190] Adjust the state of the power supply connected to the target test circuit board to perform a noise test on the target test circuit board, where the target test circuit board is a test circuit board corresponding to a second circuit board parameter set, and the second circuit board parameter set is any one of the multiple circuit board parameter sets corresponding to each noise factor combination;

[0191] And send a test instruction to the noise measuring instrument connected to the target test circuit board to instruct the noise measuring instrument to monitor and feedback the target noise test information of the target test circuit board;

[0192] Analyze the target noise test information to obtain a target noise value corresponding to the second circuit board parameter set.

[0193] In some alternative embodiments, the first generation module 1130 is specifically configured to:

[0194] Generate sub-noise test information corresponding to the target noise factor combination according to each circuit board parameter set in the multiple circuit board parameter sets corresponding to the target noise factor combination and the noise value of each circuit board parameter set in the multiple circuit board parameter sets corresponding to the target noise factor combination;

[0195] Generate total noise test information according to the sub-noise test information corresponding to each noise factor combination.

[0196] In some alternative embodiments, the first generation module 1130 is specifically configured to:

[0197] The sub-noise test information corresponding to each combination of all noise factors is jointly determined as the total noise test information.

[0198] In some alternative embodiments, the total noise test information is generated according to the sub-noise test information corresponding to each combination of noise factors, including:

[0199] When it is determined that there are multiple combinations of noise factors to be processed including the target noise-affected object, the parent noise test information corresponding to the target noise-affected object is generated according to the sub-noise test information corresponding to each combination of noise factors to be processed;

[0200] The sub-noise test information corresponding to each combination of all noise factors and the parent noise test information corresponding to each noise-affected object are jointly determined as the total noise test information.

[0201] In some alternative embodiments, the first generation module 1130 is specifically configured to:

[0202] In the current processing round, a noise value corresponding to the current processing round is respectively extracted from the sub-noise test information corresponding to each combination of noise factors to be processed and combined to obtain a noise value combination corresponding to the current processing round;

[0203] After the last processing round is completed, multiple noise value combinations are obtained;

[0204] According to all the noise values included in the target noise value combination, the total noise value corresponding to the target noise value combination is calculated, where the target noise value combination is any one of the multiple noise value combinations;

[0205] According to each noise value combination and the total noise value corresponding to each noise value combination, the parent noise test information corresponding to the target noise-affected object is generated.

[0206] In some alternative embodiments, according to all the noise values included in the target noise value combination, the total noise value corresponding to the target noise value combination is calculated using the following expression:

[0207]

[0208] where T is the total noise value corresponding to the target noise value combination, A i is the noise value extracted from the i-th combination of noise factors to be processed, n is the number of combinations of noise factors to be processed, and i is an integer less than or equal to n and greater than 0.

[0209] For the description of the features in the embodiments corresponding to the noise test information generation device, reference can be made to the relevant descriptions in the embodiments corresponding to the noise test information generation method, which will not be elaborated here one by one.

[0210] An embodiment of the present application also provides a noise evaluation device, as Figure 12 shown, including:

[0211] A second acquisition module 1210, configured to acquire a circuit board parameter group, a noise influence object, a noise source area, and a maximum noise threshold corresponding to the circuit board to be evaluated;

[0212] A determination module 1220, configured to determine a noise value corresponding to the circuit board to be evaluated in the pre-acquired total noise test information according to the circuit board parameter group, the noise influence object, and the noise source area, where the total noise test information is generated according to the above-mentioned noise test information generation method; and determine a noise test result according to the noise value corresponding to the circuit board to be evaluated and the maximum noise threshold;

[0213] A second generation module 1230, configured to generate noise evaluation information for the circuit board to be evaluated after performing an operation corresponding to the noise test result according to the noise test result, where the noise evaluation information is used to indicate whether to adjust the circuit board to be evaluated.

[0214] In some alternative embodiments, the second generation module 1230 is specifically configured to:

[0215] When the noise test result fails, at least one circuit board parameter group whose noise value is less than or equal to the maximum noise threshold is selected from the total noise test information according to the maximum noise threshold, the noise influence object, and the noise source area;

[0216] Determine at least one recommended circuit board parameter group according to each circuit board parameter group whose noise value is less than or equal to the maximum noise threshold and the circuit board parameter group corresponding to the circuit board to be evaluated;

[0217] Generate noise evaluation information according to the noise test result and each recommended circuit board parameter group.

[0218] In some alternative embodiments, the second generation module 1230 is specifically configured to:

[0219] When the noise test result passes, directly determine the noise test result as the noise evaluation information.

[0220] For the description of the features in the embodiments corresponding to the noise evaluation device, reference can be made to the relevant descriptions in the embodiments corresponding to the noise evaluation method, which will not be elaborated here one by one.

[0221] An embodiment of the present application also provides an electronic device, asFigure 13 As shown, it includes a memory 10 and a processor 20. A computer program is stored in the memory 10, and the processor 20 is configured to run the computer program to execute the steps in any of the above-described embodiments of the noise test information generation method or the noise evaluation method.

[0222] An embodiment of the present application further provides a computer-readable storage medium in which a computer program is stored. The computer program is configured to execute the steps in any of the above-described embodiments of the noise test information generation method or the noise evaluation method when running.

[0223] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: USB flash drives, read-only memories (ROM), random access memories (RAM), mobile hard disks, magnetic disks, or optical discs, etc., various media that can store computer programs.

[0224] An embodiment of the present application further provides a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above-described embodiments of the noise test information generation method or the noise evaluation method.

[0225] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above-described embodiments of the noise test information generation method or the noise evaluation method.

[0226] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described according to their functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Skilled professionals can use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of the present application.

[0227] The above has introduced in detail a method, apparatus, electronic device, storage medium, and program product for generating noise test information and performing noise assessment provided by the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of the present application, several improvements and modifications can still be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A method for generating noise test information, characterized in that, Including: Obtain at least one noise - affected object and at least one noise - source region; Pair - wise combine any one of the at least one noise - affected object and any one of the at least one noise - source region respectively to obtain at least one noise - factor combination; According to the target noise - affected object and the target noise - source region included in the target noise - factor combination, select at least one circuit - board parameter that matches both the target noise - affected object and the target noise - source region from a pre - constructed circuit - board parameter pool, where the target noise - factor combination is any one of the multiple noise - factor combinations; According to each of the circuit - board parameters, obtain a parameter - value generation rule corresponding to each of the circuit - board parameters; According to the parameter - value generation rule corresponding to each of the circuit - board parameters and a preset permutation and combination rule, generate multiple circuit - board parameter groups corresponding to the target noise - factor combination; Conduct noise tests on the test circuit boards corresponding to each of the circuit - board parameter groups respectively to obtain noise values corresponding to each of the circuit - board parameter groups; Generate total noise - test information based on each of the noise - factor combinations, the multiple circuit - board parameter groups respectively corresponding to each of the noise - factor combinations, and the noise values corresponding to each of the circuit - board parameter groups, so as to evaluate whether the noise of the circuit board is within a preset noise range.

2. The method for generating noise test information according to claim 1, wherein After generating the total noise - test information according to each of the noise - factor combinations, the multiple circuit - board parameter groups respectively corresponding to each of the noise - factor combinations, and the noise values corresponding to each of the circuit - board parameter groups, the method further includes: Obtain a first circuit - board parameter group, a first noise - affected object, and a first noise - source region corresponding to a verification circuit board; Determine a first noise value corresponding to the verification circuit board in the total noise - test information according to the first circuit - board parameter group, the first noise - affected object, and the first noise - source region; Conduct a noise test on the verification circuit board to obtain a second noise value; Determine whether to update the total noise - test information according to the first noise value and the second noise value; When it is determined to update the total noise - test information, add the noise - compensation circuit - board parameter corresponding to the first noise - affected object to the circuit - board parameter pool to re - execute the noise test and update the total noise - test information.

3. The method for generating noise test information according to claim 1, wherein The conducting noise tests on the test circuit boards corresponding to each of the circuit - board parameter groups respectively to obtain noise values corresponding to each of the circuit - board parameter groups includes: Adjust the state of the power supply connected to the target test circuit board to conduct a noise test on the target test circuit board, where the target test circuit board is the test circuit board corresponding to the second circuit - board parameter group, and the second circuit - board parameter group is any one of the multiple circuit - board parameter groups respectively corresponding to each of the noise - factor combinations; And, send a test instruction to a noise measuring instrument connected to the target test circuit board to instruct the noise measuring instrument to monitor and feedback target noise test information of the target test circuit board; Analyze the target noise test information to obtain a target noise value corresponding to the second circuit board parameter group.

4. The method for generating noise test information according to claim 1, wherein The generating of the total noise test information according to each of the noise factor combinations, the multiple circuit board parameter groups respectively corresponding to each of the noise factor combinations, and the noise values corresponding to each of the circuit board parameter groups includes: Generate sub-noise test information corresponding to the target noise factor combination according to each circuit board parameter group in the multiple circuit board parameter groups corresponding to the target noise factor combination and the noise value of each circuit board parameter group in the multiple circuit board parameter groups corresponding to the target noise factor combination; Generate the total noise test information according to the sub-noise test information corresponding to each of the noise factor combinations.

5. The method for generating noise test information according to claim 4, wherein The generating of the total noise test information according to the sub-noise test information corresponding to each of the noise factor combinations includes: Collectively determine the sub-noise test information corresponding to all the noise factor combinations as the total noise test information.

6. The method for generating noise test information according to claim 4, wherein, The generating of the total noise test information according to the sub-noise test information corresponding to each of the noise factor combinations includes: When it is determined that there are multiple to-be-processed noise factor combinations including the target noise influence object, generate parent noise test information corresponding to the target noise influence object according to the sub-noise test information corresponding to each of the to-be-processed noise factor combinations; Collectively determine the sub-noise test information corresponding to all the noise factor combinations and the parent noise test information corresponding to all the noise influence objects as the total noise test information.

7. The method for generating noise test information according to claim 6, wherein The generating of the parent noise test information corresponding to the target noise influence object according to the sub-noise test information corresponding to each of the to-be-processed noise factor combinations when it is determined that there are multiple to-be-processed noise factor combinations including the target noise influence object includes: In the current processing round, extract a noise value corresponding to the current processing round from the sub-noise test information corresponding to each of the to-be-processed noise factor combinations and combine them to obtain a noise value combination corresponding to the current processing round; After completing the last processing round, obtain multiple noise value combinations; Calculate a total noise value corresponding to the target noise value combination according to all the noise values included in the target noise value combination, where the target noise value combination is any one of the multiple noise value combinations; Generate the parent noise test information corresponding to the target noise influence object according to each of the noise value combinations and the total noise value corresponding to each of the noise value combinations.

8. The method for generating noise test information according to claim 7, wherein The calculating of the total noise value corresponding to the target noise value combination according to all the noise values included in the target noise value combination adopts the following expression: Where T is the total noise value corresponding to the combination of the target noise value, and A i is the noise value extracted from the i-th combination of the noise factors to be processed, n is the number of the combinations of the noise factors to be processed, and i is an integer less than or equal to n and greater than 0.

9. A noise assessment method, characterized in that, Includes: Obtain a circuit board parameter group, a noise influence object, a noise source area, and a maximum noise threshold corresponding to the circuit board to be evaluated; Determine, according to the circuit board parameter group, the noise influence object, and the noise source area, a noise value corresponding to the circuit board to be evaluated from pre-obtained total noise test information, where the total noise test information is generated according to the noise test information generation method described in any one of claims 1 to 8; Determine a noise test result according to the noise value corresponding to the circuit board to be evaluated and the maximum noise threshold; After performing an operation corresponding to the noise test result according to the noise test result, generate noise evaluation information for the circuit board to be evaluated, where the noise evaluation information is used to indicate whether to adjust the circuit board to be evaluated.

10. The noise evaluation method according to claim 9, wherein The step of, after performing an operation corresponding to the noise test result according to the noise test result, generating the noise evaluation information for the circuit board to be evaluated includes: When the noise test result fails, select, according to the maximum noise threshold, the noise influence object, and the noise source area, at least one of the circuit board parameter groups with a noise value less than or equal to the maximum noise threshold from the total noise test information; Determine at least one recommended circuit board parameter group according to each of the circuit board parameter groups with a noise value less than or equal to the maximum noise threshold and the circuit board parameter group corresponding to the circuit board to be evaluated; Generate the noise evaluation information according to the noise test result and each of the recommended circuit board parameter groups.

11. The noise assessment method according to claim 10, characterized in that, The method further includes: When the noise test result passes, directly determine the noise test result as the noise evaluation information.

12. An electronic device, characterized in that, including: A memory for storing a computer program; A processor for implementing the steps of the noise test information generation method described in any one of claims 1 to 8, or implementing the steps of the noise evaluation method described in any one of claims 9 to 11 when executing the computer program.

13. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium, where the computer program, when executed by a processor, implements the steps of the noise test information generation method described in any one of claims 1 to 8, or implements the steps of the noise evaluation method described in any one of claims 9 to 11.

14. A computer program product, comprising a computer program, characterized in that, The computer program, when executed by a processor, implements the steps of the noise test information generation method described in any one of claims 1 to 8, or implements the steps of the noise evaluation method described in any one of claims 9 to 11.

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