Microsecond device damage positioning system based on transient voltage method

Abstract

The invention discloses a microsecond-level device damage positioning system based on a transient voltage method, and the system comprises the steps: firstly building a trap characterization test platform which comprises a PPC end, an FPGA master controller, a drive circuit of a drain electrode and a grid electrode, an interception amplification circuit and an acquisition card; connecting three ends of the to-be-tested device into a drive circuit of a drain electrode and a grid electrode; the FPGA master control issues time sequence information to complete trap filling of a hardware circuit and state switching in a test stage; and finally, the acquisition card collects transient voltage at the drain end and the source end of the device which is denoised and amplified by the interception circuit and transmits the transient voltage to a PC end. The transient voltage response curve with microsecond-level time precision can be obtained, the switching speed of the transient voltage response curve is smaller than 1 microsecond, trap information contained in the curve is richer, new microsecond-level traps are obtained through the platform, and therefore the damage position and reason of a device to be tested can be analyzed more accurately.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor device testing, and is mainly used for high-speed and convenient characterization and positioning of internal damage in gallium nitride-based high electron mobility transistor devices. Background Art

[0002] Gallium nitride-based high electron mobility transistor (GaN High Electron Mobility Transistor, GaNHEMT) devices have shown great potential in the field of high-frequency and high-power electronic devices due to their excellent material properties, such as wide bandgap, high electron mobility, high breakdown electric field strength, and high thermal stability. However, when the device is working normally, the temperature of the active area rises and the temperature discontinuity at the interface of heterogeneous materials can easily cause damage to the micro-region structure of the active area of ​​the device. Under DC and pulse voltage stress, the damage of GaN-based HEMT devices will be aggravated, especially under pulse stress, the damage of the device is more serious. In addition, dynamic strong fields will also induce the generation of new traps and defects, accelerating the damage and degradation of the device.

[0003] Studies have shown that there is a mapping relationship between the transient drain current response of the device and the traps inside the device. When the trap energy level in the device captures electrons, the macroscopic manifestation is a decrease in the device drain current, and when the trap energy level releases electrons, it causes the drain current to increase. Based on this, a specific electrical bias is applied to the damaged device to collect the transient drain current response curves of trapping and detrapping electrons. Subsequently, the time constant spectrum is extracted from the curve to analyze the changes in the trap peak value, which can be used to study the evolution mechanism of various traps and locate the damage position.

[0004] Traditional transient drain current acquisition mainly relies on semiconductor parameter analyzers. However, this experimental instrument can only acquire transient drain current changes at the millisecond level. There may be traps with microsecond time constants inside GaN-based HEMT devices, so the trap information contained in the curve is incomplete. In addition, the traditional test circuit based on the transient current method requires a sampling resistor to be connected in series at both ends of the device drain and source, and then a constant voltage is applied to the source of the device and the end of the sampling resistor away from the device. The change of voltage over time at both ends of the sampling resistor is acquired to obtain the change of current over time, which will introduce the error of "voltage drift".

[0005] The technology of the present invention adopts an alternative technology of the transient voltage method to eliminate the voltage drift error existing in the transient current method, and can achieve a switching speed of less than 1 microsecond, so as to obtain a transient drain voltage response curve containing more trap information. The design and use method is fast and accurate and is suitable for damage location analysis of GaN-based HEMT devices. Summary of the invention

[0006] The present invention is based on the GaN-based HEMT device damage location process of the transient current method, that is, collecting transient drain current, proposing time constant spectrum, calculating trap activation energy, and analyzing trap spatial position. A trap characterization test system with a switching speed of less than 1 microsecond using the transient voltage method is designed, which can eliminate the measurement error caused by the series resistance in the traditional transient current method test circuit, and can measure a transient drain voltage response curve with a time accuracy of 1 microsecond and rich trap information. The system can provide a drain voltage of 0 to 20V and a gate voltage of 2 to -10V in the trap filling stage, and can provide a constant maximum test current of 200mA in the measurement stage.

[0007] The transient drain voltage acquisition process is as follows: first, a trap characterization test platform is built, which includes a PPC terminal, an FPGA master control, a drain and gate drive circuit, an interception amplifier circuit, and an acquisition card; then, the three terminals of the device under test are connected to the drain and gate drive circuit; the FPGA master control sends timing information to complete the trap filling of the hardware circuit and the state switching of the test phase; finally, the acquisition card collects the transient voltage at both ends of the device drain and source after being denoised and amplified by the interception circuit and transmits it to the PC terminal. The trap characterization test system of the present invention is shown in the attached figure. Figure 3 shown.

[0008] After placing the device under test damaged by pulse or DC stress on a constant temperature platform, first connect one end of the drain of the device under test to the drain drive circuit. The drain drive circuit includes a drain filling voltage and a drain test current generating circuit. The two circuit modules are connected through a single-pole double-throw analog switch. In the trap filling stage, the single-pole double-throw analog switch opens the drain filling voltage path. The filling drain voltage varies in the range of 0 to 20V. At the same time, a "dummy load" resistor with a resistance value similar to the on-resistance of the device under test is used to pre-generate a test current to reduce the time required for switching. The maximum test current can be 200mA. In the trap measurement stage, the single-pole double-throw analog switch opens the drain test current path and closes the drain voltage generating circuit.

[0009] Secondly, the gate of the device under test needs to be connected to the gate drive circuit. The gate drive circuit is divided into a gate filling voltage and a gate test voltage generation circuit, which are also connected through a single-pole double-throw analog switch. In the trap filling stage, the gate filling voltage ranges from 0 to 10V, and the test voltage ranges from 0 to 2V. In addition, the source can be kept grounded during the entire trap filling and measurement stage.

[0010] The FPGA master is used to switch the state of the trap filling phase and the trap release phase and control the amplification factor of the intercept amplifier circuit. The state switching is achieved by sending different pulse timing information to control the enable signal and selection signal of the single-pole double-throw analog switch of the drain and gate drive circuit. The state switching time is shown in the attached figure. Figure 4The amplification factor is also controlled by the pulse signal sent by the FPGA master control.

[0011] During the trap measurement phase, the interception amplifier circuit will denoise and amplify the amplified signals at both ends of the drain and source of the device under test in real time according to the setting of the amplification factor. At this time, the acquisition card will also collect the denoised and amplified signals in real time.

[0012] After the transient voltage response curve is collected, the time constant spectrum is calculated using the time constant extraction technology based on the Bayesian deconvolution iterative algorithm. The vertical axis is the relative amplitude obtained after processing by the structure function method, and its area reflects the contribution of each type of trap to the transient voltage change. The number of peaks is the number of traps measured, and the horizontal axis corresponding to the trap peak point is the time constant corresponding to the trap, reflecting the time point of the trap action.

[0013] From the above description, it can be seen that the present invention can obtain a transient voltage response curve with microsecond time accuracy, and its switching speed is less than 1 microsecond. The trap information contained in the curve is richer, and new microsecond-level traps are obtained using the platform, thereby more accurately analyzing the damage location and cause of the device under test. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is the trap characterization process of GaN-based HEMT devices based on the transient current method.

[0015] Figure 2 It is a microsecond level trap characterization test system based on transient voltage method.

[0016] Figure 3 It is the electrical stress timing diagram of the transient voltage test curve.

[0017] Figure 4 is the switching time of the trap characterization testbench.

[0018] Figure 5 It is the transient voltage change curve under different frequency pulse stress.

[0019] Figure 6 is the differential amplitude spectrum under pulse voltage stress of different frequencies. DETAILED DESCRIPTION

[0020] The present invention is described in detail below with reference to the accompanying drawings and specific implementation modes for GaN-based HEMT devices.

[0021] The system structure of the present invention is shown in the attached Figure 3As shown, it mainly includes PC end, FPGA master control, drain and gate driving circuit, interception amplifier circuit and acquisition card. Among them, FPGA master control is responsible for the timing control of the three-terminal trap filling and test voltage of the device under test, the drain filling voltage generation circuit in the drain driving circuit is responsible for generating a constant drain voltage during the trap filling process; the gate filling voltage generation circuit in the gate driving circuit is responsible for generating a constant gate voltage during the trap filling process; the drain test current generation circuit in the drain driving circuit is responsible for generating a constant test current during the trap release process, and the interception amplifier circuit is used to amplify and denoise the weak voltage signal at both ends of the drain and source of the device under test during the test process, and finally collect the drain transient voltage information through the high-speed acquisition card and upload it to the computer for calculation and analysis.

[0022] Taking the off-state pulse stress damage experiment of a lateral structure GaN-based HEMT device as an example, in order to obtain a transient drain voltage response curve containing trap information, the following steps can be performed.

[0023] Step 1: First, high drain pulse voltage stress of different frequencies is applied to the device under test. The drain pulse frequencies are 1khz, 10khz, 100khz, 1Mhz, etc., and the stress is applied for 1h.

[0024] Step 2: After applying pulse voltage stress to the device under test, place the damaged device under test DUT on a constant temperature platform at 30°C, connect the drain and gate drive circuits to the drain and gate ports of the device under test respectively, and ground the source. Apply a constant negative gate voltage of -6V between the gate and the source, keep the device under test off, and apply a constant positive drain voltage of 10V between the drain and the source to ensure that the traps are fully filled, and the filling time is 100s.

[0025] Step 3: After the trap filling process lasting 100 seconds is completed, the electrical bias is switched from the filling state to the test state using the FPGA master control. At this time, the gate drive circuit generates a constant voltage V GSTEST (0V) to ensure that the channel of the device under test is opened in the test state, and the drain drive circuit will provide a constant test current I DSTEST (100mA), and the intercept amplifier circuit will amplify the voltage at both ends of the drain and source of the device under test. The amplification factor can be controlled by the FPGA master control. During the entire test phase, the amplified drain-source voltage will be collected in real time by the acquisition card and transmitted to the PC. The timing of the filling and testing phases is shown in the attached figure. Figure 4 shown.

[0026] Step 4: After obtaining the transient drain voltage response curves of the device under test under different pulse stress conditions, as shown in the attached figure Figure 5As shown in the figure, the corresponding time constant spectrum is obtained by using the time constant extraction technique based on the Bayesian deconvolution iterative algorithm. The area enclosed by the peak spectrum envelope is the change in drain-source current. There are three different types of traps, namely DP1, Dp2 and DP3. The traps near 100s may have errors due to insufficient measurement time, so they are not analyzed here. DP1 is a newly measured trap at the microsecond level.

[0027] Step 6: For further analysis, the y value of the time constant spectrum is accumulated by accumulating the points near the peak, and then the data of the x-axis and y-axis are exchanged to obtain the integral amplitude spectrum. The differential amplitude spectrum can be obtained by taking the first-order derivative of the integral amplitude spectrum, as shown in the attached figure. Figure 6 As shown in the figure, as the pulse voltage frequency increases, the total change in drain voltage increases, that is, the higher the pulse frequency, the more serious the damage to the device under test. It is inferred from the increase in the contribution of DP1, DP2 and DP3 to the drain current that the cracking degree of the defects and traps in the active area of ​​the device under test deepens at the original position. Combined with the trap positioning experiment, it can be obtained that DP1, DP2 and DP3 are located at the drain side of the gate-drain edge of the AlGaN layer, the gate side of the gate-drain edge of the AlGaN layer, and the GaN buffer layer, respectively, so the damage position of the device under test can be determined.

[0028] It can be seen from the above description that the microsecond device damage localization system based on the transient voltage method of the present invention, combined with different stress bias schemes, can collect a transient drain voltage response curve with a time resolution of 1 microsecond and rich trap information, and then calculate the corresponding time constant spectrum and differential amplitude spectrum, so as to realize microsecond time precision damage localization analysis of GaN-based HEMT devices.

Claims

1. A microsecond device damage location system based on transient voltage method, characterized in that: It includes PC end, FPGA master control, drain and gate driving circuit, interception amplifier circuit and acquisition card; the FPGA master control is responsible for the timing control of the three-terminal trap filling and test voltage of the device under test, and the drain filling voltage generating circuit in the drain driving circuit is responsible for generating a constant drain voltage during the trap filling process; The gate filling voltage generating circuit in the gate driving circuit is responsible for generating a constant gate voltage during the trap filling process; The drain test current generating circuit in the drain drive circuit is responsible for generating a constant test current during the trap release process. The intercept amplifier circuit is used to amplify and remove noise from the weak voltage signal at both ends of the drain and source of the device under test during the test process. Finally, the drain transient voltage information is collected by a high-speed acquisition card and uploaded to the computer for calculation and analysis.

2. The microsecond level device damage location system based on transient voltage method according to claim 1 is characterized in that: The damage location process of GaN-based HEMT devices based on the transient current method, namely, collecting transient drain current, proposing time constant spectrum, calculating trap activation energy, and analyzing trap spatial position; a trap characterization test system with a switching speed of less than 1 microsecond using the transient voltage method is designed to eliminate the measurement error caused by the series resistance in the transient current method test circuit, and measure the transient drain voltage response curve of trap information with a time accuracy of 1 microsecond; provide a drain voltage of 0 to 20V and a gate voltage of 2 to -10V in the trap filling stage, and provide a constant maximum test current of 200mA in the measurement stage.

3. The microsecond level device damage location system based on transient voltage method according to claim 1 is characterized in that: The transient drain voltage acquisition process is as follows: first, build a trap characterization test platform, which includes the PPC terminal, FPGA master control, drain and gate drive circuits, interception amplifier circuits, and acquisition cards; then connect the three terminals of the device under test to the drain and gate drive circuits; The FPGA master sends timing information to complete the trap filling and state switching of the hardware circuit in the test phase; finally, the acquisition card collects the transient voltage at both ends of the device drain and source after being denoised and amplified by the interception circuit and transmits it to the PC end.

4. The microsecond level device damage location system based on transient voltage method according to claim 1 is characterized in that: After placing the device under test damaged by pulse or DC stress on a constant temperature platform, first connect one end of the drain of the device under test to the drain drive circuit. The drain drive circuit includes a drain filling voltage and a drain test current generating circuit. The two circuits are connected through a single-pole double-throw analog switch. In the trap filling stage, the single-pole double-throw analog switch opens the drain filling voltage path. The filling drain voltage varies in the range of 0 to 20V. At the same time, a "dummy load" resistor with a resistance value similar to the on-resistance of the device under test is used to pre-generate a test current to reduce the time required for switch switching. The maximum test current is 200mA. In the trap measurement stage, the single-pole double-throw analog switch opens the drain test current path and closes the drain voltage generating circuit.

5. The microsecond level device damage location system based on transient voltage method according to claim 1 is characterized in that: Connect one end of the gate of the device under test to the gate drive circuit. The gate drive circuit is divided into a gate fill voltage and a gate test voltage generation circuit, which are connected through a single-pole double-throw analog switch. During the trap filling stage, the gate fill voltage ranges from 0 to 10V, and the test voltage ranges from 0 to 2V. In addition, the source remains grounded during the entire trap filling and measurement stage.

6. The microsecond level device damage location system based on transient voltage method according to claim 1 is characterized in that: The FPGA master is used to switch the states of the trap filling phase and the trap release phase and control the amplification factor of the interception amplifier circuit. The state switching is specifically achieved by sending different pulse timing information to control the enable signal and selection signal of the single-pole double-throw analog switch of the drain and gate drive circuit; the amplification factor is also controlled by the pulse signal sent by the FPGA master.

7. The microsecond level device damage location system based on transient voltage method according to claim 1 is characterized in that: During the trap measurement phase, the interception amplifier circuit will denoise and amplify the amplified signals at both ends of the drain and source of the device under test in real time according to the setting of the amplification factor. At this time, the acquisition card will also collect the denoised and amplified signals in real time.

8. The microsecond level device damage location system based on transient voltage method according to claim 1 is characterized in that: After the transient voltage response curve is collected, the time constant spectrum is calculated using the time constant extraction technology based on the Bayesian deconvolution iterative algorithm. The vertical axis is the relative amplitude obtained after processing by the structure function method, and its area reflects the contribution of each type of trap to the transient voltage change. The number of peaks is the number of traps measured, and the horizontal axis corresponding to the trap peak point is the time constant corresponding to the trap, reflecting the time point of the trap action.

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