Waveguide wafers, composite modulators and their fabrication methods

Abstract

This invention provides a waveguide wafer, a composite modulator, and a method for fabricating the same, relating to the field of electro-optic modulation devices. The waveguide wafer includes: a SiO2 thermal oxide layer on the top surface of a silicon substrate; a first SiO2 cladding layer on the top surface of the SiO2 thermal oxide layer; a waveguide structure within the first SiO2 cladding layer; metal electrodes within the first SiO2 cladding layer and the SiO2 thermal oxide layer; a bonding interface located on the top surface of the first SiO2 cladding layer above the waveguide structure; the SiO2 thickness between the bonding interface and the top surface of the waveguide structure is a preset thickness; the bonding interface is treated to a preset flatness and protected by a sacrificial layer to prevent over-etching during the etching of the second SiO2 cladding layer; the sacrificial layer is removed after the second SiO2 cladding layer is etched; the second SiO2 cladding layer, after etching, is located on the top surface of the first SiO2 cladding layer, excluding the bonding interface. This method can obtain a bonding interface with controllable thickness and a flat surface.

Description

Technical Field

[0001] This invention relates to the field of electro-optic modulation device technology, and in particular to a waveguide wafer, a composite modulator, and a method for fabricating the same. Background Technology

[0002] Bonding technology enables the tight bonding of materials with different structures and functions, thus assembling them into a whole and achieving a combination of different material properties to produce beneficial effects. Die-to-wafer bonding typically employs single or batch bonding methods, attaching individual dies with specific functions to an entire wafer. For silicon photonics chips, combining functional dies with waveguide structures to form composite modulators holds significant application potential. However, such composite modulators are highly sensitive to the distance between the functional dies and the waveguide structure; that is, the spacing between the bonding interface and the underlying waveguide structure has a substantial impact on the optical performance of the waveguide structure. Therefore, strict control of the distance between the bonding interface and the waveguide structure is necessary.

[0003] In existing technical solutions, the method of obtaining the target structure through bonding often results in a large error in the thickness of the bonding layer, which affects the efficiency of the composite modulator after bonding. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a waveguide wafer to solve the technical problem of large bonding layer thickness errors in the prior art. The waveguide wafer includes:

[0005] Silicon substrate 14;

[0006] A SiO2 thermal oxidation layer 13 is disposed on the top surface of the silicon substrate 14;

[0007] The first SiO2 cladding layer 12 is disposed on the top surface of the SiO2 thermal oxidation layer 13;

[0008] Waveguide structure 10 is disposed in the first SiO2 cladding layer 12;

[0009] Metal electrode 11 is disposed in the first SiO2 cladding layer 12 and SiO2 thermal oxidation layer 13;

[0010] The bonding interface 17 is located on the top surface of the first SiO2 cladding 12 above the waveguide structure 10. The SiO2 thickness between the bonding interface 17 and the top surface of the waveguide structure 10 is a preset thickness. The bonding interface 17 is processed to a preset flatness and protected by a sacrificial layer 15 to prevent over-etching during the etching of the second SiO2 cladding 16. The sacrificial layer 15 is removed after the second SiO2 cladding 16 is etched.

[0011] The second SiO2 cladding layer 16 is located on the top surface of the first SiO2 cladding layer 12 in the area other than the bonding interface 17.

[0012] This invention also provides a composite modulator to address the technical problem of large bonding layer thickness errors in the prior art. The composite modulator includes:

[0013] Any of the aforementioned waveguide wafers;

[0014] An optical modulation device 18 is bonded at the bonding interface 17, and the optical modulation device 18 and the waveguide structure 10 below the bonding interface 17 constitute a composite waveguide 19.

[0015] This invention also provides a method for fabricating the aforementioned waveguide wafer to address the technical problem of large bonding layer thickness errors in the prior art. The fabrication method includes:

[0016] The SiO2 thermal oxidation layer 13 is prepared on the top surface of the silicon substrate 14;

[0017] A first SiO2 cladding layer 12 is prepared on the top surface of the SiO2 thermal oxide layer 13, and the waveguide structure 10 is prepared in the first SiO2 cladding layer 12. The metal electrode 11 is prepared in the first SiO2 cladding layer 12 and the SiO2 thermal oxide layer 13.

[0018] The top surface of the first SiO2 cladding 12 is processed such that the SiO2 thickness between the top surface of the processed first SiO2 cladding 12 and the top surface of the waveguide structure 10 is a preset thickness and the top surface of the first SiO2 cladding 12 reaches the preset flatness.

[0019] The sacrificial layer 15 is prepared on the top surface of the first SiO2 cladding 12 above the waveguide structure 10;

[0020] The second SiO2 cladding layer 16 is deposited to cover the first SiO2 cladding layer 12 and the sacrificial layer 15. The second SiO2 cladding layer 16 is etched until the sacrificial layer 15 is completely exposed.

[0021] The bonding interface 17 is obtained by removing the sacrificial layer 15.

[0022] Compared with the prior art, the beneficial effects that can be achieved by at least one of the above-mentioned technical solutions adopted in the embodiments of this specification include at least the following: The bonding interface 17 of the waveguide wafer is located on the top surface of the first SiO2 cladding layer 12 above the waveguide structure 10; the SiO2 thickness between the bonding interface 17 and the top surface of the waveguide structure 10 is a preset thickness; the bonding interface 17 is processed to a preset flatness and protected by a sacrificial layer 15 to prevent over-etching during the etching of the second SiO2 cladding layer 16; the sacrificial layer 15 is removed after the second SiO2 cladding layer 16 is etched, thus achieving a preset thickness of SiO2 thickness (i.e., bonding interface thickness) between the bonding interface 17 and the top surface of the waveguide structure 10 that is controllable. This reduces or avoids the impact of bonding interface thickness errors on the efficiency of the composite modulator after bonding. Furthermore, when the waveguide structure 10 and the metal electrode 11 are both located below the bonding interface of the waveguide wafer, after the SiO2 thickness between the bonding interface 17 and the top surface of the waveguide structure 10 reaches a preset thickness and a preset flatness, the bonding interface 17 is protected by a sacrificial layer 15. The sacrificial layer 15 serves as an etching stop layer to protect the bonding interface 17 from over-etching during the etching of the second SiO2 cladding layer 16. Finally, the sacrificial layer is removed by a wet etching process to obtain a bonding interface 17 with controllable thickness and a flat surface. This is beneficial to improving the stability of subsequent bonding processes, as well as the stability and efficiency of the optical performance of the control device. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of a cross-sectional structure for etching the second SiO2 cladding layer 16 according to an embodiment of the present invention;

[0025] Figure 2 This is a schematic diagram of a cross-sectional structure of the embedded metal electrode 11 provided in an embodiment of the present invention;

[0026] Figure 3 This is a schematic cross-sectional view of a first SiO2 cladding layer 12 deposited using a cladding filling method according to an embodiment of the present invention.

[0027] Figure 4 This is a schematic diagram of the cross-sectional structure of the first SiO2 cladding 12 after CMP, provided by an embodiment of the present invention;

[0028] Figure 5This is a schematic diagram of a cross-sectional structure of a first SiO2 cladding layer 12 grown by deposition according to an embodiment of the present invention;

[0029] Figure 6 This is a schematic diagram of a cross-sectional structure for preparing a sacrificial layer 15 according to an embodiment of the present invention;

[0030] Figure 7 This is a schematic diagram of a cross-sectional structure after deposition of a second SiO2 cladding layer 16 according to an embodiment of the present invention;

[0031] Figure 8 This is a schematic diagram of a cross-sectional structure for removing the sacrificial layer 15 according to an embodiment of the present invention;

[0032] Figure 9 This is a schematic cross-sectional view of an optical modulation device 18 bonded at the bonding interface 17, provided by an embodiment of the present invention.

[0033] Figure 10 This is a schematic cross-sectional view of a method for preparing the first sacrificial layer 151 according to an embodiment of the present invention;

[0034] Figure 11 This is a schematic cross-sectional view of a method for preparing a second sacrificial layer 152 and then depositing a second SiO2 cladding layer 16 according to an embodiment of the present invention.

[0035] Figure 12 This is a schematic cross-sectional view of an etching of the second SiO2 cladding layer 16 and the third SiO2 cladding layer 161 provided in an embodiment of the present invention;

[0036] Figure 13 This is a schematic cross-sectional view of a structure with the first sacrificial layer 151 and the second sacrificial layer 152 removed, provided by an embodiment of the present invention.

[0037] Figure 14 This is a schematic diagram of a cross-sectional structure of a modulator material bonded at a first bonding interface 171 and a second bonding interface 172, provided by an embodiment of the present invention.

[0038] Figure 15 This is a flowchart of a waveguide wafer fabrication method provided in an embodiment of the present invention.

[0039] Figure reference numerals:

[0040] 10. Waveguide structure; 11. Metal electrode; 12. First SiO2 cladding; 13. SiO2 thermal oxidation layer; 14. Silicon substrate; 15. Sacrificial layer; 16. Second SiO2 cladding; 17. Bonding interface; 18. Optical modulation device; 19. Composite waveguide; 151. First sacrificial layer; 152. Second sacrificial layer; 161. Third SiO2 cladding; 171. First bonding interface; 172. Second bonding interface; 181. First modulator material; 182. Second modulator material. Detailed Implementation

[0041] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0042] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0043] In an embodiment of the present invention, a waveguide wafer is provided, such as... Figure 1 , Figure 8 As shown, the waveguide wafer includes:

[0044] Silicon substrate 14;

[0045] A SiO2 thermal oxidation layer 13 is disposed on the top surface of the silicon substrate 14;

[0046] The first SiO2 cladding layer 12 is disposed on the top surface of the SiO2 thermal oxidation layer 13;

[0047] Waveguide structure 10 is disposed in the first SiO2 cladding layer 12;

[0048] Metal electrode 11 is disposed in the first SiO2 cladding layer 12 and SiO2 thermal oxidation layer 13;

[0049] Keying interface 17 (e.g.) Figure 8As shown), the top surface of the first SiO2 cladding 12 located above the waveguide structure 10, wherein the SiO2 thickness between the bonding interface 17 and the top surface of the waveguide structure 10 is a preset thickness, the bonding interface 17 is processed to a preset flatness and protected by a sacrificial layer 15 to prevent over-etching during the etching of the second SiO2 cladding 16, and the sacrificial layer 15 is removed after the second SiO2 cladding 16 is etched;

[0050] The second SiO2 cladding layer 16 is located on the top surface of the first SiO2 cladding layer 12 in the area other than the bonding interface 17.

[0051] Depend on Figure 1 , Figure 8 As shown, in this embodiment of the invention, the bonding interface 17 of the waveguide wafer is located on the top surface of the first SiO2 cladding 12 above the waveguide structure 10. The SiO2 thickness between the bonding interface 17 and the top surface of the waveguide structure 10 is a preset thickness. The bonding interface 17 is processed to a preset flatness and protected by a sacrificial layer 15 to prevent over-etching during the etching of the second SiO2 cladding 16. The sacrificial layer 15 is removed after the second SiO2 cladding 16 is etched. This achieves a preset thickness where the SiO2 thickness (i.e., the bonding interface layer thickness) between the bonding interface 17 and the top surface of the waveguide structure 10 is controllable, thereby reducing or avoiding over-etching due to bonding interface thickness issues. Thickness errors affect the efficiency of the composite modulator after bonding. In addition, when the waveguide structure 10 and the metal electrode 11 are both located below the bonding interface of the waveguide wafer, after the SiO2 thickness between the bonding interface 17 and the top surface of the waveguide structure 10 reaches a preset thickness and a preset flatness, the bonding interface 17 is protected by a sacrificial layer 15. The sacrificial layer 15 serves as an etching stop layer to protect the bonding interface 17 from over-etching during the etching of the second SiO2 cladding layer 16. Finally, the sacrificial layer is removed by a wet etching process to obtain a bonding interface 17 with controllable thickness and a flat surface. This is beneficial to improving the stability of subsequent bonding processes, as well as the stability and efficiency of the optical performance of the control device.

[0052] In practical implementation, in existing technologies, sacrificial layer technology is mostly used to release and obtain specific structures. Its main function is to provide necessary structural support or serve as a temporary substrate at a certain stage of device manufacturing, and then it is intentionally removed in subsequent steps to release or form the desired structure, such as microstructure bridges, cantilever beams, or cavities. However, this application does not obtain specific structures through sacrificial layer release, but uses the sacrificial layer 15 as an etching stop layer to protect the bonding interface 17 from over-etching during the etching of the second SiO2 cladding layer 16, thereby protecting the bonding interface 17 to maintain controllable thickness and surface flatness. However, existing technologies do not employ sacrificial layer technology for thickness control and protection of bonding interfaces in silicon photonics chips.

[0053] For example, the waveguide wafer (or silicon photonic chip) of this application is a special optical modulation structure in which the waveguide structure 10 and the metal electrode 11 are both located below the bonding interface 17. The fabrication of the waveguide structure 10 and the metal electrode 11 will inevitably lead to unevenness in the bonding interface 17, which will increase optical loss and reduce bonding reliability. This application proposes to deposit a sacrificial layer 15 on the bonding interface 17 as an etch stop layer after controlling the thickness of the cladding bonding interface 17 on the waveguide structure 10 to reach a preset thickness and a preset flatness. This protects the bonding interface 17 from over-etching during the etching of the second SiO2 cladding layer 16, thereby ensuring that the thickness of the bonding interface 17 is controllable and the surface is flat. After removing the sacrificial layer 15 by wet etching, a bonding interface 17 with controllable thickness and a flat surface can be obtained.

[0054] In specific implementations, the thickness of the waveguide structure 10 can be 200–450 nm, and the material of the waveguide structure 10 can be silicon nitride, silicon, etc.; the material of the metal electrode 11 can be AlCu or Cu; the thickness of the metal electrode 11 can be 500–1500 nm; the thickness of the first SiO2 cladding layer 12 can be 0.6–1.6 μm; the thickness of the SiO2 thermal oxidation layer 13 can be 2–8 μm; the thickness of the silicon substrate 14 can be 500–800 μm; and the thickness of the second SiO2 cladding layer 16 can be 1–4 μm.

[0055] In specific implementation, in order to ensure that the modulator material bonded to the waveguide structure 10 and the bonding interface 17 can form a composite waveguide, the preset thickness of SiO2 between the bonding interface 17 and the top surface of the waveguide structure 10 can be 50 to 150 nm.

[0056] In specific implementations, the material of the sacrificial layer can be one of Al, AlCu, TiN, or α-Si, preferably Al. The thickness of the sacrificial layer can be 100 nm.

[0057] In specific implementations, to improve the structural diversity of waveguide wafers, achieve different composite waveguide spacings, and obtain composite optical waveguide modulators with different modulation efficiencies, it is proposed that the bonding interface 17 can be located at one point, on the top surface of the first SiO2 cladding 12 above all the waveguide structures 10, such as... Figure 8 As shown. Furthermore, the bonding interface 17 can be multiple locations, with different bonding interfaces 17 situated on the top surface of the first SiO2 cladding 12 above different waveguide structures 10. The SiO2 thickness between the bonding interface 17 and the top surface of the corresponding waveguide structure 10 varies at different locations, such as... Figure 13 As shown, the bonding interface 17 includes a first bonding interface 171 and a second bonding interface 172. There may be one or more first bonding interfaces 171 and one or more second bonding interfaces 172.

[0058] In specific implementation, based on any of the aforementioned waveguide wafers, this application also proposes a composite modulator, comprising:

[0059] Any of the aforementioned waveguide wafers;

[0060] An optical modulator 18 is bonded at the bonding interface 17, and the optical modulator 18 and the waveguide structure 10 below the bonding interface 17 constitute a composite waveguide 19. When the bonding interface 17 is at one location, the resulting composite modulator is as follows: Figure 9 As shown; when there are multiple bonding interfaces 17, including a first bonding interface 171 and a second bonding interface 172, the first optical modulator 181 is bonded at the first bonding interface 171, and the second optical modulator 182 is bonded at the second bonding interface 172, forming a composite modulator as shown. Figure 14 As shown.

[0061] In specific implementation, to achieve the fabrication of the aforementioned waveguide wafer, this application also provides a method for fabricating any of the aforementioned waveguide wafers, such as... Figure 15 As shown, it includes:

[0062] Step S1501: Prepare the SiO2 thermal oxidation layer 13 on the top surface of the silicon substrate 14;

[0063] Step S1502: A first SiO2 cladding layer 12 is prepared on the top surface of the SiO2 thermal oxide layer 13, and the waveguide structure 10 is prepared in the first SiO2 cladding layer 12. The metal electrode 11 is prepared in the first SiO2 cladding layer 12 and the SiO2 thermal oxide layer 13, as follows. Figure 2 As shown;

[0064] Step S1503: Process the top surface of the first SiO2 cladding 12 so that the SiO2 thickness between the top surface of the processed first SiO2 cladding 12 and the top surface of the waveguide structure 10 is a preset thickness and the top surface of the first SiO2 cladding 12 reaches the preset flatness (the preset flatness can be a flatness that meets the bonding requirements).

[0065] Step S1504: Prepare the sacrificial layer 15 on the top surface of the first SiO2 cladding 12 above the waveguide structure 10;

[0066] Step S1505: Deposit the second SiO2 cladding layer 16 to cover the first SiO2 cladding layer 12 and the sacrificial layer 15, etch the second SiO2 cladding layer 16 until the sacrificial layer 15 is completely exposed.

[0067] Step S1506: Remove the sacrificial layer 15 to obtain the bonding interface 17.

[0068] In practice, to ensure a bonding interface 17 with controllable thickness and a smooth surface, the embedded metal electrode 11 can be prepared after the fabrication process is complete (e.g., ...). Figure 2 (As shown) After depositing the first SiO2 cladding layer 12, the distance between the top surface of the first SiO2 cladding layer 12 and the top surface of the waveguide structure 10 is controlled so that the SiO2 thickness between the bonding interface 17 and the top surface of the waveguide structure 10 reaches a preset thickness, and the first SiO2 cladding layer 12 is planarized to achieve a preset flatness. To further ensure that the bonding interface 17 can accurately reach the preset thickness and the preset flatness, it is proposed to process the top surface of the first SiO2 cladding layer 12 so that the SiO2 thickness between the top surface of the processed first SiO2 cladding layer 12 and the top surface of the waveguide structure 10 is a preset thickness and the top surface of the first SiO2 cladding layer 12 reaches the preset flatness, including:

[0069] The first SiO2 cladding layer 12 is deposited using a cladding filling method, such as... Figure 3 As shown, the upper surface of the first SiO2 cladding 12 is 300-500 nm higher than the upper surface of the waveguide structure 10;

[0070] The first SiO2 cladding 12 is subjected to CMP planarization, and the CMP is controlled to end on the top surface of the waveguide structure 10, as follows. Figure 4 As shown;

[0071] The first SiO2 cladding layer 12 is grown by deposition, such that the SiO2 thickness between the top surface of the grown first SiO2 cladding layer 12 and the top surface of the waveguide structure 10 is a preset thickness (for example, the upper surface of the first SiO2 cladding layer 12 is 50-150 nm higher than the upper surface of the waveguide structure 10, to obtain a bonding layer with controllable thickness), and the top surface of the first SiO2 cladding layer 12 achieves the preset flatness, resulting in a bonding interface 17 that achieves the preset thickness and preset flatness. Figure 5 As shown.

[0072] In specific implementation, after the bonding interface 17 is processed to achieve a preset thickness and a preset flatness, a sacrificial layer can be prepared to protect the bonding interface 17. For example, taking the preparation of one sacrificial layer as an example, the sacrificial layer 15 is prepared on the top surface of the first SiO2 cladding 12 above the waveguide structure 10, including:

[0073] A sacrificial layer 15 is prepared, which covers the first SiO2 cladding 12 above all waveguide structures 10, such as... Figure 6 As shown.

[0074] In specific implementation, based on Figure 6 After the sacrificial layer 15 is prepared as shown, the second SiO2 cladding layer 16 can be deposited to cover the first SiO2 cladding layer 12 and the sacrificial layer 15, as shown. Figure 7 As shown; then, dry etching is used to etch the second SiO2 cladding layer 16 until the sacrificial layer 15 is reached, at which point the etching stops. The sacrificial layer 15 serves to prevent over-etching, and is completely exposed with some over-etching present, as shown. Figure 1 As shown; finally, the sacrificial layer 15 is removed by wet etching to obtain the bonding interface 17, as shown. Figure 8 As shown. At this point, the distance from the top of the waveguide structure 10 to the bonding interface 17 can be maintained at 50–150 nm, and then the optical modulation device 18 can be bonded at the bonding interface 17, as shown. Figure 9 As shown, the bonding of the modulation device 18 with the waveguide structure 10 below the bonding interface 17 forms a composite waveguide 19, achieving better optical performance, such as reducing coupling loss and increasing optical bandwidth.

[0075] In specific implementation, after the bonding interface 17 is processed to achieve a preset thickness and a preset flatness, a sacrificial layer can be prepared to protect the bonding interface 17. For example, taking the preparation of multiple sacrificial layers as an example, the sacrificial layer 15 is prepared on the top surface of the first SiO2 cladding 12 above the waveguide structure 10, including:

[0076] A first sacrificial layer 151 is fabricated on the top surface of the first SiO2 cladding 12 above a portion of the waveguide structure 10; for example, a 100 nm sacrificial layer (e.g., TiN) is deposited on the first SiO2 cladding 12 and patterned to obtain a patterned first sacrificial layer 151; then a third SiO2 cladding 161 is deposited and CMP is performed, such that the distance between the upper surface of the first sacrificial layer 151 and the upper surface of the third SiO2 cladding 161 is 100 nm. Figure 10 As shown;

[0077] A third SiO2 cladding layer 161 is prepared to cover the first sacrificial layer 151 and the first SiO2 cladding layer 12; for example, the third SiO2 cladding layer 161 is deposited and CMP is performed so that the distance between the upper surface of the first sacrificial layer 151 and the upper surface of the third SiO2 cladding layer 161 is 100 nm. The upper surface of the third SiO2 cladding layer 161 above the first sacrificial layer 151 is the first bonding interface 171. Figure 10 As shown;

[0078] A second sacrificial layer 152 is fabricated on the top surface of the third SiO2 cladding 161 above the waveguide structure 10. The second sacrificial layer 152 and the first sacrificial layer 151 do not overlap in a horizontal projection. For example, a 100nm sacrificial layer is deposited and patterned on the flat surface of the third SiO2 cladding 161 to obtain a patterned second sacrificial layer 152. Then, the second SiO2 cladding 16 is deposited. Figure 11 As shown.

[0079] In specific implementation, based on Figure 11 After preparing the second sacrificial layer 152 and the first sacrificial layer 151, the second SiO2 cladding layer 16 can be deposited, and the second SiO2 cladding layer 16 and the third SiO2 cladding layer 161 can be etched to expose the second sacrificial layer 152 and the first sacrificial layer 151. For example, the second SiO2 cladding layer 16 is deposited, and the second SiO2 cladding layer 16 is etched until the sacrificial layer 15 is completely exposed (at this time, the sacrificial layer 15 includes the second sacrificial layer 152 and the first sacrificial layer 151).

[0080] Deposit the second SiO2 cladding layer 16, covering the third SiO2 cladding layer 161 and the second sacrificial layer 152 (e.g. Figure 11 As shown), the third SiO2 cladding layer 161 and the second SiO2 cladding layer 16 are etched (e.g., using dry etching) until the first sacrificial layer 151 and the second sacrificial layer 152 are reached. The first sacrificial layer 151 and the second sacrificial layer 152 serve to prevent over-etching and protect their corresponding underlying SiO2 cladding layers. The first sacrificial layer 151 and the second sacrificial layer 152 are completely exposed, as shown. Figure 12As shown, removing the first sacrificial layer 151 yields a first bonding interface 171 (e.g., removing the first sacrificial layer 151 using a wet etching method), and removing the second sacrificial layer 152 yields a second bonding interface 172 (e.g., removing the second sacrificial layer 152 using a wet etching method). Figure 13 As shown, the SiO2 thickness (i.e., bonding layer thickness) between the top of the waveguide structure 10 and the first bonding interface 171 can be 100 nm, and the SiO2 thickness (i.e., bonding layer thickness) between the top of the waveguide structure 10 and the second bonding interface 172 can be 300 nm. This allows for the control of different bonding layer thicknesses by patterning the sacrificial layer and adjusting the thickness of the sacrificial layer and the cladding layer.

[0081] Finally, the first modulator material 181 and the second modulator material 182 are bonded to the first bonding interface 171 and the second bonding interface 172, respectively. The first modulator material 181 and the second modulator material 182 form different composite waveguide regions with the corresponding waveguide structures 10, which can realize different composite waveguide spacings and obtain composite optical waveguide modulators with different modulation efficiencies, such as... Figure 14 As shown.

[0082] The embodiments of the present invention achieve the following technical effects: A bonding interface 17 of the waveguide wafer is located on the top surface of the first SiO2 cladding 12 above the waveguide structure 10. The SiO2 thickness between the bonding interface 17 and the top surface of the waveguide structure 10 is a preset thickness. The bonding interface 17 is processed to a preset flatness and protected by a sacrificial layer 15 to prevent over-etching during the etching of the second SiO2 cladding 16. The sacrificial layer 15 is removed after the second SiO2 cladding 16 is etched. This achieves a controllable preset thickness for the SiO2 thickness (i.e., bonding interface thickness) between the bonding interface 17 and the top surface of the waveguide structure 10, thereby reducing or avoiding over-etching due to bonding interface defects. Errors in layer thickness affect the efficiency of the composite modulator after bonding. Furthermore, when the waveguide structure 10 and the metal electrode 11 are both located below the bonding interface of the waveguide wafer, after the SiO2 thickness between the bonding interface 17 and the top surface of the waveguide structure 10 reaches a preset thickness and a preset flatness, the bonding interface 17 is protected by a sacrificial layer 15. The sacrificial layer 15 serves as an etching stop layer to protect the bonding interface 17 from over-etching during the etching of the second SiO2 cladding layer 16. Finally, the sacrificial layer is removed by a wet etching process to obtain a bonding interface 17 with controllable thickness and a flat surface. This is beneficial to improving the stability of subsequent bonding processes, as well as the stability and efficiency of the optical performance of the control device.

[0083] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, various modifications and variations can be made to the embodiments of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A waveguide wafer, characterized in that, include: Silicon substrate (14); A SiO2 thermal oxidation layer (13) is disposed on the top surface of the silicon substrate (14); A first SiO2 cladding layer (12) is disposed on the top surface of the SiO2 thermal oxide layer (13); A waveguide structure (10) is disposed in the first SiO2 cladding (12); A metal electrode (11) is disposed in the first SiO2 cladding layer (12) and the SiO2 thermal oxide layer (13); The bonding interface (17) is located on the top surface of the first SiO2 cladding (12) above the waveguide structure (10). The SiO2 thickness between the bonding interface (17) and the top surface of the waveguide structure (10) is a preset thickness. The bonding interface (17) is processed to a preset flatness and protected by a sacrificial layer (15) to prevent over-etching during the etching of the second SiO2 cladding (16). The sacrificial layer (15) is removed after the second SiO2 cladding (16) is etched. The second SiO2 cladding (16) is located on the top surface of the first SiO2 cladding (12) in the area other than the bonding interface (17).

2. The waveguide wafer as described in claim 1, characterized in that, The bonding interface (17) is located on the top surface of the first SiO2 cladding (12) above all the waveguide structures (10).

3. The waveguide wafer as described in claim 1, characterized in that, The bonding interface (17) is located in multiple places. The bonding interface (17) at different locations is located on the top surface of the first SiO2 cladding (12) above different waveguide structures (10). The SiO2 thickness between the bonding interface (17) at different locations and the top surface of the corresponding waveguide structure (10) is different.

4. The waveguide wafer as described in any one of claims 1 to 3, characterized in that, The material of the sacrificial layer is Al.

5. A composite modulator, characterized in that, include: Waveguide wafer as claimed in any one of claims 1 to 4; An optical modulation device (18) is bonded at the bonding interface (17), and the optical modulation device (18) and the waveguide structure (10) below the bonding interface (17) constitute a composite waveguide (19).

6. A method for fabricating a waveguide wafer according to any one of claims 1 to 4, characterized in that, include: The SiO2 thermal oxide layer (13) is prepared on the top surface of the silicon substrate (14); A first SiO2 cladding (12) is prepared on the top surface of the SiO2 thermal oxide layer (13), and the waveguide structure (10) is prepared in the first SiO2 cladding (12). The metal electrode (11) is prepared in the first SiO2 cladding (12) and the SiO2 thermal oxide layer (13). The top surface of the first SiO2 cladding (12) is processed so that the SiO2 thickness between the top surface of the processed first SiO2 cladding (12) and the top surface of the waveguide structure (10) is a preset thickness and the top surface of the first SiO2 cladding (12) reaches the preset flatness. The sacrificial layer (15) is prepared on the top surface of the first SiO2 cladding (12) above the waveguide structure (10); The second SiO2 cladding layer (16) is deposited to cover the first SiO2 cladding layer (12) and the sacrificial layer (15). The second SiO2 cladding layer (16) is etched until the sacrificial layer (15) is completely exposed. The bonding interface (17) is obtained by removing the sacrificial layer (15).

7. The preparation method according to claim 6, characterized in that, The sacrificial layer (15) is prepared on the top surface of the first SiO2 cladding (12) above the waveguide structure (10), comprising: A sacrificial layer (15) is prepared, which covers the first SiO2 cladding (12) above all the waveguide structures (10).

8. The preparation method according to claim 6, characterized in that, The sacrificial layer (15) is prepared on the top surface of the first SiO2 cladding (12) above the waveguide structure (10), comprising: A first sacrificial layer (151) is prepared on the top surface of the first SiO2 cladding (12) above part of the waveguide structure (10); A third SiO2 cladding layer (161) is prepared to cover the first sacrificial layer (151) and the first SiO2 cladding layer (12); A second sacrificial layer (152) is prepared on the top surface of the third SiO2 cladding (161) above the waveguide structure (10), and the second sacrificial layer (152) and the first sacrificial layer (151) do not overlap in the horizontal projection.

9. The preparation method according to claim 8, characterized in that, A second SiO2 cladding layer (16) is deposited, covering the first SiO2 cladding layer (12) and the sacrificial layer (15). The second SiO2 cladding layer (16) is etched until the sacrificial layer (15) is completely exposed, including: The second SiO2 cladding layer (16) is deposited to cover the third SiO2 cladding layer (161) and the second sacrificial layer (152). The third SiO2 cladding layer (161) and the second SiO2 cladding layer (16) are etched until the first sacrificial layer (151) and the second sacrificial layer (152) are completely exposed. The first sacrificial layer (151) is removed to obtain the first bonding interface (171), and the second sacrificial layer (152) is removed to obtain the second bonding interface (172).

10. The preparation method according to any one of claims 6 to 9, characterized in that, The top surface of the first SiO2 cladding (12) is processed such that the SiO2 thickness between the top surface of the processed first SiO2 cladding (12) and the top surface of the waveguide structure (10) is a preset thickness and the top surface of the first SiO2 cladding (12) reaches the preset flatness, including: The first SiO2 cladding layer (12) is deposited using a cladding filling method; The first SiO2 cladding (12) is subjected to CMP processing, and the CMP is controlled to end on the top surface of the waveguide structure (10); The first SiO2 cladding (12) is grown by deposition, such that the SiO2 thickness between the top surface of the grown first SiO2 cladding (12) and the top surface of the waveguide structure (10) is a preset thickness and the top surface of the first SiO2 cladding (12) reaches the preset flatness.

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