Wafer level intelligent optical computing chip system and architecture

Abstract

The invention relates to the technical field of optical computing, in particular to a wafer-level intelligent optical computing chip system and architecture. The system comprises a high-energy-efficiency information coding compression module used for carrying out multi-channel information channel coding compression on an input matrix to obtain a first coding vector; the reconfigurable information coding compression module is used for carrying out multipath information reconfigurable weight calculation on the input matrix to obtain a second coding vector; the general feature calculation module is used for performing general feature calculation on the first coding vector and the second coding vector to obtain a feature vector; the high-energy-efficiency feature decoding characterization module is used for performing first decoding characterization on the feature vector to obtain a first decoding vector; the reconfigurable feature decoding characterization module is used for performing second decoding characterization on the feature vector to obtain a second decoding vector; and the output module is used for fusing the first decoding vector and the second decoding vector to obtain a target calculation result. The present disclosure supports optical deployment of a higher number of parameters of intelligent computing networks.

Description

Technical Field

[0001] The present disclosure relates to the field of optical computing technology, and in particular to a wafer-level intelligent optical computing chip system and architecture. Background Art

[0002] With the rapid development of artificial intelligence and scientific computing, the complexity and scale of computing needs are also increasing. However, the performance of existing electronic computing is gradually approaching saturation, making it difficult to effectively cope with the increasingly stringent demands of large-scale complex algorithms for computing power and power consumption. Light has natural advantages such as high throughput and low latency during propagation. Optical computing technology that uses photons instead of electrons as computing carriers is seen as the key to breaking the existing computing bottleneck. Summary of the invention

[0003] The present disclosure aims to solve one of the technical problems in the related art at least to some extent.

[0004] To this end, the first objective of the present disclosure is to propose a wafer-level intelligent optical computing chip system.

[0005] The second objective of the present disclosure is to propose a computing method for a wafer-level intelligent optical computing chip system.

[0006] To achieve the above objectives, the first embodiment of the present disclosure proposes a wafer-level intelligent optical computing chip system, including: A high-energy-efficiency information coding and compression module, used to perform multi-channel information channel coding and compression on the input matrix through a diffraction coding device to obtain a first coding vector; A reconfigurable information coding compression module is used to perform multi-path information reconfigurable calculation weights on the input matrix through a phase modulation device or an amplitude modulation device to obtain a second coding vector; A general feature calculation module, used for performing general feature calculation on the first coding vector and the second coding vector to obtain a feature vector; A high energy efficiency feature decoding and characterization module, used for performing a first decoding and characterization on the feature vector to obtain a first decoding vector, wherein the structure of the high energy efficiency feature decoding and characterization module is relatively dual to the structure of the high energy efficiency information coding and compression module; A reconfigurable feature decoding representation module is used to perform a second decoding representation on the feature vector to obtain a second decoding vector, wherein the structure of the reconfigurable feature decoding representation module is relatively dual to the structure of the reconfigurable information coding compression module; An output module is used to fuse the first decoding vector with the second decoding vector to obtain a target calculation result.

[0007] Optionally, the energy-efficient information coding and compression module and the reconfigurable information coding and compression module are deployed together on a wafer.

[0008] Optionally, the general feature calculation module performs general feature calculation on the first coding vector and the second coding vector through a fully reconfigurable arbitrary matrix calculation unit of an MZI or cross-bar structure to obtain a feature vector.

[0009] Optionally, the system further includes an auxiliary module for assisting the wafer-level intelligent optical computing chip system to complete large-scale complex intelligent computing tasks with high parameters.

[0010] Optionally, the auxiliary module includes a high-speed interface array module, a high-speed modulation module, a loading module and a data routing and monitoring module, wherein: The auxiliary module includes a high-speed interface array module for data coupling and reading; The high-speed modulation module is used for high-speed modulation of calculation information; The loading module is used for loading the electric control signal; The data routing and monitoring module is used for data routing and monitoring.

[0011] Optionally, the system includes an array of energy-efficient information coding and compression modules, wherein each diffraction coding device in the array has mutually orthogonal weight distributions and their characteristics are independent of each other.

[0012] Optionally, the output module performs weighted fusion on the first decoding vector and the second decoding vector to obtain a target calculation result.

[0013] To achieve the above-mentioned purpose, the second embodiment of the present disclosure proposes a computing method using the wafer-level intelligent optical computing chip system described in the first aspect, including: Obtaining an input matrix to be calculated, and performing multi-channel information channel coding compression on the input matrix to obtain a first coding vector; The input matrix is ​​subjected to multi-path information reconfigurable calculation weights to obtain a second encoding vector; Performing common feature calculation on the first encoding vector and the second encoding vector to obtain a feature vector; Performing a first decoding representation on the feature vector to obtain a first decoding vector; Performing a second decoding representation on the feature vector to obtain a second decoding vector; The first decoding vector and the second decoding vector are merged to obtain a target calculation result.

[0014] Another object of the present invention is to provide an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the methods described in the above two aspects.

[0015] Another object of the present invention is to provide a computer storage medium, wherein the computer storage medium stores computer executable instructions; after the computer executable instructions are executed by a processor, the computer executes the methods described in the above two aspects.

[0016] In summary, the wafer-level intelligent optical computing chip system and architecture provided by the present invention can support the optical deployment of intelligent computing networks with higher parameter quantities through the division of labor among the high-efficiency information coding and compression module, the reconfigurable information coding and compression module, the general feature computing module, the high-efficiency feature decoding and characterization module, and the reconfigurable feature decoding and characterization module, thereby improving the computing scale and supporting large models with parameter quantities of more than 100 million in the form of optical computing, thereby supporting the efficient computing of the new generation of large-model artificial intelligence.

[0017] Additional aspects and advantages of the present disclosure will be given in part in the following description and in part will be obvious from the following description or learned through practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and / or additional aspects and advantages of the present disclosure will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which: Figure 1 A schematic diagram of the structure of a wafer-level intelligent optical computing chip system provided by an embodiment of the present disclosure; Figure 2 A schematic diagram of the structure of a wafer-level intelligent optical computing chip architecture provided by an embodiment of the present disclosure; Figure 3 A flowchart of a calculation method of a wafer-level intelligent optical computing chip system provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] Embodiments of the present disclosure are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present disclosure, and should not be construed as limiting the present disclosure.

[0020] Currently, for most analog computing architectures, signals may attenuate during transmission and processing, and noise may also affect the quality of the signal. This may lead to errors or instability in the calculation results. For optical computing models, due to factors such as material defects, wavefront errors, and uneven transmission in the optical system, various errors will inevitably be introduced in optical calculations. These errors may affect the accuracy of the calculation results and cause deviations between experimental results and simulation data. If the optical neural network parameters are expanded by simply stacking the number of layers, the errors will gradually accumulate during propagation, eventually causing huge errors in the output.

[0021] In the existing technology, the classification of four vowel sound wave signals can be completed through an array composed of 56 cascaded Mach-Zehnder Interferometers (MZI), or a deep diffraction neural network based on a cascade of optical diffraction masks can be used to achieve visual tasks such as handwritten digit recognition and image saliency detection; the splitting and aggregation of the optical path can give the diffracted light calculation the ability of multi-channel parallel processing.

[0022] However, due to errors in the simulation calculation and optical calibration process, the scalability of the common paradigm of optical computing based on interference and diffraction is limited and cannot be extended to large-scale applications, thus limiting the complexity of intelligent optical computing tasks.

[0023] The present disclosure is described in detail below with reference to specific embodiments.

[0024] Figure 1 The structure diagram of a wafer-level intelligent optical computing chip system provided by the embodiment of the present disclosure is shown in FIG. Figure 1 As shown, the wafer-level intelligent optical computing chip system includes: The high energy efficiency information coding and compression module 101 is used to perform multi-channel information channel coding and compression on the input matrix through a diffraction coding device to obtain a first coding vector; The reconfigurable information coding and compression module 102 is used to calculate the weights of the multi-path information reconfiguration by using a phase modulation device or an amplitude modulation device on the input matrix to obtain a second coding vector; A general feature calculation module 103, used to perform general feature calculation on the first coding vector and the second coding vector to obtain a feature vector; A high energy efficiency feature decoding and characterization module 104, used for performing a first decoding and characterization on the feature vector to obtain a first decoding vector, wherein the structure of the high energy efficiency feature decoding and characterization module is relatively dual to the structure of the high energy efficiency information coding and compression module; A reconfigurable feature decoding representation module 105 is used to perform a second decoding representation on the feature vector to obtain a second decoding vector, wherein the structure of the reconfigurable feature decoding representation module is relatively dual to the structure of the reconfigurable information coding compression module; The output module 106 is used to merge the first decoding vector and the second decoding vector to obtain a target calculation result.

[0025] In one embodiment of the present disclosure, the wafer-level intelligent optical computing chip system is suitable for large-matrix computing. Based on this, the wafer-level intelligent optical computing chip system can be applied to a variety of scenarios, such as the classification of intelligent computing tasks.

[0026] Among them, in one embodiment of the present disclosure, the above-mentioned high-energy-efficiency information coding and compression module can use the on-chip diffraction computing device with pre-trained parameters to perform multi-channel information channel coding and compression on the input matrix to achieve channel redundancy elimination. In one embodiment of the present disclosure, the above-mentioned high-energy-efficiency information coding and compression module is passively modulated and the weights are not reconfigurable, with very high area efficiency and very low computing energy consumption. And, in one embodiment of the present disclosure, the above-mentioned system may include an array of high-energy-efficiency information coding and compression modules that can be set, and each diffraction coding device in the array has a mutually orthogonal weight distribution, and the characteristics of each other are independent. Specifically, on a wafer-level chip system, the array composed of the above-mentioned modules is mainly used for preliminary modulation and semantic extraction of information, and arrays of different sizes can be activated according to the difficulty of the task.

[0027] And, in one embodiment of the present disclosure, the above-mentioned reconfigurable information coding compression module can use a phase modulation device or an amplitude modulation device to provide accurate and reconfigurable calculation weights for the multi-channel information of the input matrix, and fuse the latter multi-channel information. Among them, in one embodiment of the present disclosure, the above-mentioned reconfigurable information coding compression module can be actively modulated and weight-trainable, has a high degree of computational freedom, and can be used for weight migration between different computing tasks in general computing. In one embodiment of the present disclosure, the above-mentioned reconfigurable information coding compression module can be used as a supplement to the aforementioned high-energy-efficiency information coding compression module, and deployed on the wafer in combination with it.

[0028] Furthermore, in one embodiment of the present disclosure, the above-mentioned general feature calculation module can be cascaded and reused in depth or breadth through a fully reconfigurable arbitrary matrix calculation unit of an MZI or cross-bar structure, and the first coding vector and the second coding vector can be subjected to general feature calculation to obtain a feature vector, so as to realize general feature calculation of any scale. Among them, the above-mentioned general feature calculation module performs further high-degree-of-freedom calculation processing on the above-mentioned first coding vector and the second coding vector, and its weights can be flexibly switched according to different tasks. And, in one embodiment of the present disclosure, the above-mentioned general feature calculation module can deploy multiple general feature calculation modules on a wafer-level chip system, which can be selectively activated and expanded according to the calculation scale.

[0029] Furthermore, in one embodiment of the present disclosure, the energy-efficient feature decoding and characterization module can use a structure and pre-trained decoding weights that are opposite to the energy-efficient information coding and compression module to decode and characterize the feature vector of the general feature calculation module and map it to a second decoding vector output by a high-dimensional network intermediate layer. The energy-efficient feature decoding and characterization module can be deployed in a multi-core form on a wafer-level system, and a computing array with orthogonal decoding weights expands the output dimension.

[0030] Furthermore, in one embodiment of the present disclosure, the above-mentioned reconfigurable feature decoding representation module can use a structure and pre-trained weights that are relatively opposite to the reconfigurable information coding compression module as a supplement to the high-energy-efficiency feature decoding representation module to achieve the task versatility of feature decoding representation.

[0031] In one embodiment of the present disclosure, the output module performs weighted fusion of the first decoding vector and the second decoding vector to obtain a target calculation result.

[0032] And, in one embodiment of the present disclosure, the system may further include an auxiliary module for assisting the wafer-level intelligent optical computing chip system to complete large-scale, high-parameter, and complex intelligent computing tasks. The auxiliary module includes a high-speed interface array module, a high-speed modulation module, a loading module, and a data routing and monitoring module. High-speed interface array module for data coupling and readout; High-speed modulation module, used for high-speed modulation of computing information; A loading module, used for loading electric control signals; Data routing and monitoring module, used for data routing and monitoring.

[0033] In one embodiment of the present disclosure, the auxiliary modules can cooperate with the modules to form a wafer-level device array to achieve large-scale complex intelligent computing tasks with high parameters.

[0034] In summary, the wafer-level intelligent optical computing chip system provided in this embodiment can support the optical deployment of intelligent computing networks with higher parameter quantities through the division of labor and cooperation of high-efficiency information coding and compression modules, reconfigurable information coding and compression modules, general feature computing modules, high-efficiency feature decoding and characterization modules, and reconfigurable feature decoding and characterization modules, thereby improving the computing scale and supporting large models with parameter quantities of more than 100 million in the form of optical computing, supporting the efficient computing of the new generation of large-model artificial intelligence, and has broad application prospects, and can be applied to unmanned systems, autonomous driving, ultrafast science and other fields.

[0035] Figure 2 The wafer-level intelligent optical computing chip architecture of the present invention is as follows: Figure 2 As shown in Figure 1, the architecture consists of multiple layers of optical computing chips cascaded together. Each part of the chip is driven by intelligent task goals and reversely designed to ensure optimal computing performance.

[0036] In order to implement the above embodiment, Figure 3 The present disclosure also proposes a computing method using a wafer-level intelligent optical computing chip system. Figure 3 As shown, the method may include the following steps: Step 301: Obtain an input matrix to be calculated, and perform multi-channel information channel coding compression on the input matrix to obtain a first coding vector; Step 302, performing multi-channel information reconstructable calculation weights on the input matrix to obtain a second coding vector; Step 303: perform common feature calculation on the first coding vector and the second coding vector to obtain a feature vector; Step 304: Perform a first decoding representation on the feature vector to obtain a first decoding vector; Step 305: Perform a second decoding representation on the feature vector to obtain a second decoding vector; Step 306: Fuse the first decoding vector and the second decoding vector to obtain a target calculation result.

[0037] The collection, storage, use, processing, transmission, provision and disclosure of user personal information involved in this disclosure shall comply with the relevant laws and regulations and shall not violate public order and good morals.

[0038] It should be noted that personal information from users should be collected for legitimate and reasonable purposes and should not be shared or sold outside of these legitimate uses. In addition, such collection / sharing should be carried out after receiving the user's informed consent, including but not limited to notifying the user to read the user agreement / user notice and sign the agreement / authorization including authorization of relevant user information before the user uses the function. In addition, any necessary steps should be taken to protect and safeguard access to such personal information data and ensure that others who have access to personal information data comply with its privacy policy and procedures.

[0039] The present disclosure anticipates providing implementation schemes for users to selectively block the use or access of personal information data. That is, the present disclosure anticipates providing hardware and / or software to prevent or block access to such personal information data. Once the personal information data is no longer needed, risks can be minimized by limiting data collection and deleting the data. In addition, when applicable, such personal information is de-identified to protect the privacy of the user.

[0040] The acquisition, transmission, storage, use, and processing of data in the technical solution disclosed in this disclosure are in compliance with the relevant provisions of national laws and regulations.

[0041] It should be noted that in the embodiments of the present disclosure, certain software, components, models and other existing solutions in the industry may be mentioned, which should be regarded as exemplary. Their purpose is only to illustrate the feasibility of implementing the technical solution of the present application, but it does not mean that the applicant has or will necessarily use the solution.

[0042] In the description of the aforementioned embodiments, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they contradict each other.

[0043] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present disclosure, "plurality" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0044] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present disclosure includes additional implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present disclosure belong.

[0045] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection with one or more wires (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or otherwise processing in a suitable manner if necessary, and then stored in a computer memory.

[0046] It should be understood that the various parts of the present disclosure can be implemented in hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0047] A person skilled in the art may understand that all or part of the steps in the above-mentioned embodiment method may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0048] In addition, each functional unit in each embodiment of the present disclosure may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0049] The storage medium mentioned above may be a read-only memory, a disk or an optical disk, etc. Although the embodiments of the present disclosure have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations of the present disclosure. A person of ordinary skill in the art may change, modify, replace and modify the above embodiments within the scope of the present disclosure.

Claims

1. A wafer-level intelligent optical computing chip system, characterized in that: include: A high-energy-efficiency information coding and compression module, used to perform multi-channel information channel coding and compression on the input matrix through a diffraction coding device to obtain a first coding vector; A reconfigurable information coding compression module is used to perform multi-path information reconfigurable calculation weights on the input matrix through a phase modulation device or an amplitude modulation device to obtain a second coding vector; A general feature calculation module, used for performing general feature calculation on the first coding vector and the second coding vector to obtain a feature vector; A high energy efficiency feature decoding and characterization module, used for performing a first decoding and characterization on the feature vector to obtain a first decoding vector, wherein the structure of the high energy efficiency feature decoding and characterization module is relatively dual to the structure of the high energy efficiency information coding and compression module; A reconfigurable feature decoding representation module is used to perform a second decoding representation on the feature vector to obtain a second decoding vector, wherein the structure of the reconfigurable feature decoding representation module is relatively dual to the structure of the reconfigurable information coding compression module; An output module is used to fuse the first decoding vector with the second decoding vector to obtain a target calculation result.

2. The system according to claim 1, characterized in that The energy-efficient information coding and compression module and the reconfigurable information coding and compression module are deployed on a wafer.

3. The system according to claim 1, characterized in that The general feature calculation module performs general feature calculation on the first coding vector and the second coding vector through a fully reconfigurable arbitrary matrix calculation unit of an MZI or cross-bar structure to obtain a feature vector.

4. The system according to claim 1, characterized in that The system also includes an auxiliary module for assisting the wafer-level intelligent optical computing chip system to complete large-scale, high-parameter complex intelligent computing tasks.

5. The system according to claim 4, characterized in that The auxiliary module includes a high-speed interface array module, a high-speed modulation module, a loading module and a data routing and monitoring module, wherein: The high-speed interface array module is used for data coupling and reading; The high-speed modulation module is used for high-speed modulation of calculation information; The loading module is used for loading the electric control signal; The data routing and monitoring module is used for data routing and monitoring.

6. The system according to claim 1, characterized in that The system comprises an array of configurable high energy efficiency information coding compression modules, wherein each diffraction coding device in the array has mutually orthogonal weight distributions and their characteristics are independent of each other.

7. The system according to claim 1, characterized in that The output module performs weighted fusion on the first decoding vector and the second decoding vector to obtain a target calculation result.

8. A computing method using the wafer-level intelligent optical computing chip system as claimed in claim 1, characterized in that: include: Obtaining an input matrix to be calculated, and performing multi-channel information channel coding compression on the input matrix to obtain a first coding vector; The input matrix is ​​subjected to multi-path information reconfigurable calculation weights to obtain a second encoding vector; Performing common feature calculation on the first encoding vector and the second encoding vector to obtain a feature vector; Performing a first decoding representation on the feature vector to obtain a first decoding vector; Performing a second decoding representation on the feature vector to obtain a second decoding vector; The first decoding vector and the second decoding vector are merged to obtain a target calculation result.

9. An electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method of claim 8.

10. A computer storage medium, wherein: The computer storage medium stores computer executable instructions; after the computer executable instructions are executed by the processor, the method according to claim 8 can be implemented.

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