Chip clock synchronization system and electronic equipment
By introducing an on-chip clock subsystem and a global time base counting subsystem inside the chip, and using PPS signals to correct time synchronization, the problem of low time synchronization accuracy of the internal subsystem in the chip is solved, and higher synchronization accuracy and flexibility are achieved.
Patent Information
- Application Number
- CN202411690393.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-22
- Publication Date
- 2025-04-25
AI Technical Summary
In the prior art, the time synchronization accuracy of different subsystems inside the chip is low, which affects the accuracy of data fusion of multiple subsystems.
The on-chip clock subsystem outputs the second pulse PPS signal, and the global time base counting subsystem is used to forward the PPS signal to each subsystem to realize the synchronous correction of system time.
It improves the time synchronization accuracy and flexibility of different subsystems inside the chip, reduces the number of peripherals used, and reduces the system complexity and cost.
Smart Images
Figure CN119882934A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of chip technology, and in particular to a chip clock synchronization system and electronic equipment. Background Art
[0002] The Advanced Driving Assistance System (ADAS) uses various types of subsystems installed on the vehicle (such as lidar, millimeter-wave radar, cameras, satellite positioning devices, etc.) to collect surrounding environment data in real time during vehicle driving, identify, detect and track dynamic and static objects, and perform systematic calculations and analysis in combination with navigation map data, so that the driver can be aware of possible dangers in the shortest time possible, thereby improving driving safety.
[0003] After collecting the corresponding data information, different types of subsystems will record the timestamp information of the collection time, and then the processing unit will integrate it according to the timestamp information to restore the vehicle's surrounding environment data. Therefore, maintaining a high degree of time consistency between subsystems is a necessary condition for multi-subsystem data fusion.
[0004] In the prior art, the accuracy of time synchronization between different subsystems within a chip is low. Summary of the invention
[0005] The purpose of the present invention is at least to provide a chip clock synchronization system, in which different subsystems inside the chip synchronize system time with the on-chip clock subsystem respectively, reducing the number of peripherals required to achieve time synchronization and improving the accuracy of time synchronization of different subsystems.
[0006] In a first aspect, the present invention provides a chip clock synchronization system, comprising: an on-chip clock subsystem and a global time base counting subsystem, suitable for performing clock synchronization on multiple subsystems in the chip, wherein the multiple subsystems include at least one of the following: a first-category subsystem and other-category subsystems; wherein: the on-chip clock subsystem is suitable for sending a second pulse PPS signal to the global time base counting subsystem, and outputting the start time of the PPS signal to the multiple subsystems; the global time base counting subsystem is suitable for forwarding the PPS signal to the first-category subsystem; and / or, obtaining a first time when the PPS signal is received, and providing a second time for the other-category subsystem to perform synchronous correction of the system time; the first-category subsystem and the other-category subsystem both use the PPS signal as a synchronization trigger source, and: the first-category subsystem is suitable for synchronously correcting its own system time based on the start time of the PPS signal and the first local time when the PPS signal is received; the other-category subsystem is suitable for synchronously correcting its own system time based on the start time, the first time and the second time; the first-category subsystem has the ability to receive the PPS signal.
[0007] The PPS signal is output through the on-chip clock subsystem, and each subsystem in the chip uses the PPS signal as a synchronization trigger source. The PPS signal is forwarded to the first type of subsystem through the global time base counting subsystem. The first subsystem synchronizes and corrects its own system time based on the start time of the PPS signal and the first local time when the PPS signal is received. Alternatively, the first time and the second time are provided by the global time base counting subsystem, so that other subsystems synchronize and correct their own system time. In this way, different subsystems synchronize the system time with the on-chip clock subsystem respectively, which can improve the accuracy and flexibility of the clock synchronization inside the chip.
[0008] Optionally, the global time base counting subsystem includes at least one of the following: a gate module, a local latch module, and a global time base counting module, wherein: the gate module is suitable for receiving the PPS signal and forwarding the PPS signal to the first type of subsystem; the local latch module is suitable for latching a first count value, and the first count value represents the first time; the first count value is: the count value of the global time base counting module when the global time base counting subsystem receives the PPS signal; the global time base counting module is suitable for counting based on a preset frequency.
[0009] Optionally, the first type of subsystem includes: a second pulse receiving module, a first inter-core communication module and a first time correction module, wherein: the second pulse receiving module is suitable for receiving a second pulse PPS signal sent by the on-chip clock subsystem, and latching the first local time when the PPS signal is received; the first inter-core communication module is coupled to the on-chip clock subsystem, and is suitable for receiving a first notification message sent by the on-chip clock subsystem, and the first notification message includes the start time; the first time correction module is suitable for synchronizing and correcting its own system time through a first time correction amount; the first time correction amount is associated with the first local time and the start time.
[0010] Optionally, the first time correction amount is also associated with a first error; the first error includes: a first PPS signal transmission delay and a first PPS signal reception delay; wherein, the first PPS signal transmission delay is: the transmission time of the PPS signal from the on-chip clock subsystem to the first type of subsystem; the first PPS signal reception delay is: the time required from the time when the second pulse receiving module receives the PPS signal to the time when the second pulse receiving module captures the first local time.
[0011] Optionally, the first time correction module is suitable for correcting its own system time using the first time correction amount when the first time correction amount is greater than a preset time threshold; and / or, when the first time correction amount is not greater than the time threshold, using a fixed time step to perform successive approximation correction on the system time of the first type of subsystem.
[0012] Optionally, the other type of system includes a second type of subsystem; the second type of subsystem includes: a second inter-core communication module, a local time base counting module and a second time correction module, wherein: the second inter-core communication module is coupled to the on-chip clock subsystem, and is suitable for receiving a second notification message sent by the on-chip clock subsystem, and the second notification message includes the start time and the first time; the local time base counting module is coupled to the global time base counting module, and the count value of the local time base counting module is equal to the count value of the global time base counting module; the second time correction module is suitable for synchronously correcting its own system time through a second time correction amount; the second time correction amount is associated with the start time, the first time and the second time; the second time is represented by the second count value of the local time base counting module, and the second count value is: the count value of the local time base counting module when performing synchronous correction of the system time.
[0013] Optionally, the second time correction amount is also associated with a second error; the second error includes: a second PPS signal transmission delay, a second PPS signal reception delay and a first reading delay, wherein: the second PPS signal transmission delay is: the transmission time of the PPS signal from the on-chip clock subsystem to the global time base counting module; the second PPS signal reception delay is: the time required from the time the global time base counting subsystem receives the PPS signal to latching the first time; the first reading delay is: the time required to read the second count value from the local time base counting module.
[0014] Optionally, the global time base counting subsystem also includes: an encoding module, suitable for encoding the count value output by the global time base counting module and outputting the encoding result; the second type of subsystem also includes: a decoding module, suitable for decoding the encoding result to obtain the count value of the global time base counting module.
[0015] Optionally, the other types of subsystems include a third type of subsystem; the third type of subsystem includes: a third inter-core communication module, a fourth inter-core communication module and a third time correction module, wherein: the third inter-core communication module is coupled to the on-chip clock subsystem, and is suitable for receiving a second notification message sent by the on-chip clock subsystem, the second notification message including the start time and the first time; the fourth inter-core communication module is coupled to the global time base counting module; the third time correction module is suitable for synchronously correcting its own system time through a third time correction amount; the third time correction amount is associated with the start time, the first time and the second time; the second time is determined by the third count value of the global time base counting module; the third count value is: the count value obtained from the global time base counting module through the fourth inter-core communication module when performing synchronous correction of the system time.
[0016] Optionally, the third time correction amount is also associated with a third error; the third error includes: a second PPS signal transmission delay, a second PPS signal reception delay and a second read delay, wherein: the second PPS signal transmission delay is: the transmission time of the PPS signal from the on-chip clock subsystem to the global time base counting module; the second PPS signal reception delay is: the time required from the time the global time base counting subsystem receives the PPS signal to latching the first time; the second read delay is: the time required to read the third count value from the global time base counting module.
[0017] In a second aspect, the present invention further provides an electronic device comprising any one of the chip clock synchronization systems described above. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Figure 1 is a schematic structural diagram of a chip in an embodiment of the present invention;
[0019] Figure 2 is a schematic structural diagram of an on-chip clock subsystem in an embodiment of the present invention;
[0020] Figure 3 is a schematic structural diagram of a global time base counting subsystem in an embodiment of the present invention;
[0021] Figure 4 is a schematic diagram of a first-type subsystem synchronization process in an embodiment of the present invention;
[0022] Figure 5 is a schematic diagram of a second type of subsystem synchronization process in an embodiment of the present invention;
[0023] Figure 6 It is a schematic diagram of a third type of subsystem synchronization process in an embodiment of the present invention. DETAILED DESCRIPTION
[0024] In the prior art, different subsystems in a chip need to obtain external Coordinated Universal Time (UTC). One synchronization implementation method is to synchronize different subsystems with corresponding external clock sources. Since it is necessary to set an external clock source corresponding to each subsystem, this implementation method greatly increases the complexity and cost of the chip, and has high requirements for the chip.
[0025] Another way to achieve synchronization is to synchronize a subsystem (such as subsystem A) with an external clock source, so that subsystem A obtains the world standard time. Other subsystems in the chip obtain the world standard time from subsystem A through inter-core communication, thereby achieving time synchronization of different subsystems in the chip. However, when different subsystems communicate with subsystem A, there may be different transmission delays, which leads to poor accuracy of time synchronization in the chip.
[0026] In an embodiment of the present invention, a PPS signal is outputted through an on-chip clock subsystem, and each subsystem in the chip uses the PPS signal as a synchronization trigger source. The PPS signal is forwarded to the first type of subsystem through a global time base counting subsystem. The first subsystem performs synchronization correction on its own system time based on the start time of the PPS signal and the first local time when the PPS signal is received. Alternatively, the first time and the second time are provided by the global time base counting subsystem, so that other subsystems perform synchronization correction on their own system time. Thus, different subsystems synchronize their system time with the on-chip clock subsystem respectively, which can improve the accuracy and flexibility of clock synchronization within the chip.
[0027] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0028] The embodiment of the present invention provides a chip, referring to Figure 1 .
[0029] In the embodiment of the present invention, the chip may include a chip clock synchronization system and multiple subsystems. The chip clock synchronization system may include an on-chip clock subsystem 11 and a global time base counting subsystem 12 .
[0030] In a specific implementation, the multiple subsystems may include a first type of subsystem 13 and other types of subsystems 14, wherein:
[0031] The on-chip clock subsystem 11 can generate a PPS signal, send the PPS signal to the global time base counting subsystem 12, and output the start time of the PPS signal to multiple subsystems;
[0032] The global time base counting subsystem 12 may forward the PPS signal to the first type subsystem 13; and / or obtain the first time when the PPS signal is received, and provide the second time for the other type subsystem 14 to perform synchronous correction of the system time;
[0033] The first type of subsystem 13 and other types of subsystems 14 can use the PPS signal as a synchronization trigger source;
[0034] The first type of subsystem 13 has the ability to directly receive the PPS signal; the first type of subsystem 13 can synchronize and correct its own system time based on the start time of the received PPS signal and the first local time when the PPS signal is received;
[0035] For other types of subsystems 14, their own system time can be corrected based on the start time, the first time and the second time of the PPS signal.
[0036] In a specific implementation, the above-mentioned multiple subsystems may refer to subsystems within the chip that are responsible for different functions, for example, a subsystem responsible for camera image acquisition, a subsystem responsible for millimeter-wave radar signal acquisition, a subsystem responsible for data fusion operations, a subsystem responsible for satellite positioning, etc.
[0037] Reference Figure 2 , a schematic diagram of the structure of an on-chip clock subsystem in an embodiment of the present invention is given.
[0038] In a specific implementation, the on-chip clock subsystem 11 may include: a time synchronization module 111, an inter-core communication module 112, and a PPS signal generation and transmission module 113, wherein:
[0039] The time synchronization module 111 communicates with the PPS signal generation and transmission module 113 and the inter-core communication module 112 to set the start time of the PPS signal, the pulse width of the PPS signal, the period and other parameters, and output the start time of the PPS signal to the inter-core communication module 112; or, obtains the first time, and outputs the start time of the PPS signal and the first time to the inter-core communication module 112;
[0040] The inter-core communication module 112 can be connected to the inter-core communication modules of multiple subsystems in the chip to realize inter-core communication with multiple subsystems; the inter-core communication module 112 can send the start time of the PPS signal to the first type of subsystem, or the inter-core communication module 112 can send the start time of the PPS signal and the first time to other types of subsystems;
[0041] The PPS signal generating and sending module 113 may be used to generate a PPS signal and output the generated PPS signal to the global time base counting subsystem 12 .
[0042] In a specific implementation, the on-chip clock subsystem 11 can also synchronize time with an external clock source. Specifically, the on-chip clock subsystem 11 can synchronize time with an external clock source through global satellite navigation system (GNSS) timing synchronization, network time protocol (NTP) synchronization, precision time protocol (PTP) synchronization, etc.
[0043] Reference Figure 3 , a schematic diagram of the structure of a global time base counting subsystem in an embodiment of the present invention is given.
[0044] In the embodiment of the present invention, the global time base counting subsystem 12 may include: a gate module 121, a local latch module 122 and a global time base counting module 123, wherein:
[0045] The gate module 121 can receive the PPS signal and forward the received PPS signal to the first type subsystem 13; the gate module 121 can also forward the PPS signal to the local latch module 122; the gate module 121 can include multiple output terminals, each of which can be coupled to a first type subsystem 13;
[0046] The local latch module 122 can latch a first count value, and the first count value can represent a first time; the first count value can be: the count value of the global time base counting module 123 when the global time base counting subsystem 12 receives the PPS signal;
[0047] The global time base counting module 123 can count based on a preset frequency.
[0048] In a specific implementation, when the global time base counting subsystem 12 receives the PPS signal, the global time base counting subsystem 12 can latch the count value of the global time base counting module 123 into the local latch module 122. In this scenario, the count value in the local latch module 122 is the first count value used to represent the first time.
[0049] In a specific implementation, the time synchronization module 111 of the on-chip clock subsystem 11 may read the first count value stored in the local latch module 122 to obtain the first time.
[0050] In the embodiment of the present invention, the number of the first type subsystem 13 may be one or more. Different first type subsystems 13 may be connected to the same on-chip clock subsystem, or to different on-chip clock subsystems.
[0051] For example, the first type of subsystem 13 includes subsystem A and subsystem B, and the PPS signal output by the on-chip clock subsystem G is the synchronization trigger source of subsystem A and subsystem B.
[0052] For another example, the first type of subsystem includes subsystem A and subsystem B, the on-chip clock subsystem G outputs a PPS signal to subsystem A, and the on-chip clock subsystem F outputs a PPS signal to subsystem B. Subsystem A uses the PPS signal output by the on-chip clock subsystem G as a synchronization trigger source, and subsystem B uses the PPS signal output by the on-chip clock subsystem F as a synchronization trigger source, and the frequency of the PPS signal output by the on-chip clock subsystem G is equal to that of the PPS signal output by the on-chip clock subsystem F.
[0053] In some embodiments, the frequencies of the PPS signals output by different on-chip clock subsystems may be different. For example, in the above example, the frequencies of the PPS signals output by on-chip clock subsystem G and the PPS signals output by on-chip clock subsystem F are different.
[0054] Reference Figure 4 , a schematic diagram of a first-type subsystem synchronization process in an embodiment of the present invention is given. Since the global time base counting module 123 and the local latch module 122 are not used in the process of synchronizing the first-type subsystem, Figure 4 The global time base counting module 123 and the local latch module 122 are not shown.
[0055] In the embodiment of the present invention, the first type of subsystem 13 may include: a second pulse receiving module 131, a first inter-core communication module 132 and a first time correction module 133, wherein:
[0056] The pulse per second receiving module 131 can receive the PPS signal forwarded by the gate module 121, and latch the local time when receiving the PPS signal. The latched local time is the first local time when the PPS signal is received. The latched local time can also be understood as the latched system time.
[0057] A first inter-core communication module 132 is coupled to the inter-core communication module 112 of the on-chip clock subsystem and is adapted to receive first notification information sent by the on-chip clock subsystem, where the first notification information includes a start time of a PPS signal;
[0058] The first time correction module 133 can synchronously correct its own system time through a first time correction value; the first time correction value is associated with the first local time and the start time of the PPS signal.
[0059] The synchronization process of the first type of subsystem is described below.
[0060] The on-chip clock subsystem 11 generates and sends a PPS signal through the PPS signal generation and transmission module 113. The PPS signal passes through the gate module 121 and is output to the pulse per second receiving module 131 of the first type subsystem 13. After sending the PPS signal, the PPS signal generation and transmission module 113 can notify the time synchronization module 111. The time synchronization module 111 can send the start time of the PPS signal to the first type subsystem 13 through the inter-core communication module 112.
[0061] When receiving the PPS signal, the pulse per second receiving module 131 of the first type subsystem 13 may capture the first local time when the PPS signal is received.
[0062] The first time correction module 133 of the first type of subsystem 13 receives the first notification information through the first inter-core communication module 132, and then learns the start time of the PPS signal. The first time correction module 133 can determine the first time correction value based on the first local time and the start time of the PPS signal. Then, the first time correction module 133 performs synchronization correction on its own system time based on the first time correction value, thereby achieving time synchronization with the on-chip clock subsystem 11.
[0063] In a specific implementation, the first time correction amount can be determined by the following formula: Offset=TPT-LPT, wherein TPT is the start time of the PPS signal, and LPT is the first local time.
[0064] In some embodiments, there is a certain transmission delay when the PPS signal is transmitted from the on-chip clock subsystem 11 to the first type of subsystem 13. There is also a certain reception delay from the detection of the PPS signal to the capture of the first local time (that is, the acquisition of the first count value) by the second pulse receiving module 131. The above transmission delay and reception delay will affect the first time correction amount.
[0065] In order to improve the accuracy of time synchronization, a first error may be introduced into the first time correction. The first error is the sum of the first PPS signal transmission delay and the first PPS signal reception delay. The first PPS signal transmission delay may refer to: the transmission time required for the PPS signal to be transmitted from the on-chip clock subsystem 11 to the first type of subsystem 13; the first PPS signal reception delay may refer to: the time required from the second pulse receiving module 131 receiving the PPS signal to capturing the first local time.
[0066] After the first error is introduced, the first time correction amount can be determined as: Offset=TPT-LPT+first error.
[0067] In a specific implementation, the first PPS signal transmission delay and the first PPS signal reception delay can be known in advance. When calculating the first time correction, the first PPS signal transmission delay and the first PPS signal reception delay can be directly called to obtain the first error.
[0068] In a specific implementation, for the first type of subsystem 13, if the first time correction amount obtained is large, it means that the time offset of the system time of the first type of subsystem 13 is large, and time synchronization needs to be achieved as soon as possible. In this scenario, the first time correction module 133 can directly correct the system time based on the first time correction amount. Thus, time synchronization can be achieved quickly. However, since the system time is corrected directly based on the first time correction amount, the system time may jump.
[0069] If the first time correction obtained is small, it means that the time offset of the system time of the first subsystem 13 is small. To avoid the system time jump of the first subsystem 13, the system time of the on-chip clock subsystem 11 can be gradually approached by adjusting the stepping method.
[0070] For example, within a synchronization cycle, the system time of the first type subsystem 13 is adjusted in steps of a fixed duration, so that the system time of the first type subsystem 13 gradually approaches the system time of the on-chip clock subsystem 11 .
[0071] In the embodiment of the present invention, the other subsystem 14 may include a second subsystem 141. The second subsystem 141 may be a subsystem that supports external count value input. In some embodiments, the second subsystem 141 may not support PPS signal reception.
[0072] Reference Figure 5 , a schematic diagram of a second type of subsystem synchronization process in an embodiment of the present invention is given.
[0073] In a specific implementation, the second type of subsystem 141 may include: a local time base counting module 1411, a second inter-core communication module 1412, and a second time correction module 1413, wherein:
[0074] The second inter-core communication module 1412 may be coupled to the on-chip clock subsystem 11 to receive second notification information sent by the on-chip clock subsystem 11, where the second notification information may include the start time of the PPS signal and the first time;
[0075] The local time base counting module 1411 may be coupled to the global time base counting module 123; the count value of the local time base counting module 1411 is equal to the count value of the global time base counting module 123;
[0076] The second time correction module 1413 can determine a second time correction amount, and perform synchronization correction on its own system time based on the second time correction amount.
[0077] Specifically, the second inter-core communication module 1412 may perform inter-core communication with the inter-core communication module 112 of the on-chip clock subsystem 11 to receive the second notification information sent by the on-chip clock subsystem 11 .
[0078] In a specific implementation, the global time base counting subsystem may further include an encoding module, suitable for encoding the count value output by the global time base counting module; accordingly, the second type of subsystem may further include a decoding module, suitable for decoding the encoded count value to obtain the count value output by the global time base counting module.
[0079] By setting an encoding module in the global time base counting subsystem and encoding the count value output by the global time base counting module, errors can be avoided when transmitting across asynchronous systems (i.e., the global time base counting subsystem and the second type of subsystem have different clock sources and frequencies).
[0080] The synchronization process of the second type of subsystem 141 is described below.
[0081] The on-chip clock subsystem 11 sets the start time of the PPS signal, the pulse width of the PPS signal, the period and other parameters through the time synchronization module 111, and outputs the start time of the PPS signal to the inter-core communication module 112. The PPS signal generation and transmission module 113 generates and transmits the corresponding PPS signal based on the parameters configured by the time synchronization module 111. After transmitting the PPS signal, the PPS signal generation and transmission module 113 can notify the time synchronization module 111 that the PPS signal has been transmitted.
[0082] After receiving the PPS signal, the global time base counting subsystem 12 latches the first count value of the global time base counting module 123 when the PPS signal is received, and the first count value represents the first time. The first count value is latched in the local latch module 122. After latching the first count value, the local latch module 122 can communicate with the time synchronization module 111 of the on-chip clock subsystem 11 to notify the time synchronization module 111 to obtain the first count value.
[0083] The time synchronization module 111 reads the latched first count value from the local latch module 122 to obtain the first time. The time synchronization module 111 sends the second notification information to the second inter-core communication module 1412 of the second type subsystem 141 through the inter-core communication module 112, and the second notification information includes: the first time (represented by the first count value GLC) and the start time TPT of the PPS signal.
[0084] The second time correction module 1413 calculates the second time correction value based on the first time, the start time of the PPS signal, and the second time of performing the synchronous correction of the system time. After obtaining the second time correction value, the system time itself is synchronously corrected, thereby achieving time synchronization with the on-chip clock subsystem 11. The second time can be represented by the second count value of the local time base counting module 1411, and the second count value can be: the count value of the local time base counting module 1411 when performing the synchronous correction of the system time.
[0085] In the embodiment of the present invention, the second time is the count value of the local time base counting module 1411 when the second time correction module 1413 starts to synchronize and correct the system time. In other words, the second time is after the second time correction module 1413 receives the second notification message.
[0086] The second time correction module 1413 may run a corresponding software program to perform synchronization correction of the system time through the software program. Therefore, the second time mentioned above may also be understood as the count value of the local time base counting module 1411 when the software program starts to perform synchronization correction on the system time.
[0087] Specifically, the second time correction amount may be:
[0088] Offset=TPT+(Current Local Counter Value-GLC) / GTC frequency;
[0089] Among them, TPT is the start time of the PPS signal; Current Local Counter Value is the second count value, that is, the count value of the local time base counting module 1411 when synchronizing and correcting the system time, which is used to represent the second time; GLC is the first count value of the global time base counting module 123, which is used to represent the first time; GTC frequency is the frequency of the global time base counting module 123.
[0090] In a specific implementation, the second time correction amount can also be corrected by a second error. The second error can be composed of the following parts: a second PPS signal transmission delay, a second PPS signal reception delay, and a first reading delay; wherein the second PPS signal transmission delay is: the transmission time of the PPS signal from the on-chip clock subsystem 11 to the global time base counting subsystem 12; the second PPS signal reception delay is: the time required from the global time base counting subsystem 12 receiving the PPS signal to capturing the first count value (latching the first time); the first reading delay is: the time required to read the second count value from the local time base counting module 1411.
[0091] Therefore, the second time correction value can be updated as follows:
[0092] Offset=TPT+(Current Local Counter Value-GLC) / GTC frequency+second error.
[0093] After obtaining the updated second time correction value, time synchronization can be performed based on the updated second time correction value.
[0094] In the embodiment of the present invention, the other subsystems 14 may further include a third subsystem. The third subsystem may be a subsystem that does not support PPS signal reception and does not support external count value input.
[0095] Reference Figure 6 , a schematic diagram of a third-type subsystem synchronization process in an embodiment of the present invention is given.
[0096] In a specific implementation, the third subsystem 142 may include: a third inter-core communication module 1422, a fourth inter-core communication module 1421, and a third time correction module 1423, wherein:
[0097] The third inter-core communication module 1422 is coupled to the on-chip clock subsystem 11 and is adapted to receive second notification information sent by the on-chip clock subsystem 11, where the second notification information includes the start time of the PPS signal and the first time;
[0098] The fourth inter-core communication module 1421 is coupled to the global time base counting module 123; the third time correction module 1423 is adapted to obtain the third count value of the global time base counting module 123 through the fourth inter-core communication module, and determine the second time based on the third count value;
[0099] The third time correction module 1423 is adapted to synchronously correct its own system time through a third time correction value; the third time correction value may be associated with the start time of the PPS signal, the first time and the second time.
[0100] The synchronization process of the third type of subsystem 142 is described below.
[0101] The on-chip clock subsystem 11 generates and sends a PPS signal through the PPS signal generation and transmission module 113. After sending the PPS signal, the PPS signal generation and transmission module 113 may notify the time synchronization module 111 that the PPS signal has been sent.
[0102] After receiving the PPS signal, the global time base counting subsystem 12 latches the first count value of the global time base counting module 123 when the PPS signal is received, and the first count value represents the first time. The first count value is latched in the local latch module 122. After latching the first count value, the local latch module 122 can communicate with the time synchronization module 111 of the on-chip clock subsystem 11 to notify the time synchronization module 111 to obtain the first count value.
[0103] The time synchronization module 111 reads the latched first count value from the local latch module 122 to obtain the first time. The time synchronization module 111 sends the second notification information to the third inter-core communication module 1422 of the third type subsystem 142 through the inter-core communication module 112, and the second notification information includes: the first time (represented by the first count value GLC) and the start time TPT of the PPS signal.
[0104] The third time correction module 1423 calculates a third time correction value based on the first time, the start time of the PPS signal, and the second time for synchronously correcting the system time. The second time can be represented by a third count value, which can be: the count value of the global time base counting module 123 when synchronously correcting the system time.
[0105] In the embodiment of the present invention, a corresponding software program may be run in the third time correction module 1423, and the system time may be synchronously corrected by the software program. Therefore, the second time mentioned above may also be understood as the count value of the global time base counting module 123 when the software program starts to synchronously correct the system time.
[0106] Specifically, the third time correction value may be:
[0107] Offset=TPT+(Current GTC Counter Value-GLC) / GTC frequency;
[0108] Among them, TPT is the start time of the PPS signal; Current GTC Counter Value is the third count value, that is, the count value of the global time base counting module 123 when synchronously correcting the system time, which is used to represent the second time; GLC is the first count value of the global time base counting module 123, which is used to represent the first time; GTC frequency is the frequency of the global time base counting module 123.
[0109] In a specific implementation, the third time correction amount can also be corrected by a third error. The third error can be composed of the following parts: a second PPS signal transmission delay, a second PPS signal reception delay, and a second reading delay; wherein the second PPS signal transmission delay is: the transmission time of the PPS signal from the on-chip clock subsystem 11 to the global time base counting subsystem 12; the second PPS signal reception delay is: the time required from the global time base counting subsystem 12 receiving the PPS signal to capturing the first count value (latching the first time); the second reading delay is: the time required to read the third count value from the global time base counting module 123.
[0110] Therefore, the third time correction value can be updated as follows:
[0111] Offset=TPT+(Current GTC Counter Value-GLC) / GTC frequency+third error.
[0112] After obtaining the updated third time correction value, time synchronization may be performed based on the updated third time correction value.
[0113] In the embodiment of the present invention, for the above-mentioned first type subsystem, second type subsystem and third type subsystem, the synchronization accuracy of the first type subsystem is the highest, the synchronization accuracy of the second type subsystem is the second, and the synchronization accuracy of the third type subsystem is the worst.
[0114] The synchronization error of the first type of subsystem mainly comes from the hardware transmission delay inside the chip, such as the time required for the PPS signal to be transmitted from the on-chip clock subsystem to the first type of subsystem. The hardware transmission delay can be compensated by introducing the first error.
[0115] The synchronization error of the second type of subsystem mainly comes from the hardware transmission delay inside the chip (such as the time required for the PPS signal to be transmitted from the on-chip clock subsystem to the global time base counting subsystem) and the delay in reading the second count value in the local time base counting module. The hardware transmission delay and reading delay can be compensated by introducing the second error.
[0116] The synchronization error of the third type of subsystem mainly comes from the hardware transmission delay inside the chip (such as the time required for the PPS signal to be transmitted from the on-chip clock subsystem to the global time base counting subsystem) and the delay in reading the second count value in the global time base counting module. The hardware transmission delay and the reading delay can be compensated by introducing the third error. Since the second count value is read across subsystems (the third type of subsystem reads the second count value from the global time base counting subsystem), the corresponding delay is larger than that of the second type of subsystem.
[0117] In some application scenarios, the synchronization accuracy of the first type of subsystem can reach tens of nanoseconds, the synchronization accuracy of the second type of subsystem can reach hundreds of nanoseconds, and the synchronization accuracy of the third type of subsystem can reach hundreds of microseconds.
[0118] In summary, the chip clock synchronization system provided in the embodiment of the present application can achieve time synchronization for subsystems of different types and capabilities through the internal clock subsystem and the global time base counting subsystem. In addition, subsystems of different types and capabilities adopt the time synchronization scheme provided in the above embodiment to reduce synchronization errors, improve synchronization accuracy, and reduce the inter-core communication load.
[0119] An embodiment of the present invention further provides an electronic device, comprising the chip clock synchronization system provided by any of the above embodiments.
[0120] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A chip clock synchronization system, characterized in that: include: The on-chip clock subsystem and the global time base counting subsystem are suitable for clock synchronization of multiple subsystems in the chip, wherein the multiple subsystems include at least one of the following: a first type of subsystem, and other types of subsystems; wherein: The on-chip clock subsystem is adapted to send a pulse per second (PPS) signal to the global time base counting subsystem, and output the start time of the PPS signal to the multiple subsystems; The global time base counting subsystem is adapted to forward the PPS signal to the first type of subsystem; and / or obtain a first time when the PPS signal is received, and provide a second time for the other types of subsystems to perform synchronous correction of system time; The first type of subsystem and the other types of subsystems all use the PPS signal as a synchronization trigger source, and: The first type of subsystem is adapted to synchronously correct its own system time based on the start time of the PPS signal and the first local time when the PPS signal is received; The other type of subsystem is suitable for synchronously correcting its own system time based on the start time, the first time and the second time; the first type of subsystem has the ability to receive the PPS signal.
2. The chip clock synchronization system according to claim 1, characterized in that: The global time base counting subsystem includes at least one of the following: a gate module, a local latch module, and a global time base counting module, wherein: The gate module is adapted to receive the PPS signal and forward the PPS signal to the first type of subsystem; The local latch module is adapted to latch a first count value, wherein the first count value represents the first time; the first count value is: a count value of the global time base counting module when the global time base counting subsystem receives the PPS signal; The global time base counting module is suitable for counting based on a preset frequency.
3. The chip clock synchronization system according to claim 1 or 2, characterized in that: The first type of subsystem includes: a second pulse receiving module, a first inter-core communication module and a first time correction module, wherein: The pulse-per-second receiving module is adapted to receive a pulse-per-second PPS signal sent by the on-chip clock subsystem, and latch the first local time when the PPS signal is received; The first inter-core communication module is coupled to the on-chip clock subsystem and is adapted to receive first notification information sent by the on-chip clock subsystem, wherein the first notification information includes the start time; The first time correction module is suitable for synchronously correcting the system time of the module by using a first time correction value; the first time correction value is associated with the first local time and the start time.
4. The chip clock synchronization system according to claim 3, characterized in that: The first time correction is also associated with a first error; the first error includes: a first PPS signal transmission delay and a first PPS signal reception delay; wherein, The first PPS signal transmission delay is: the transmission time of the PPS signal from the on-chip clock subsystem to the first type of subsystem; The first PPS signal receiving delay is: the time required from the second pulse receiving module receiving the PPS signal to the second pulse receiving module capturing the first local time.
5. The chip clock synchronization system according to claim 3 or 4, characterized in that: The first time correction module is adapted to correct its own system time using the first time correction amount when the first time correction amount is greater than a preset time threshold; and / or, When the first time correction amount is not greater than the time threshold, the system time of the first type of subsystem is corrected in successive approximations with fixed time steps.
6. The chip clock synchronization system according to claim 2, characterized in that: The other type of system includes a second type of subsystem; the second type of subsystem includes: a second inter-core communication module, a local time base counting module and a second time correction module, wherein: The second inter-core communication module is coupled to the on-chip clock subsystem and is adapted to receive second notification information sent by the on-chip clock subsystem, wherein the second notification information includes the start time and the first time; The local time base counting module is coupled to the global time base counting module, and the count value of the local time base counting module is equal to the count value of the global time base counting module; The second time correction module is suitable for synchronously correcting its own system time through a second time correction amount; the second time correction amount is associated with the start time, the first time and the second time; the second time is represented by the second count value of the local time base counting module, and the second count value is: the count value of the local time base counting module when performing synchronous correction of the system time.
7. The chip clock synchronization system according to claim 6, characterized in that: The second time correction is also associated with a second error; the second error includes: a second PPS signal transmission delay, a second PPS signal reception delay and a first reading delay, wherein: The second PPS signal transmission delay is: the transmission time of the PPS signal from the on-chip clock subsystem to the global time base counting module; The second PPS signal receiving delay is: the time required from the global time base counting subsystem receiving the PPS signal to latching the first time; The first reading delay is: the time required to read the second count value from the local time base counting module.
8. The chip clock synchronization system according to claim 6, characterized in that: The global time base counting subsystem further includes: an encoding module adapted to encode the count value output by the global time base counting module and output the encoding result; The second type of subsystem further includes: a decoding module, adapted to decode the encoding result to obtain the counting value of the global time base counting module.
9. The chip clock synchronization system according to claim 2, characterized in that: The other subsystems include a third subsystem; the third subsystem includes: a third inter-core communication module, a fourth inter-core communication module and a third time correction module, wherein: The third inter-core communication module is coupled to the on-chip clock subsystem and is adapted to receive second notification information sent by the on-chip clock subsystem, where the second notification information includes the start time and the first time; The fourth inter-core communication module is coupled to the global time base counting module; The third time correction module is suitable for synchronously correcting its own system time through a third time correction amount; the third time correction amount is associated with the start time, the first time and the second time; the second time is determined by the third count value of the global time base counting module; the third count value is: when performing synchronous correction of the system time, the count value obtained from the global time base counting module through the fourth inter-core communication module.
10. The chip clock synchronization system according to claim 9, characterized in that: The third time correction is also associated with a third error; the third error includes: a second PPS signal transmission delay, a second PPS signal reception delay and a second reading delay, wherein: The second PPS signal transmission delay is: the transmission time of the PPS signal from the on-chip clock subsystem to the global time base counting subsystem; The second PPS signal receiving delay is: the time required from the global time base counting subsystem receiving the PPS signal to latching the first time; The second read delay is: the time required to read the third count value from the global time base counting module.
11. An electronic device, characterized in that: It comprises the chip clock synchronization system as claimed in any one of claims 1 to 10.