Memristor-based approximate addition circuit control method and approximate addition operation device

Abstract

The present invention discloses a control method for an approximate adder circuit based on memristors and an approximate adder operation device, belonging to the technical field of microelectronic logic operations; in the approximate adder circuit, by inputting logical values to be subjected to majority gate logic operations to the first, second, and third memristors and regulating the voltage, the majority gate logic operation M(a, b, c) can be realized. By inputting logical values to be subjected to majority gate logic operations to the first, second, and fourth memristors and regulating the voltage, the majority gate logic operation can be realized. By iterating the two majority gate logic operations, the approximate addition operation can be realized. In the present invention, since two different majority gate logic operations can reuse the operation units, the integration degree of the device is relatively high and the calculation speed is relatively fast.

Description

Technical Field

[0001] The present invention belongs to the technical field of microelectronic logic operations, and more specifically, relates to a method for controlling an approximate adder circuit based on a memristor and an approximate adder operation device. Background Art

[0002] Addition operations can be implemented through Majority-Inverter Graph (MIG) logic. MIG consists of Majority (MAJ) and Inverter (INV) logics. The logical expression of a three-input majority decision gate is: M(a, b, c) = a·b + a·c + b·c, and the expression of the inverter logic is: , and addition operations can be implemented by iterating MAJ and inverter logics.

[0003] Since memristors have the advantages of low power consumption, small size, and compatibility with CMOS processes, they are ideal candidate devices for in-memory computing architectures. Therefore, memristors are usually used to implement majority gate logic operations. Existing implementation schemes for majority gate logic based on memristors operate on a, b, and c respectively through three memristor units, achieving the three-input majority gate logic M(a, b, c) = a·b + a·c + b·c. Although this can reduce hardware complexity, this logic scheme only supports single logical operations and lacks the implementation of inverter logic. In addition, addition operations implemented based on majority gate logic often involve not only the traditional majority gate logic M(a, b, c) = a·b + a·c + b·c, but also majority gate logic including inverter logic ; Since two different types of majority gate logics are involved simultaneously, if the existing majority gate logic based on memristors is used to implement addition operations, the required number of devices is large, the integration level is low, and the calculation speed is also low, which cannot meet the requirements for adders in practical applications with high integration and calculation speed.

[0004] Therefore, there is an urgent need to propose a new scheme to improve the integration level and calculation speed of addition operations. Summary of the Invention

[0005] Aiming at the above defects or improvement requirements of the prior art, the present invention provides a method for controlling an approximate adder circuit based on a memristor and an approximate adder operation device, so as to improve the integration level and calculation speed of the adder operation device.

[0006] To achieve the above object, in a first aspect, the present invention provides a method for controlling an approximate adder circuit based on a memristor. The majority gate circuit includes: a voltage comparator, a resistor, and three identical memristors; the negative electrodes of the three memristors are all connected to one end of the resistor; the other end of the resistor is grounded; the first input terminal of the voltage comparator is connected to the common node of the three memristors and the resistor; the resistance value of the resistor is the low-resistance state resistance value of the memristor.

[0007] The control method includes: performing n rounds of addition sub-processes; wherein, in the i-th round of addition sub-process, the following operations are performed:

[0008] Write the logic value a into the first memristor i , write the logic value b into the second memristor i , and write the carry c used in the i-th round of addition into the third memristor i ;

[0009] Select the first to third memristors to participate in the calculation: apply voltage V to the positive electrodes of the first to third memristors respectively 1 , connect the reference voltage V to the second input terminal of the voltage comparator Ref1 , and obtain the result M(a i , b i , c i ) = a i ·b i + a i ·c i + b i ·c i at the output terminal of the voltage comparator, as the carry c used in the (i + 1)-th round of addition i+1 ;

[0010] Write c into the fourth memristor i+1 ,

[0011] Select the first, second, and fourth memristors to participate in the calculation: apply voltage V to the positive electrodes of the first and second memristors respectively 2 , apply a voltage with an amplitude of 0 to the positive electrode of the fourth memristor, connect the reference voltage V to the second input terminal of the voltage comparator Ref2 , and obtain the result of the majority gate logic operation at the output terminal of the voltage comparator, as the sum result s in the i-th round of addition i ;

[0012] After completing the n-th round of addition, use c n+1 s n ......s 2 s 1 as a n ......a 2 a1 and b n ......b 2 b 1 The addition result with;

[0013] where i = 1, 2,..., n; 0 < V 1 < V set ; V 1 / 2 < V Ref1 < 2V 1 / 3; 0 < V 2 < V set ; V 2 / 3 < V Ref2 < V 2 / 2; V set is the threshold value for the memristor to transition from the high resistance state to the low resistance state; the high resistance state of the memristor corresponds to the logic value "0", and the low resistance state corresponds to the logic value "1". When the voltage at the first input terminal of the voltage comparator is greater than the voltage at the second input terminal, the output terminal outputs the first level, and the first level is used as the result "1" of the majority gate logic operation; otherwise, the output terminal outputs the second level, and the second level is used as the result "0" of the majority gate logic operation.

[0014] Optionally, the first input terminal is the positive terminal, the second input terminal is the negative terminal, the first level is the high level, and the second level is the low level.

[0015] In a second aspect, the present invention provides an approximate addition operation device based on a memristor, which includes: an approximate addition circuit and a controller;

[0016] The approximate addition circuit includes: a voltage comparator, a resistor, and a total of four identical memristors from the first to the fourth; the negative electrodes of the four memristors are all connected to one end of the resistor; the other end of the resistor is grounded; the first input terminal of the voltage comparator is connected to the common node of the four memristors and the resistor; the resistance value of the resistor is the low resistance state resistance value of the memristor;

[0017] The controller is used to execute the control method provided in the first aspect of the present invention.

[0018] Optionally, the resistance values of the low resistance state and the high resistance state of the memristor differ by at least two orders of magnitude.

[0019] In a third aspect, the present invention provides a control system, including: a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, it executes the control method provided in the first aspect of the present invention.

[0020] Fourthly, the present invention further provides a computer-readable storage medium, which includes a stored computer program. When the computer program is run by a processor, it controls the device where the storage medium is located to execute the control method provided in the first aspect of the present invention.

[0021] Fifthly, the invention further provides a computer program product, including a computer program / instructions. When the computer program / instructions are executed by a processor, the control method provided in the first aspect of the present invention is implemented.

[0022] Generally speaking, through the above technical solutions conceived by the present invention, the following beneficial effects can be achieved:

[0023] 1. The present invention combines two majority gate logics of M(a, b, c) and to realize approximate addition. Although the approximate adder sacrifices some precision, it can simplify the circuit structure, reduce power consumption, shorten the operation delay and reduce the chip area, and can greatly improve the integration and calculation speed of the addition operation, and has good application prospects in the fields of image processing, artificial intelligence and signal processing.

[0024] 2. The key to realizing the approximate addition operation in the present invention lies in the design of two majority gate logics of M(a, b, c) and . Among them, both of the two majority gate logics of M(a, b, c) and can be realized by controlling the same approximate addition circuit. The approximate addition circuit only needs to set four memristors, one resistor and one voltage comparator in total. By inputting the logical values to be subjected to the majority gate logic operation to the first, second and third memristors and regulating the voltage, the result of the majority gate logic operation is determined by the voltage comparator according to the comparison result of the common node voltage and the reference voltage, and thus the majority gate logic operation M(a, b, c) can be realized. By inputting the logical values to be subjected to the majority gate logic operation to the first, second and fourth memristors and regulating the voltage, the result of the majority gate logic operation is determined by the voltage comparator according to the comparison result of the common node voltage and the reference voltage, and thus the majority gate logic operation can be realized. By iterating the two majority gate logic operations, the approximate addition operation can be realized. In the present invention, since two different majority gate logic operations can reuse multiple operation units, the integration of the addition operation device is relatively high and the calculation speed is relatively fast.

[0025] 3. In the present invention, to realize the majority gate logic When performing the operation, it is possible to avoid decomposing it into two independent logic operations, namely the majority gate logic M(a, b, c) and the negation logic. It can be achieved by applying voltage in one step without increasing the number of memristors. The majority gate logic operation can be realized with fewer devices and faster computing speed. Based on this, the present invention can meet the requirements for approximate adders in practical applications with high integration and fast computing speed.

[0026] 4. In the present invention, after the logical calculation is completed, the states of the three input memristors still maintain the written input information values, which is non-destructive to the input information and has non-volatility at the same time, realizing a logic circuit with the resistance values of memristors as inputs and a non-destructive operation process. This circuit has strong data reusability and does not require additional copying operations to save data in practical applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 Schematic diagram of an approximate adder circuit provided by an embodiment of the present invention.

[0028] Figure 2 Schematic diagram of the gate-level representation for realizing addition operation based on majority gate logic provided by an embodiment of the present invention.

[0029] Figure 3 Schematic diagram of a majority gate circuit for realizing majority gate logic provided by an embodiment of the present invention.

[0030] Figure 4 Schematic diagram of the control of majority gate logic M(a, b, c) provided by an embodiment of the present invention.

[0031] Figure 5 Schematic diagram of the design concept of majority gate logic M(a, b, c) provided by an embodiment.

[0032] Figure 6 Equivalent circuit after writing logic values to the memristor provided by an embodiment.

[0033] Figure 7 Schematic diagram of the control of majority gate logic provided by an embodiment of the present invention of the present invention.

[0034] Figure 8 Schematic diagram of the design concept of majority gate logic provided by an embodiment of the present invention of the present invention.

[0035] Figure 9 Experimental result diagram for realizing 1-bit addition approximate operation using the addition operation method proposed by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0036] In order to make the objectives, technical solutions and advantages of the present invention more clear and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0037] In order to make the objectives, technical solutions and advantages of the present invention more clear and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0038] In a first aspect, the present invention provides a control method for an approximate adder circuit based on a memristor, which is used to implement the addition operation of n-bit numbers a n ......a 2 a 1 and b n ......b 2 b 1 .

[0039] As Figure 1 shown, the adder circuit includes: a voltage comparator, a resistor, and a total of four identical memristors from the first to the fourth; the negative electrodes of the four memristors are all connected to one end of the resistor; the other end of the resistor is grounded; the first input terminal of the voltage comparator is connected to the common node of the four memristors and the resistor; the resistance value of the resistor is the low-resistance state resistance value of the memristor; n≥1;

[0040] The control method includes: performing n rounds of addition sub-processes; wherein, in the i-th round of addition sub-process, the following operations are performed:

[0041] Select three memristors and denote them as the first memristor M a , the second memristor M b and the third memristor M c ; write the logic value a i into the first memristor, write the logic value b i into the second memristor, and write the carry c i of the i-th round of addition into the third memristor; wherein, logic "1" means setting the memristor resistance state to low resistance, and logic "0" means setting the memristor resistance state to high resistance. When i = 1, the carry c 1 is input by the user and can be logic "1" or logic "0".

[0042] Select the first to third memristors to participate in the calculation: Apply voltage V to the positive electrodes of the first memristor, the second memristor, and the third memristor respectively 1 , connect the reference voltage V to the second input terminal of the voltage comparator Ref1 , and obtain the result M(a i ,b i ,c i ) = a i ·b i + a i ·c i + b i ·c i at the output terminal of the voltage comparator, which is used as the carry for the (i + 1)-th round of addition ; In this process, the first memristor, the second memristor, the third memristor, the resistor, and the voltage comparator implement the majority gate logic operation M(a i ,b i ,c i ) = a i ·b i + a i ·c i + b i ·c i .

[0043] Denote the remaining unassigned memristor as the fourth memristor M d , and write M(a i ,b i ,c i ) into the fourth memristor, that is, write the carry ,

[0044] Select the first, second, and fourth memristors to participate in the calculation: Apply voltage V to the positive electrodes of the first memristor and the second memristor respectively 2 , apply a voltage with an amplitude of 0 to the positive electrode of the third memristor, connect the reference voltage V to the second input terminal of the voltage comparator Ref2 , and obtain the result of the majority gate logic operation at the output terminal of the voltage comparator, and denote it as s i ; In this process, the first memristor, the second memristor, the fourth memristor, the resistor, and the voltage comparator implement the majority gate logic operation .

[0045] After n rounds of addition sub-processes, s n ......s 2 s 1 and c n+1 are the desired n-bit numbers a n ......a 2a 1 and b n ......b 2 b 1 The addition result with;

[0046] where i = 1, 2,..., n; 0 < V 1 < V set ; V 1 / 2 < V Ref1 < 2V 1 / 3; 0 < V 2 < V set ; V 2 / 3 < V Ref2 < V 2 / 2; V set is the threshold value for the memristor to change from the high resistance state to the low resistance state; by setting the high and low resistance states of the memristor, the corresponding logic values are written. The high resistance state of the memristor corresponds to the logic value "0", and the low resistance state corresponds to the logic value "1"; when the voltage at the first input terminal of the voltage comparator is greater than the voltage at the second input terminal, the output terminal outputs the first level, and the first level is used as the result "1" of the majority gate logic operation; otherwise, the output terminal outputs the second level, and the second level is used as the result "0" of the majority gate logic operation.

[0047] Specifically, the first input terminal is the positive terminal, the second input terminal is the negative terminal, the first level is the high level, and the second level is the low level.

[0048] It can be understood that the correspondence between the output level of the voltage comparator and the logic value can be set flexibly. For example, with the first input terminal as the positive terminal, the second input terminal as the negative terminal, the first level as the high level, and the second level as the low level, the high level is used as the result "1" of the majority gate logic operation, and the low level is used as the result "0" of the majority gate logic operation. It is also possible to use the first input terminal as the negative terminal, the second input terminal as the positive terminal, the first level as the low level, and the second level as the high level, with the low level as the result "1" of the majority gate logic operation and the high level as the result "0" of the majority gate logic operation.

[0049] The schematic diagram of the gate-level representation for implementing the addition operation based on the majority gate logic is as Figure 2 shown. The control method of the approximate addition circuit based on the memristor provided by the present invention performs two majority gate logic operations. The first majority gate logic operation M(a i , b i , c i ) outputs the carry of the next digit , and the second majority gate logic operation outputs the calculation result s i . By combining the results of n addition sub-processes, the n-bit approximate addition operation result can be obtained.

[0050] Next, the implementation processes of the majority gate logic operation M(a, b, c) and the majority gate logic operation performed in each round of addition sub - process in the approximate addition operation of the present invention will be described in detail.

[0051] In the approximate addition operation, the first memristor, the second memristor, the third memristor, the resistor, and the voltage comparator implement the majority gate logic operation M(a, b, c); the first memristor, the second memristor, the fourth memristor, the resistor, and the voltage comparator implement the majority gate logic operation . It can be seen that the majority gate circuit structures on which the two different majority gate logic operations are based are the same, and both can be controlled based on the majority gate circuit as Figure 3 shown. By different manipulations, different majority gate logic operations can be achieved.

[0052] As Figure 3 shown, the majority gate circuit of each majority gate logic includes: M 1 , M 2 and M 3 three memristors, a fixed - value resistor, and a voltage comparator; among them, the positive electrodes of the memristors M 1 , M 2 and M 3 are controlled through the control terminals T 1 , T 2 and T 3 ; one end of the fixed - value resistor is controlled through the control terminal T 4 ; the other end of the fixed - value resistor is connected to the negative electrodes of the memristors M 1 , M 2 and M 3 , and the voltage of this common node is represented by V Com ; the control voltages of the other four control ports T 1 , T 2 , T 3 and T 4 are V T1 , V T2 , V T3 and V T4 respectively. The positive terminal of the voltage comparator is connected to the common node of the memristor and the series resistor, the negative terminal is connected to the reference voltage V Ref , and the output - terminal voltage is V o .

[0053] A memristor includes two resistance states, namely the high - resistance state (High Resistance State, HRS) and the low - resistance state (Low Resistance State, LRS). By applying a port voltage with a specific direction and magnitude, the memristor can transition between the two resistance states. Among them, by applying a voltage greater than Vset The forward voltage of can set the memristor from the high-resistance state to the low-resistance state; conversely, by applying a negative voltage less than V reset , the memristor can change from the low-resistance state to the high-resistance state. V set Is the threshold voltage for the memristor to change from the high-resistance state to the low-resistance state; V reset Is the threshold voltage for the memristor to change from the low-resistance state to the high-resistance state.

[0054] The high and low configuration resistances of the memristor are R H and R L , R H <<R L ; Preferably, in this embodiment, the resistance value of the resistor is equal to the resistance value of the low resistance of the memristor. The high resistance R H of the memristor = 100 KΩ, and the low resistance R L = 1 KΩ. In the case of the resistor R = 1 KΩ.

[0055] The three input variables a, b, and c of the majority gate logic are respectively mapped to the resistance states of the memristors M 1 , M 2 and M 3 , where the high-resistance state of the memristor corresponds to the logical value "0", and the low-resistance state of the memristor corresponds to the logical value "1"; the output of the logic is the voltage value at the output port of the comparator, where the output V o = V+ indicates that the output is a high level, corresponding to the logical result "1"; the output V o = V- indicates that the output is a low level, corresponding to the logical result "0".

[0056] Based on the above logic circuit, only by changing the control voltages applied to the control ports T 1 , T 2 , T 3 and T 4 , the two majority gate logics of M(a, b, c) and can be realized.

[0057] (1) Realization of the majority gate logic M(a, b, c).

[0058] As Figure 4 shown, by applying voltages V 1 , T 2 , T 3 and T 4 to the control ports T 1 , V 1 , V 1 , 0, V Ref = V Ref1 respectively; the result of the logical operation is obtained through the output terminal of the voltage comparator, and the port voltage V 1 and the reference voltage V of the voltage comparatorRef It is necessary to satisfy the following constraints: 0 < V 1 < V set ; V 1 / 2 < V Ref1 < 2V 1 / 3; The value of V 1 should be such that it cannot change the logical value currently written in the memristor, while the value of V Ref1 should be such that the voltage comparator can output the correct operation result. The design concept is as Figure 5 shown.

[0059] The principle of logical implementation lies in that when at least two of the input memristors M 1 , M 2 and M 3 are in the low-resistance state, the voltage V Com of the common node is greater than the reference voltage V Ref1 of the comparator, thus outputting a high level "1"; conversely, when at most one of the input memristors M 1 , M 2 and M 3 is in the low-resistance state, the voltage V Com of the common node is less than the reference voltage V Ref1 of the comparator, thus outputting a low level "0". Thus, the majority gate logic M(a, b, c) is implemented.

[0060] Taking Figure 5 's second combination as an example to further illustrate that the correct logical operation result can be obtained using the above method, and the other combinations can be deduced by analogy. In the second combination, a logical value "1" and two logical values "0" are input, and they are written into the memristors M 1 , M 2 and M 3 respectively. The memristor corresponding to the logical value "1" is in the low-resistance state, and the memristors corresponding to the logical values "0" are in the high-resistance state. Therefore, the equivalent circuit after writing the logical values is as Figure 6 shown. At this time, the voltage V Com of the common node is:

[0061] ;

[0062] That is, the voltage V Com of the common node is less than and close to V 1 / 2, and V 1 / 2 < V Ref1 . Therefore, the voltage V Com is less than V Ref1 . Thus, the voltage comparator outputs a low level, indicating the logical value "0", and the majority gate logic operation result is correct.

[0063] (2) Majority gate logic Implementation

[0064] As Figure 7 shown, by applying voltages V 1 , V 2 , 0, 0, V 3 and V 4 to control ports T 2 , T 2 , T Ref and T Ref2 respectively, where V 2 = V Ref2 ; the result of the logical operation is obtained through the output terminal of the voltage comparator, and the port voltage V 2 and the comparator reference voltage V set need to satisfy the following constraint conditions: 0 < V 2 < V Ref2 < V 2 ; V 2 is taken to ensure that the currently written logical value of the memristor cannot be changed, while V Ref2 is taken to ensure that the voltage comparator can output the correct operation result, and its design concept is as Figure 8 shown.

[0065] The principle of logical implementation is that when the input memristors M 1 , M 2 are both low-resistance "1", the voltage V Com of the common node can be pulled up, and the voltage V Com of the common node is greater than the comparator reference voltage V Ref2 , thus outputting a high level "1"; when there is a high-resistance "0" in the input memristors M 1 , M 2 and the input memristor M 3 is a low-resistance "1", the voltage V Com of the common node will be pulled down, and the voltage V Com of the common node is less than the comparator reference voltage V Ref2 , thus outputting a low level "0". Thus, the implementation of the majority gate logic is achieved.

[0066] In the present invention, in the i-th round of addition sub-process, the approximate addition calculation formula implemented based on the above two different majority gate logics is as follows:

[0067] ;

[0068] The truth table corresponding to the calculation formula is shown in Table 1 below. Among them, type A is the approximate addition operation result obtained by the present invention. It can be seen that there are only two summation errors, and the rest of the summation results are correct, indicating that the approximate addition operation can be realized by adopting the solution of the present invention. Moreover, although a certain operation accuracy is sacrificed, M(a, b, c) and The two majority gate logics can be implemented based on the same approximate addition circuit, and multiple operation units in it can be reused for the majority gate logic operation. In particular, the reuse of the first memristor and the second memristor, because M(a, b, c) and The two majority gate logics reuse the logic values of the first memristor and the second memristor. Therefore, there is no need to set more memristors and no need to perform more logic writing operations, so that the integration degree of the adder device is relatively high and the calculation speed is relatively fast.

[0069]

[0070] Further, take the 1-bit adder circuit (n = 1) based on the two majority gate logics as an example for illustration. Specifically, in the case where the high resistance R H of the memristor is 100 KΩ and the low resistance R L is 1 KΩ, the resistance R is 1 KΩ. The function of the adder is verified, and the experimental results as shown in Figure 9 are obtained. Among them, R M represents the resistance value of the memristor, and a i , b i , c i are the input logic values, c i+1 is the measured result of the carry, m i is the measured result of the summation, s i is the accurate result of the summation. The correct rate of the summation result is 6 / 8, and there is no error in the carry, all of which are correct. It can be seen from the figure that the one-bit approximate full adder provided by the present invention has the correct function and the calculation accuracy of the present invention is relatively high.

[0071] In a second aspect, the present invention provides an approximate addition operation device, including: an approximate addition circuit and a controller;

[0072] The approximate addition circuit includes: a voltage comparator, a resistor, and four memristors; the negative electrodes of the four memristors are all connected to one end of the resistor; the other end of the resistor is grounded; the first input end of the voltage comparator is connected to the common node of the four memristors and the resistor; the resistance value of the resistor is the low resistance state resistance value of the memristor;

[0073] The controller is used to execute the control method provided in the first aspect of the present invention.

[0074] Preferably, in an alternative embodiment, the resistance value of the resistor is the low resistance state resistance value of the memristor.

[0075] The related technical solutions are the same as the control method provided in the first aspect of the present invention, and will not be elaborated here.

[0076] In a third aspect, the present invention provides a control system, including: a memory and a processor, where the memory stores a computer program, and when the processor executes the computer program, it executes the control method provided in the first aspect of the present invention.

[0077] The related technical solutions are the same as the control method provided in the first aspect of the present invention, and will not be elaborated here.

[0078] In a fourth aspect, the present invention further provides a computer-readable storage medium, where the computer-readable storage medium includes a stored computer program, and when the computer program is run by a processor, it controls the device where the storage medium is located to execute the control method provided in the first aspect of the present invention.

[0079] The related technical solutions are the same as the control method provided in the first aspect of the present invention, and will not be elaborated here.

[0080] In a fifth aspect, the invention further provides a computer program product, including a computer program / instructions, and when the computer program / instructions are executed by a processor, they implement the control method provided in the first aspect of the present invention.

[0081] In summary, by designing a control method for an approximate adder circuit based on memristors and an approximate adder operation device, the present invention aims to solve problems such as high delay and large hardware overhead when using a single-logic memristor majority gate to implement arithmetic addition. By multiplexing memristors, it can implement the three-input majority gate logic M(a, b, c) = a·b + a·c + b·c, and can also implement a new majority gate logic including inversion logic . Through the iteration of the two logic operations, approximate addition operations can be realized. Therefore, the present invention can effectively improve the performance of the arithmetic function of the adder, significantly reduce the consumption of hardware resources and delay, and provide a new technical path for the efficient implementation of in-memory computing.

[0082] Those skilled in the art can easily understand that the above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A control method for an approximate adding circuit based on a memristor, characterized in that: Used to implement n-bit number a n ......a2a1 and b n ......approximate addition operation of b2b1; the approximate addition circuit comprises: a voltage comparator, a resistor and four identical memristors from the first to the fourth; the negative electrodes of the four memristors are connected to one end of the resistor; the other end of the resistor is grounded; the first input end of the voltage comparator is connected to the common node of the four memristors and the resistor; the resistance value of the resistor is the low resistance value of the memristor; n≥1; The control method comprises: executing n rounds of addition sub-processes; wherein the following operations are performed in the i-th round of addition sub-processes: Write the logic value a into the first memristor i , write the logic value b into the second memristor i , write the carry c used in the i-th round of addition into the third memristor i ; Select the first to third memristors to participate in the calculation: apply voltage V1 to the positive electrodes of the first to third memristors respectively, and connect the reference voltage V to the second input terminal of the voltage comparator. Ref1 , the result of the majority gate logic operation M(a i ,b i ,c i ) = a i b i + a i ·c i + b i ·c i , as the carry c used in the i+1th round of addition i+1 ; Write c into the fourth memristor i+1 , Select the first, second and fourth memristors to participate in the calculation: apply voltage V2 to the positive electrodes of the first and second memristors respectively, apply a voltage with an amplitude of 0 to the positive electrode of the fourth memristor, and connect the reference voltage V to the second input terminal of the voltage comparator. Ref2 , the result of the majority gate logic operation is obtained at the output of the voltage comparator , as the summation result s in the i-th round of addition i ; After completing the nth round of addition, c n+1 s n ......s2s1 is a n ......a2a1 and b n ......the result of adding b2b1; Where i=1,2,...,n; 0<V1<V set ; V1 / 2<V Ref1 <2V1 / 3;0<V2<V set ; V2 / 3<V Ref2 <V2 / 2;V set is the threshold value for the memristor to change from a high-resistance state to a low-resistance state; the high-resistance state of the memristor corresponds to a logic value "0", and the low-resistance state corresponds to a logic value "1". When the voltage at the first input terminal of the voltage comparator is greater than the voltage at the second input terminal, the output terminal outputs a first level, and the first level is used as the result of the majority gate logic operation "1"; otherwise, the output terminal outputs a second level, and the second level is used as the result of the majority gate logic operation "0".

2. The control method according to claim 1, characterized in that: The first input terminal is a positive terminal, the second input terminal is a negative terminal, the first level is a high level, and the second level is a low level.

3. A memristor-based approximate addition device, characterized in that: include: Approximate adding circuits and controllers; The approximate adding circuit comprises: a voltage comparator, a resistor and four identical memristors, from first to fourth; The negative electrodes of the four memristors are all connected to one end of the resistor; the other end of the resistor is grounded; the first input end of the voltage comparator is connected to the common node of the four memristors and the resistor; the resistance value of the resistor is the low resistance value of the memristor; The controller is used to execute the control method as claimed in claim 1 or 2.

4. The approximate addition operation device according to claim 3, characterized in that: The resistance values ​​of the low-resistance state and the high-resistance state of the memristor differ by at least two orders of magnitude.

5. A control system, characterized in that: include: A memory and a processor, wherein the memory stores a computer program, and the processor executes the control method according to claim 1 or 2 when executing the computer program.

6. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored computer program, wherein when the computer program is executed by a processor, the device where the storage medium is located is controlled to execute the control method according to claim 1 or 2.

7. A computer program product, characterized in that The invention comprises a computer program / instruction, which implements the control method as claimed in claim 1 or 2 when executed by a processor.

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