Method and device for controlling nonvolatile majority gate circuit and summing circuit based on memristor

Abstract

The invention discloses a control method and device of a non-volatile majority gate circuit and a summing circuit based on a memristor, and belongs to the technical field of microelectronic logic operation. In the majority gate circuit, the three memristors respectively and correspondingly input logic values a, b and c to be subjected to majority gate logic operation, and the result of the logic operation is determined by a voltage comparator according to the comparison result of the common node voltage and the reference voltage; by changing the voltage of the positive electrode of the memristor, two kinds of majority gate logics of M (a, b, c) and # imgabs0 # can be realized; in the implementation process of different types of majority gate logics, the number of memristors does not need to be increased, two kinds of majority gate logic operation can be achieved with few devices and high calculation speed, the two kinds of majority gate logics are complete, and any Boolean function can be achieved by combining the two kinds of majority gate logics; on the basis, the requirements for multifunctional logic in practical application can be met with high integration level and high calculation speed.

Description

Technical Field

[0001] The present invention belongs to the technical field of microelectronic logic operation, and more specifically, relates to a control method and device of a non-volatile majority gate circuit and an adding circuit based on a memristor. Background Art

[0002] Traditional computers use the von Neumann architecture, in which the storage unit and the processing unit are physically separated. Usually, the processing unit reads data from the storage unit, completes the corresponding arithmetic and logical operations, and then writes the data back to the storage unit. Frequent read and write operations put a huge burden on the bus, especially when the transmission speed is limited, which not only affects the data transmission efficiency, but also causes considerable power consumption. At the same time, the speed between the processing unit and the storage unit is not matched, and this difference is increasing year by year. Therefore, how to solve the "bottleneck problem" and "storage wall" problems in the von Neumann architecture has become a research focus in the field of computer architecture.

[0003] In order to break through these bottlenecks, storage-computing integrated technology came into being. This technology integrates computing and storage functions on the same hardware platform, achieving advantages such as high computing parallelism, low latency and low power consumption, and has gradually become a research hotspot in academia and industry. As a new type of non-volatile memory device, memristor has the advantages of low power consumption, small size and compatibility with CMOS process, making it an ideal candidate device for in-memory computing architecture. Memristors can store information by changing their resistance state and can still maintain their resistance state after power failure, so they are naturally suitable for digital logic operations. By selecting multiple memristor units for readout operations at the same time, the specified logical operations or complex arithmetic functions can be completed without explicitly taking out the memristor stored data, thereby realizing storage-computing integrated. This method greatly improves the speed and efficiency of information processing.

[0004] Majority-Inverter Graph (MIG) logic is a new type of data logic representation structure, which consists of majority gate logic (MAJ) and inverter logic (INV). The logic expression of the three-input majority decision gate is: M(a,b,c) = a·b +a·c + b·c, and the expression of the inverted logic is: . MAJ and negation logic constitute a complete logic set, that is, all Boolean logic functions can be implemented by iterating MAJ and negation logic. Logic optimization involves manipulating the logic representation structure to minimize certain target metrics. Logic optimization methods are closely linked to the data structures on which they are run. The MIG logic primitive itself demonstrates efficient logic synthesis potential. MIG often requires a smaller logic depth to implement the same complex logic, and thus has better experimental results in propagation delay. The key and difficulty of implementing MIG logic lies in the realization of majority gate logic. Majority gate logic plays a core role in arithmetic circuits such as adders and multipliers, as well as complex reasoning tasks. Therefore, it is of great significance to study a majority gate logic circuit.

[0005] However, the existing CMOS-based majority gate implementation not only has high hardware complexity, but also has significant delay and power consumption bottlenecks. The implementation of majority gate logic based on memristors provides a new solution to this problem. The existing memristor-based majority gate logic implementation uses three memristor units to operate a, b, and c respectively, realizing a three-input majority gate logic M(a,b,c) = a·b + a·c + b·c. Although it can reduce hardware complexity, this logic scheme only supports a single logic operation and lacks the implementation of inversion logic. In the multifunctional logic implemented based on majority gate logic, it often involves not only the traditional majority gate logic M(a,b,c) = a·b +a·c + b·c, but also the majority gate logic including inversion logic. ; Since two different types of majority gate logic are involved at the same time, if the existing implementation scheme of majority gate logic based on memristor is adopted, it is often necessary to convert the majority gate logic It is decomposed into two independent logic operations: majority gate logic M(a,b,c) and negation logic, and at least four memristor units are used to operate a, b, c, To perform operations, a large number of devices are required, the integration level is low, and the computing speed is also low, which cannot meet the needs of multi-functional logic in practical applications with higher integration level and computing speed. Summary of the invention

[0006] In view of the above defects or improvement needs of the prior art, the present invention provides a control method and device for a non-volatile majority gate circuit and an addition circuit based on a memristor, so as to solve the technical problem that the prior art is difficult to meet the requirements of multi-functional logic in practical applications with a higher integration and computing speed due to only supporting a single logic operation.

[0007] In order to achieve the above-mentioned object, in a first aspect, the present invention provides a control method of a non-volatile majority gate circuit based on a memristor; The majority gate circuit includes: a voltage comparator, a resistor and three identical memristors; the negative electrodes of the three memristors are all connected to one end of the resistor; the other end of the resistor is grounded; the first input end of the voltage comparator is connected to the common node of the three memristors and the resistor; the resistance value of the resistor is the low resistance value of the memristor; The above control method includes: The logic values ​​a, b, and c to be operated on by the majority gate logic operation are written into the three memristors respectively, and a voltage V is applied to the positive electrode of the memristor with the logic value a written. a , a voltage V is applied to the positive electrode of the memristor that writes the logic value b b , apply voltage V to the positive electrode of the memristor that writes the logic value c c , connect the reference voltage V to the second input of the voltage comparator Ref , the result of majority gate logic operation is obtained at the output of the voltage comparator; Among them, when the majority gate logic operation M(a,b,c) = a·b + a·c + b·c is performed on the logic values ​​a, b, c, V a = V b = V c = V 1 , V Ref = V Ref1 ; 0<V 1 <V set ; V 1 / 2<V Ref1 <2V 1 / 3; When performing majority gate logic operations on logic values ​​a, b, and c When V a =V b = V 2 , V c = 0, V Ref = V Ref2 ; 0<V 2 <V set ; V 2 / 3<V Ref2 <V 2 / 2; V set is the threshold value for the memristor to change from a high-resistance state to a low-resistance state; when the voltage at the first input terminal of the voltage comparator is greater than the voltage at the second input terminal, the output terminal outputs a first level, and the first level is used as the result of the majority gate logic operation "1"; otherwise, the output terminal outputs a second level, and the second level is used as the result of the majority gate logic operation "0".

[0008] Further preferably, the corresponding logic value is written by setting the high and low resistance states of the memristor; wherein the high resistance state of the memristor corresponds to the logic value "0", and the low resistance state corresponds to the logic value "1".

[0009] In a second aspect, the present invention provides a majority gate operation device, comprising: a majority gate circuit and a controller; The majority gate circuit includes: a voltage comparator, a resistor and three identical memristors; the negative electrodes of the three memristors are connected to one end of the resistor; the other end of the resistor is grounded; the first input end of the voltage comparator is connected to the common node of the three memristors and the resistor; the resistance value of the resistor is the low resistance value of the memristor; The controller is used to execute the control method provided by the first aspect of the present invention.

[0010] In a third aspect, the present invention provides a control method for an adding circuit for realizing an n-bit number a n ......a 2 a 1 With b n ......b 2 b 1 The addition operation is performed; the addition circuit comprises: a voltage comparator, a resistor and five memristors; the negative electrodes of the five memristors are connected to one end of the resistor; the other end of the resistor is grounded; the first input end of the voltage comparator is connected to the common node of the five memristors and the resistor; the resistance value of the resistor is the low resistance value of the memristor; n≥1; The control method comprises: executing n rounds of addition sub-processes; wherein the following operations are performed in the i-th round of addition sub-processes: Select three memristors and record them as the first memristor, the second memristor and the third memristor respectively; write the logic value a into the first memristor i , write the logic value b into the second memristor i , write the carry c of the i-th round of addition into the third memristor i ; Apply voltage V to the positive electrodes of the first memristor, the second memristor, and the third memristor respectively. 1 , connect the reference voltage V to the second input of the voltage comparator Ref1 , the result of the majority gate logic operation M(a i ,b i ,c i ) = a i b i + a i ·c i + b i ·c i , as the carry c of the i+1th round of addition i+1 ; Apply voltage V to the positive electrodes of the first memristor and the second memristor respectively. 2 , a voltage with an amplitude of 0 is applied to the positive electrode of the third memristor, and a reference voltage V is connected to the second input terminal of the voltage comparator Ref2 , the result of the majority gate logic operation is obtained at the output of the voltage comparator ; The remaining two unset memristors are marked as the fourth memristor and the fifth memristor, and M(a i ,b i ,c i ), write in the fifth memristor ; Apply voltage V to the positive electrodes of the third memristor and the fifth memristor respectively. 2 , a voltage with an amplitude of 0 is applied to the positive electrode of the fourth memristor, and a reference voltage V is connected to the second input terminal of the voltage comparator Ref2 , the result of the majority gate logic operation is obtained at the output of the voltage comparator , as the summation result s in the i-th round of addition i ; s n ......s 2 s 1 and c n+1 This is the desired n-bit number a n ......a 2 a 1 With b n ......b 2 b 1 The addition result of Where i=1,2,...,n; 0<V 1 <V set ; V 1 / 2<V Ref1 <2V 1 / 3; 0<V 2 <V set ; V 2 / 3<V Ref2 <V 2 / 2; V set is the threshold value for the memristor to change from a high-resistance state to a low-resistance state; when the voltage at the first input terminal of the voltage comparator is greater than the voltage at the second input terminal, the output terminal outputs a first level, and the first level is used as the result of the majority gate logic operation "1"; otherwise, the output terminal outputs a second level, and the second level is used as the result of the majority gate logic operation "0".

[0011] Further preferably, the corresponding logic value is written by setting the high and low resistance states of the memristor; wherein the high resistance state of the memristor corresponds to the logic value "0", and the low resistance state corresponds to the logic value "1".

[0012] In a fourth aspect, the present invention provides an addition operation device, comprising: an addition circuit and a controller; The adding circuit includes: a voltage comparator, a resistor and five memristors; the negative electrodes of the five memristors are all connected to one end of the resistor; the other end of the resistor is grounded; the first input end of the voltage comparator is connected to the common node of the five memristors and the resistor; the resistance value of the resistor is the low resistance value of the memristor; The controller is used to execute the control method provided in the third aspect of the present invention.

[0013] In a fifth aspect, the present invention provides a control system, comprising: a memory and a processor, wherein the memory stores a computer program, and the processor executes the control method provided in the first aspect or the third aspect of the present invention when executing the computer program.

[0014] In a sixth aspect, the present invention further provides a computer-readable storage medium, which includes a stored computer program, wherein when the computer program is executed by a processor, the device where the storage medium is located is controlled to execute the control method provided in the first aspect or the third aspect of the present invention.

[0015] In a seventh aspect, the invention further provides a computer program product, comprising a computer program / instruction, which, when executed by a processor, implements the control method provided in the first aspect or the third aspect of the invention.

[0016] In general, the above technical solutions conceived by the present invention can achieve the following beneficial effects: 1. In the control method of the non-volatile majority gate circuit based on memristor and the corresponding majority gate operation device provided by the present invention, the majority gate circuit includes three memristors, a resistor and a voltage comparator; the three memristors correspond to the input logic values ​​a, b, c to be performed on the majority gate logic operation, respectively, and the result of the majority gate logic operation is determined by the voltage comparator according to the comparison result between the common node voltage and the reference voltage; by changing the voltage of the positive electrode of the memristor, the traditional majority gate logic M (a, b, c) and the new majority gate logic including the inversion logic can be realized. ; Among them, most gate logic The implementation avoids the situation of decomposing it into two independent logic operations of majority gate logic M(a, b, c) and negation logic, and can be achieved by applying voltage in one step, so that in the implementation process of different types of majority gate logic, there is no need to increase the number of memristors, and two majority gate logic operations can be implemented with fewer devices and faster computing speed. Moreover, the two majority gate logics are complete, and any Boolean function can be implemented by combining the two majority gate logics, thereby meeting the needs of multifunctional logic; based on this, the present invention can meet the needs of multifunctional logic in practical applications with higher integration and faster computing speed.

[0017] 2. The control method of the non-volatile majority gate circuit based on memristors and the corresponding majority gate operation device provided by the present invention, after the logic calculation is completed, the three input memristor states still maintain the written input information value, which is non-destructive to the input information and has non-volatility, realizing a majority gate logic circuit whose input is the resistance value of the memristor and the operation process is non-destructive; the circuit has strong data reuse and does not require additional copying operations to save data in practical applications.

[0018] 3. The control method of the adding circuit and the corresponding adding operation device provided by the present invention are realized based on the realization idea of ​​the majority gate logic operation provided by the first aspect of the present invention, by controlling the combination M(a, b, c) and The two majority gate logics are combined and the implementation M(a, b, c) and The control method is used to control the addition operation accordingly, so that the addition operation can be realized with fewer devices and faster calculation speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic diagram of a majority gate circuit provided by an embodiment of the present invention.

[0020] Figure 2 A control schematic diagram of the majority gate logic M(a, b, c) provided in an embodiment of the present invention.

[0021] Figure 3 A schematic diagram of the design concept of the majority gate logic M(a, b, c) provided in an embodiment of the present invention.

[0022] Figure 4 The majority gate logic provided by the embodiment of the present invention Control diagram of .

[0023] Figure 5 The majority gate logic provided by the embodiment of the present invention Schematic diagram of the design concept.

[0024] Figure 6This is a schematic diagram of an adding circuit provided by the present invention.

[0025] Figure 7 A schematic diagram of a gate-level representation of an addition operation based on majority gate logic provided by the present invention.

[0026] Figure 8 The test results of the 1-bit addition circuit based on two majority gate logics provided by the present invention. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0028] In order to achieve the above-mentioned object, in a first aspect, the present invention provides a control method of a non-volatile majority gate circuit based on a memristor; The majority gate circuit includes: a voltage comparator, a resistor and three identical memristors; the negative electrodes of the three memristors are all connected to one end of the resistor; the other end of the resistor is grounded; the first input end of the voltage comparator is connected to the common node of the three memristors and the resistor; the resistance value of the resistor is the low resistance value of the memristor; The above control method includes: The logic values ​​a, b, and c to be operated on by the majority gate logic operation are written into the three memristors respectively, and a voltage V is applied to the positive electrode of the memristor with the logic value a written. a , a voltage V is applied to the positive electrode of the memristor that writes the logic value b b , apply voltage V to the positive electrode of the memristor that writes the logic value c c , connect the reference voltage V to the second input of the voltage comparator Ref , the result of majority gate logic operation is obtained at the output of the voltage comparator; Among them, when the majority gate logic operation M(a,b,c) = a·b + a·c + b·c is performed on the logic values ​​a, b, c, V a = V b = V c = V 1 , V Ref = V Ref1 ; 0<V 1 <V set ; V 1 / 2<V Ref1 <2V 1 / 3; When performing majority gate logic operations on logic values ​​a, b, and c When V a =V b = V 2 , V c = 0, V Ref = V Ref2 ; 0<V 2 <V set ; V 2 / 3<V Ref2 <V 2 / 2; V set is the threshold value for the memristor to change from a high-resistance state to a low-resistance state; when the voltage at the first input terminal of the voltage comparator is greater than the voltage at the second input terminal, the output terminal outputs a first level, and the first level is used as the result of the majority gate logic operation "1"; otherwise, the output terminal outputs a second level, and the second level is used as the result of the majority gate logic operation "0".

[0029] It can be understood that the corresponding relationship between the output level of the voltage comparator and the logic value can be flexibly set. For example, the first input terminal is the positive terminal, the second input terminal is the negative terminal, the first level is the high level, the second level is the low level, the high level is used as the result of the majority gate logic operation "1", and the low level is used as the result of the majority gate logic operation "0". Alternatively, the first input terminal can be used as the negative terminal, the second input terminal can be used as the positive terminal, the first level is the low level, the second level is the high level, the low level is used as the result of the majority gate logic operation "1", and the high level is used as the result of the majority gate logic operation "0".

[0030] In a second aspect, the present invention provides a majority gate operation device, comprising: a majority gate circuit and a controller; The majority gate circuit includes: a voltage comparator, a resistor and three identical memristors; the negative electrodes of the three memristors are connected to one end of the resistor; the other end of the resistor is grounded; the first input end of the voltage comparator is connected to the common node of the three memristors and the resistor; the resistance value of the resistor is the low resistance value of the memristor; The controller is used to execute the control method provided by the first aspect of the present invention.

[0031] The related technical solution is the same as the control method provided in the first aspect of the present invention, and will not be described in detail here.

[0032] In order to further illustrate the control method of the non-volatile majority gate circuit based on memristor and the corresponding majority gate operation device provided by the present invention, a specific embodiment is described in detail below: like Figure 1 As shown, this embodiment provides a majority gate circuit, including: M 1 、M 2 and M3 Three memristors, a fixed resistor and a voltage comparator; among them, the memristor M 1 、M 2 and M 3 The positive electrode passes through the control terminal T 1 , T 2 and T 3 To control, one end of the fixed resistor passes through the control terminal T 4 The other end of the fixed resistor is connected to the memristor M 1 、M 2 and M 3 The voltage of the common node is V Com Indicates that the remaining four control ports T 1 , T 2 , T 3 and T 4 The control voltages are V T1 、V T2 、V T3 and V T4 The positive terminal of the voltage comparator is connected to the common node of the memristor and the series resistor, and the negative terminal is connected to the reference voltage V Ref , the output voltage is V o .

[0033] The memristor has two resistance states, namely high resistance state (HRS) and low resistance state (LRS). The memristor can switch between the two resistance states by applying a port voltage of a specific direction and magnitude. set The memristor can be set from a high-resistance state to a low-resistance state by applying a forward voltage less than V reset The memristor can change from a low resistance state to a high resistance state by applying a negative voltage V set V is the threshold value of the memristor changing from high resistance state to low resistance state; reset is the threshold value at which the memristor changes from a low-resistance state to a high-resistance state.

[0034] The high and low configuration resistances of the memristor are R H and R L , R H < <R L Preferably, in this embodiment, the resistance of the resistor is equal to the resistance of the low resistance of the memristor. H =100KΩ, low resistance R L =1KΩ, the resistance R=1KΩ.

[0035] The three input variables a, b, and c of the majority gate logic are mapped to memristors M 1 、M2 and M 3 The resistance state of the memristor is the logic value "0", and the low resistance state of the memristor is the logic value "1". The output of the logic is the voltage value of the comparator output port, where the output V o = V+ indicates that the output is high level, and the corresponding logic result is "1"; the output V o = V- indicates that the output is low level, and the corresponding logic result is "0".

[0036] Furthermore, based on the above logic circuit, only the control port T 1 , T 2 , T 3 and T 4 The applied control voltage can realize M(a,b,c) and Two majority gate logics. The specific implementation steps are as follows: (1) Implementation of majority gate logic M(a,b,c): like Figure 2 As shown, by controlling the port T 1 , T 2 , T 3 and T 4 Apply voltage V 1 、V 1 、V 1 , 0, V Ref = V Ref1 The result of the logic operation is obtained through the output of the voltage comparator. The principle of logic implementation is that when the input memristor M 1 、M 2 and M 3 When at least two memristors are in low resistance state, the voltage V Com Greater than the comparator reference voltage V Ref1 , thus outputting a high level "1"; conversely, when the input memristor M 1 、M 2 and M 3 When at most one memristor is in low resistance state, the voltage V Com Less than the comparator reference voltage V Ref1 , thus outputting a low level "0". Specifically, to realize the majority gate logic M(a,b,c), the port voltage V 1 The voltage comparator reference voltage V Ref The following constraints must be met: 0<V 1 <V set ; V 1 / 2<V Ref1 <2V 1 / 3, its design concept is as follows Figure 3 shown.

[0037] (2) Majority gate logic Implementation: like Figure 4 As shown, by controlling the port T 1 , T 2 , T 3 and T 4 Apply voltage V 2 、V 2 , 0, 0, V Ref = V Ref2 The result of the logic operation is obtained through the output of the voltage comparator. The principle of logic implementation is that when the input memristor M 1 、M 2 When it is low resistance "1", it can pull up the voltage V of the common node Com , the voltage of the common node V Com Greater than the comparator reference voltage V Ref2 When the input memristor M 3 When it is low resistance, it will pull down the voltage V of the common node Com , the voltage of the common node V Com Less than the comparator reference voltage V Ref2 , thus outputting a low level "0". Specifically, to achieve the majority gate logic , port voltage V 2 The comparator reference voltage V Ref2 The following constraints must be met: 0<V 2 <V set ; V 2 / 3<V Ref2 <V 2 / 2, its design concept is as follows Figure 5 shown.

[0038] The present invention provides a reconfigurable majority gate logic implementation method based on memristor, which can realize M(a, b, c) and Two majority gate logics are proposed to improve the efficiency of arithmetic operations. At the same time, the two majority gate logics proposed are complete. By combining the two logics, any Boolean function can be realized. For example, for logic a·c, b=0 can be set in logic M(a,b,c); for logic a+c, b=0 can be set in logic M(a,b,c); for logic , in logic In the example, b=0 can be used to implement this; for logic , in logic It can be realized by setting b=1; for more complex logical expressions, it can be implemented by iterating the above logic.

[0039] Considering that the adder is the most basic arithmetic unit in digital circuit design, its performance directly affects the efficiency and power consumption of data processing. Traditional CMOS adders rely on full adder structures, and their implementation process requires multiple logic gates to be cascaded. Especially in carry calculations, the delay shows a linear accumulation trend as the number of bits increases. This cascade logic not only leads to large consumption of hardware resources, but also shows obvious performance bottlenecks in the expansion of high-bit adders. The adder design based on memristors provides a new optimization approach. For example, the Boolean calculation of carry output and sum output can be realized through majority gate logic, which can significantly reduce the logic level and delay. However, traditional majority gate and negation logic are two independent logical operations. They need to iterate more operation steps when realizing the full adder function, and the calculation speed and area efficiency still need to be further improved. Therefore, the present invention focuses on the adder as an example, and specifically explains the application of the two majority gate logic implementation methods provided by the present invention in the adder operation implementation process, as follows: In a third aspect, the present invention provides a control method for an adding circuit for realizing an n-bit number a n ......a 2 a 1 With b n ......b 2 b 1 addition operation; such as Figure 6 As shown, the adding circuit includes: a voltage comparator, a resistor and five memristors; the negative electrodes of the five memristors are all connected to one end of the resistor; the other end of the resistor is grounded; the first input end of the voltage comparator is connected to the common node of the five memristors and the resistor; the resistance value of the resistor is the low resistance value of the memristor; n≥1; The control method comprises: executing n rounds of addition sub-processes; wherein the following operations are performed in the i-th round of addition sub-processes: Select three memristors and record them as the first memristor, the second memristor and the third memristor respectively; write the logic value a into the first memristor i , write the logic value b into the second memristor i , write the carry c of the i-th round of addition into the third memristor i ; Wherein, logic "1" means setting the memristor resistance state to low resistance, and logic "0" means setting the memristor resistance state to high resistance. When i=1, the carry c 1 Input by the user, can be either logic "1" or logic "0".

[0040] Apply voltage V to the positive electrodes of the first memristor, the second memristor, and the third memristor respectively. 1 , connect the reference voltage V to the second input of the voltage comparator Ref1 , the result of the majority gate logic operation M(ai ,b i ,c i ) = a i b i + a i ·c i + b i ·c i , as the carry c of the i+1th round of addition i+1 In this process, the first memristor, the second memristor, the third memristor, the resistor and the voltage comparator constitute the majority gate circuit in the first aspect of the present invention. The control method provided by the first aspect of the present invention realizes the majority gate logic operation M(a i ,b i ,c i ) = a i b i +a i ·c i + b i ·c i .

[0041] Apply voltage V to the positive electrodes of the first memristor and the second memristor respectively. 2 , a voltage with an amplitude of 0 is applied to the positive electrode of the third memristor, and a reference voltage V is connected to the second input terminal of the voltage comparator Ref2 , the result of the majority gate logic operation is obtained at the output of the voltage comparator , which is denoted as s i In this process, the first memristor, the second memristor, the third memristor, the resistor and the voltage comparator constitute the majority gate circuit in the first aspect of the present invention. The control method provided by the first aspect of the present invention realizes the majority gate logic operation. .

[0042] The remaining two unset memristors are marked as the fourth memristor and the fifth memristor, and M(a i ,b i ,c i ), write in the fifth memristor ; Apply voltage V to the positive electrodes of the third memristor and the fifth memristor respectively. 2 , a voltage with an amplitude of 0 is applied to the positive electrode of the fourth memristor, and a reference voltage V is connected to the second input terminal of the voltage comparator Ref2 , the result of the majority gate logic operation is obtained at the output of the voltage comparator , as the summation result s in the i-th round of addition iIn this process, the third memristor, the fifth memristor, the fourth memristor, the resistor and the voltage comparator constitute the majority gate circuit in the first aspect of the present invention, and the majority gate logic operation is realized through the control method provided by the first aspect of the present invention. .

[0043] After n rounds of addition sub-processes, s n ......s 2 s 1 and c n+1 This is the desired n-bit number a n ......a 2 a 1 With b n ......b 2 b 1 The addition result of Where i=1,2,...,n; 0<V 1 <V set ; V 1 / 2<V Ref1 <2V 1 / 3; 0<V 2 <V set ; V 2 / 3<V Ref2 <V 2 / 2; V set is the threshold value for the memristor to change from a high-resistance state to a low-resistance state; when the voltage at the first input terminal of the voltage comparator is greater than the voltage at the second input terminal, the output terminal outputs a first level, and the first level is used as the result of the majority gate logic operation "1"; otherwise, the output terminal outputs a second level, and the second level is used as the result of the majority gate logic operation "0".

[0044] It can be understood that the corresponding relationship between the output level of the voltage comparator and the logic value can be flexibly set. For example, the first input terminal is the positive terminal, the second input terminal is the negative terminal, the first level is the high level, the second level is the low level, the high level is used as the result of the majority gate logic operation "1", and the low level is used as the result of the majority gate logic operation "0". Alternatively, the first input terminal can be used as the negative terminal, the second input terminal can be used as the positive terminal, the first level is the low level, the second level is the high level, the low level is used as the result of the majority gate logic operation "1", and the high level is used as the result of the majority gate logic operation "0".

[0045] The gate-level representation diagram of the addition operation based on majority gate logic is as follows Figure 7 shown.

[0046] It should be noted that the above majority gate logic operation M(a i ,b i ,c i ) = ai b i + a i ·c i + b i ·c i AND majority gate logic operation The execution order is not limited.

[0047] Furthermore, a 1-bit addition circuit (n = 1) based on two majority gate logics is used as an example for explanation. Specifically, the high resistance R H =100KΩ, low resistance R L =1KΩ, the resistor R = 1KΩ. Verify the adder function and get Figure 8 The experimental results shown (where R M represents the resistance value of the memristor), it can be seen from the figure that the one-bit full adder provided by the present invention functions correctly and the calculation accuracy of the present invention is high.

[0048] In a fourth aspect, the present invention provides an addition operation device, comprising: an addition circuit and a controller; The adding circuit includes: a voltage comparator, a resistor and five memristors; the negative electrodes of the five memristors are all connected to one end of the resistor; the other end of the resistor is grounded; the first input end of the voltage comparator is connected to the common node of the five memristors and the resistor; the resistance value of the resistor is the low resistance value of the memristor; The controller is used to execute the control method provided in the third aspect of the present invention.

[0049] Preferably, in an optional implementation manner, the resistance value of the resistor is a low-resistance resistance value of the memristor.

[0050] The related technical solution is the same as the control method provided in the third aspect of the present invention, and will not be described in detail here.

[0051] In a fifth aspect, the present invention provides a control system, comprising: a memory and a processor, wherein the memory stores a computer program, and the processor executes the control method provided in the first aspect or the third aspect of the present invention when executing the computer program.

[0052] The related technical solution is the same as the control method provided in the first aspect or the third aspect of the present invention, and will not be described in detail here.

[0053] In a sixth aspect, the present invention further provides a computer-readable storage medium, which includes a stored computer program, wherein when the computer program is executed by a processor, the device where the storage medium is located is controlled to execute the control method provided in the first aspect or the third aspect of the present invention.

[0054] The related technical solution is the same as the control method provided in the first aspect or the third aspect of the present invention, and will not be described in detail here.

[0055] In a seventh aspect, the invention further provides a computer program product, comprising a computer program / instruction, which, when executed by a processor, implements the control method provided in the first aspect or the third aspect of the invention.

[0056] In summary, the present invention aims to solve the problems of the singleness of the majority gate logic of the current memristor and the high delay of the addition arithmetic function and the large hardware overhead by designing a reconfigurable majority gate logic circuit based on memristors and its adder implementation scheme. The two majority gates proposed include both the traditional three-input majority gate logic M(a,b,c) = a·b + a·c + b·c and the new majority gate logic including the negation logic For most gate logic Set a = "0", b = "1" to get , that is, the negation logic is realized. The two proposed reconfigurable logics can realize MIG logic, and MIG logic is complete, so the proposed reconfigurable logic is complete, and two majority gate logics are proposed through iteration to realize any Boolean function. By combining the storage and calculation characteristics of memristors, the present invention can effectively improve the performance of arithmetic functions such as logical operations and adders, significantly reduce hardware resource consumption and delay, and provide a new technical path for efficient in-memory computing.

[0057] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A control method for a non-volatile majority gate circuit based on a memristor, characterized in that: The majority gate circuit comprises: a voltage comparator, a resistor and three identical memristors; the negative electrodes of the three memristors are all connected to one end of the resistor; the other end of the resistor is grounded; the first input end of the voltage comparator is connected to a common node of the three memristors and the resistor; the resistance value of the resistor is the low resistance value of the memristor; The control method comprises: The logic values ​​a, b, and c to be operated on by the majority gate logic operation are written into the three memristors respectively, and a voltage V is applied to the positive electrode of the memristor with the logic value a written. a , a voltage V is applied to the positive electrode of the memristor that writes the logic value b b , apply voltage V to the positive electrode of the memristor that writes the logic value c c , connect the reference voltage V to the second input of the voltage comparator Ref , the result of majority gate logic operation is obtained at the output of the voltage comparator; Among them, when the majority gate logic operation M(a,b,c) = a·b + a·c + b·c is performed on the logic values ​​a, b, c, V a =V b = V c = V1, V Ref = V Ref1 ; 0<V1<V set ; V1 / 2<V Ref1 <2V1 / 3; When performing majority gate logic operations on logic values ​​a, b, and c When V a = V b = V2, V c = 0, V Ref = V Ref2 ; 0<V2<V set ; V2 / 3<V Ref2 <V2 / 2; V set is the threshold value for the memristor to change from a high-resistance state to a low-resistance state; when the voltage at the first input terminal of the voltage comparator is greater than the voltage at the second input terminal, the output terminal outputs a first level, and the first level is used as the result of the majority gate logic operation "1"; otherwise, the output terminal outputs a second level, and the second level is used as the result of the majority gate logic operation "0".

2. The control method according to claim 1, characterized in that: The corresponding logic value is written by setting the high and low resistance states of the memristor; wherein the high resistance state of the memristor corresponds to the logic value "0", and the low resistance state corresponds to the logic value "1".

3. A majority gate computing device, characterized in that: include: Most gate circuits and controllers; The majority gate circuit comprises: a voltage comparator, a resistor and three identical memristors; The negative electrodes of the three memristors are all connected to one end of the resistor; the other end of the resistor is grounded; the first input end of the voltage comparator is connected to the common node of the three memristors and the resistor; the resistance value of the resistor is the low resistance value of the memristor; The controller is used to execute the control method described in claim 1 or 2.

4. A control method for an adding circuit, characterized in that: Used to implement n-bit number a n ......a2a1 and b n ......addition operation of b2b1; the addition circuit comprises: a voltage comparator, a resistor and five memristors; the negative electrodes of the five memristors are all connected to one end of the resistor; the other end of the resistor is grounded; the first input end of the voltage comparator is connected to the common node of the five memristors and the resistor; the resistance value of the resistor is the low resistance value of the memristor; n≥1; The control method comprises: executing n rounds of addition sub-processes; wherein the following operations are performed in the i-th round of addition sub-processes: Select three memristors and record them as the first memristor, the second memristor and the third memristor respectively; write the logic value a into the first memristor i , write the logic value b into the second memristor i , write the carry c of the i-th round of addition into the third memristor i ; A voltage V1 is applied to the positive electrodes of the first memristor, the second memristor, and the third memristor respectively, and a reference voltage V is connected to the second input terminal of the voltage comparator. Ref1 , the result of the majority gate logic operation M(a i ,b i ,c i ) = a i b i + a i ·c i + b i ·c i , as the carry c of the i+1th round of addition i+1 ; A voltage V2 is applied to the positive electrodes of the first memristor and the second memristor respectively, a voltage with an amplitude of 0 is applied to the positive electrode of the third memristor, and a reference voltage V is connected to the second input terminal of the voltage comparator. Ref2 , the result of the majority gate logic operation is obtained at the output of the voltage comparator ; The remaining two unset memristors are marked as the fourth memristor and the fifth memristor, and M(a i ,b i ,c i ), write in the fifth memristor ; A voltage V2 is applied to the positive electrodes of the third memristor and the fifth memristor respectively, a voltage with an amplitude of 0 is applied to the positive electrode of the fourth memristor, and a reference voltage V is connected to the second input terminal of the voltage comparator. Ref2 , the result of the majority gate logic operation is obtained at the output of the voltage comparator , as the summation result s in the i-th round of addition i ; s n ...s2s1 and c n+1 This is the desired n-bit number a n ......a2a1 and b n ......the result of adding b2b1; Where i=1,2,...,n; 0<V1<V set ; V1 / 2<V Ref1 <2V1 / 3;0<V2<V set ; V2 / 3<V Ref2 <V2 / 2;V set is the threshold value for the memristor to change from a high-resistance state to a low-resistance state; when the voltage at the first input terminal of the voltage comparator is greater than the voltage at the second input terminal, the output terminal outputs a first level, and the first level is used as the result of the majority gate logic operation "1"; otherwise, the output terminal outputs a second level, and the second level is used as the result of the majority gate logic operation "0".

5. The control method according to claim 4, characterized in that: The corresponding logic value is written by setting the high and low resistance states of the memristor; wherein the high resistance state of the memristor corresponds to the logic value "0", and the low resistance state corresponds to the logic value "1".

6. An addition operation device, characterized in that: include: Adding circuits and controllers; The adding circuit comprises: a voltage comparator, a resistor and five memristors; The negative electrodes of the five memristors are all connected to one end of the resistor; the other end of the resistor is grounded; the first input end of the voltage comparator is connected to the common node of the five memristors and the resistor; the resistance value of the resistor is the low resistance value of the memristor; The controller is used to execute the control method described in claim 4 or 5 of the present invention.

7. A control system, characterized in that: include: A memory and a processor, wherein the memory stores a computer program, and the processor executes the control method according to claim 1, 2, 4 or 5 when executing the computer program.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored computer program, wherein when the computer program is executed by a processor, the device where the storage medium is located is controlled to execute the control method of claim 1, 2, 4 or 5.

9. A computer program product, characterized in that The invention comprises a computer program / instruction, which implements the control method of claim 1, 2, 4 or 5 when executed by a processor.

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