Program control method, device, electronic device and storage medium

Abstract

An embodiment of the present invention provides a program control method, apparatus, electronic device, and storage medium. The method is applied to a control system, and the control system includes a control end and a program scheduler. The method includes: the control end reads the clock signal of the design to be tested. When the clock signal reaches the edge of a clock cycle, the control end suspends the operation of the design to be tested and sends a control signal to the program scheduler; when the program scheduler receives the control signal sent by the control end, it schedules the subroutines in sequence according to the execution order of the subroutines in the test program; when all the subroutines in the test program run to the preset positions, the program scheduler sends a wake-up signal to the control end; when the control end receives the wake-up signal, it drives the design to be tested to continue running to the next clock cycle edge. In the embodiment of the present invention, the hardware clock can be controlled by a software programming language and parallel operations can be completed, improving the program control efficiency.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular, to a program control method, device, electronic device, and storage medium. Background Art

[0002] In the process of verifying a design under test, generally a hardware programming language is used. In recent years, there has been a need to use a software programming language for chip verification. However, a software programming language cannot well control the parallel operations and clocks required by the hardware. Among existing tools, cocotb can well meet the control requirements by controlling coroutines based on callbacks. But the requirements for implementation are relatively high and the running efficiency is also low. Therefore, the efficiency of controlling the hardware clock and completing parallel operations in a software programming language is reduced. Summary of the Invention

[0003] Embodiments of the present invention provide a program control method, device, electronic device, and storage medium, which can solve the problem that in related technologies, a software programming language cannot well control the parallel operations and clocks required by the hardware, and the requirements for control implementation are relatively high and the running efficiency is also low.

[0004] To solve the above problems, embodiments of the present invention disclose a program control method applied to a control system. The control system includes a control end and a program scheduler. The method includes:

[0005] The control end reads a clock signal of a design under test. When the clock signal reaches an edge of a clock cycle, the control end pauses the operation of the design under test and sends a control signal to the program scheduler;

[0006] When the program scheduler receives the control signal sent by the control end, the program scheduler sequentially schedules the subprograms according to the execution order of each subprogram in the test program; when each subprogram in the test program runs to a preset position, the program scheduler sends a wake-up signal to the control end;

[0007] When the control end receives the wake-up signal, the control end drives the design under test to continue running to the next clock cycle edge.

[0008] Optionally, the method further includes:

[0009] When the clock signal reaches an edge of a clock cycle, obtain a first operation result of the design under test;

[0010] When at least one subprogram runs to a preset position, obtain a second operation result corresponding to the at least one subprogram;

[0011] Match the first operation result with the second operation result;

[0012] When the first operation result matches the second operation result, it is determined that the design under test runs correctly;

[0013] When the first operation result does not match the second operation result, it is determined that the design under test runs incorrectly.

[0014] Optionally, when the control terminal receives a wake-up signal, driving the design under test to continue running to the next clock cycle edge includes:

[0015] When the control terminal receives a wake-up signal, it calls a drive interface, sends a drive signal to the design under test, and drives the design under test to continue running to the next clock cycle edge.

[0016] Optionally, driving the design under test to continue running to the next clock cycle edge includes:

[0017] Obtain the signal value of the first interface in each subroutine; the first interface is any interface in the subroutine;

[0018] Determine the second interface in the design under test that matches the first interface;

[0019] Input the signal value into the second interface and drive the design under test to continue running to the next clock cycle edge.

[0020] Optionally, when the program scheduler receives a control signal sent by the control terminal, scheduling the subroutines in sequence according to the execution order of each subroutine in the test program includes:

[0021] When the program scheduler receives a control signal sent by the control terminal, it schedules the first subroutine in the test program according to the execution order of each subroutine in the test program and monitors the running status of the first subroutine;

[0022] When the first subroutine runs to a preset position, the program scheduler schedules the second subroutine; where the second subroutine is the next subroutine corresponding to the first subroutine.

[0023] Optionally, before the control terminal reads the clock signal of the design under test, the method further includes:

[0024] According to the test logic of the test program, add wait functions at preset positions in each subroutine; the wait functions are used to pause the running of the subroutine.

[0025] On the other hand, an embodiment of the present invention discloses a program control device applied to a control system. The control system includes a control terminal and a program scheduler. The device includes:

[0026] A reading module, configured to read the clock signal of the design under test;

[0027] A sending module, configured to pause the operation of the design under test and send a control signal to the program scheduler when the clock signal reaches an edge of a clock cycle;

[0028] A scheduling module, configured to schedule the subroutines in sequence according to the execution order of the subroutines in the test program when receiving the control signal sent by the control terminal;

[0029] The sending module is further configured to send a wake-up signal to the control terminal when each subroutine in the test program runs to a preset position;

[0030] A driving module, configured to drive the design under test to continue running to the next clock cycle edge when receiving the wake-up signal.

[0031] Optionally, the device further includes:

[0032] An obtaining module, configured to obtain the first operation result of the design under test when the clock signal reaches an edge of a clock cycle; and obtain the second operation result corresponding to at least one subroutine when at least one subroutine runs to a preset position;

[0033] A matching module, configured to match the first operation result with the second operation result;

[0034] A determining sub-module, configured to determine that the design under test runs correctly when the first operation result matches the second operation result; and determine that the design under test runs incorrectly when the first operation result does not match the second operation result.

[0035] Optionally, the driving module includes:

[0036] A driving sub-module, configured to call a driving interface and send a driving signal to the design under test to drive the design under test to continue running to the next clock cycle edge when receiving the wake-up signal.

[0037] Optionally, the driving module further includes:

[0038] An obtaining sub-module, configured to obtain the signal value of a first interface in each subroutine; the first interface is any interface in the subroutine;

[0039] A first determination sub-module, configured to determine a second interface in the design under test that matches the first interface;

[0040] An input module, configured to input the signal value into the second interface and drive the design under test to continue running to the next clock cycle edge.

[0041] Optionally, the scheduling module further includes:

[0042] A first scheduling sub-module, configured to schedule a first subroutine in the test program according to the execution order of each subroutine in the test program when receiving a control signal sent by a control end;

[0043] A monitoring module, configured to monitor the running status of the first subroutine;

[0044] A second scheduling sub-module, configured to schedule a second subroutine when the first subroutine runs to a preset position; wherein, the second subroutine is the next subroutine corresponding to the first subroutine.

[0045] Optionally, the apparatus further includes:

[0046] An adding module, configured to add a waiting function at preset positions of each subroutine according to the test logic of the test program; the waiting function is used to pause the running of the subroutine.

[0047] On the other hand, an embodiment of the present invention further discloses an electronic device, which includes a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface complete communication with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions cause the processor to execute the foregoing program control method.

[0048] An embodiment of the present invention further discloses a readable storage medium. When instructions in the readable storage medium are executed by a processor of an electronic device, the electronic device can execute the foregoing program control method.

[0049] Embodiments of the present invention have the following advantages:

[0050] An embodiment of the present invention provides a program control method. The control system includes a control terminal and a program scheduler. During the process of program control, when the program scheduler receives a control signal sent by the control terminal, it schedules the sub-programs in sequence according to the execution order of each sub-program in the test program; when each sub-program in the test program runs to a preset position, it sends a wake-up signal to the control terminal; at the same time, the control terminal reads the clock signal of the design under test and starts to drive the design under test. When the clock signal reaches the edge of a clock cycle, it pauses the operation of the design under test and sends a control signal to the program scheduler; that is, the scheduling of sub-programs by the program scheduler and the driving of the design under test by the control terminal are executed alternately, so that the hardware clock can be controlled by a software programming language and parallel operations can be completed, improving the program control efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments of the present invention. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0052] Figure 1 It is a flowchart of the steps of an embodiment of the program control method of the present invention;

[0053] Figure 2 It is a schematic structural diagram of a control system of the present invention;

[0054] Figure 3 It is a schematic diagram of the execution order flow of the program in a model of the present invention;

[0055] Figure 4 It is a block diagram of the structure of an embodiment of the program control device of the present invention;

[0056] Figure 5 It is a block diagram of the structure of an electronic device provided by an example of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0057] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art without creative efforts based on the embodiments of the present invention belong to the scope of protection of the present invention.

[0058] In the description and claims of the present invention, the terms "first", "second", etc. are used to distinguish similar objects, rather than to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same category, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the description and claims is used to describe the relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. In the embodiments of the present invention, the term "a plurality" refers to two or more, and other quantifiers are similar.

[0059] Method embodiment

[0060] Refer to Figure 1 , which shows a step flowchart of an embodiment of a program control method of the present invention. The method may specifically include the following steps:

[0061] Step S101: The control end reads the clock signal of the design under test. When the clock signal reaches the edge of a clock cycle, the operation of the design under test is paused, and a control signal is sent to the program scheduler.

[0062] Step S102: When the program scheduler receives the control signal sent by the control end, it schedules the subroutines in sequence according to the execution order of each subroutine in the test program; when each subroutine in the test program runs to a preset position, a wake-up signal is sent to the control end.

[0063] Step S103: When the control end receives the wake-up signal, it drives the design under test to continue running to the next clock cycle edge.

[0064] The program control method provided by the embodiments of the present invention can be applied to a control system, and the control system includes a control end and a program scheduler. Refer to Figure 2 , which shows a schematic diagram of the architecture of a control system provided by an embodiment of the present invention. As Figure 2 shown, the control end is used to drive the design under test, and the program scheduler is used to schedule each subroutine in the test program. The program scheduler in the present invention may include components capable of scheduling each subroutine. By reasonably arranging the scheduling order of the program, resources such as the Central Processing Unit (CPU) are made as busy as possible, reducing idle time.

[0065] In an embodiment of the present invention, through the interaction between the control end and the program scheduler, parallel control of each subroutine in the test program and synchronous control of the test program and the design under test can be achieved.

[0066] Exemplarily, the control end in the embodiment of the present invention can first read the clock signal of the design under test. When the clock signal reaches the edge of a clock cycle, the operation of the design under test is paused, and a control signal is sent to the program scheduler.

[0067] The control signal is used to instruct the program scheduler to schedule the subroutines in sequence according to the execution order of each subroutine in the test program.

[0068] The design under test is driven by the clock signal. The operation of the design under test can be paused by controlling the clock signal. When the input of the clock signal in the design under test is stopped, the design under test will also stop running. The design under test (DUT) refers to the circuit design or implementation to be tested in prototype verification. Exemplarily, the design under test can be a register transfer level (RTL) circuit or other hardware designs.

[0069] When the program scheduler receives the control signal sent by the control end, it schedules the subroutines in sequence according to the execution order of each subroutine in the test program; when each subroutine in the test program runs to a preset position, a wake-up signal is sent to the control end.

[0070] The test program is used to test the performance or correctness of the design under test to verify whether the design under test meets the expected functional and performance requirements.

[0071] As an example, the user can pre-write a test program according to the test requirements, and divide the test program into at least one subroutine according to the dependencies and execution order of the test cases or execution flows in the test program, and determine the execution order of each subroutine. It should be noted that each subroutine in the embodiment of the present invention can be executed in parallel. For example, assume that the test program includes subroutine 1, subroutine 2, and subroutine 3. In one execution stage, subroutine 1 can be run to the preset position first, then subroutine 2 to the preset position, and finally subroutine 3 to the preset position; in the next execution stage, continue to run from subroutine 1, and the parallel control of the subroutines is achieved by executing each subroutine in segments.

[0072] The preset position refers to the position where a wait function is added in each subroutine. When running to the preset position, the program scheduler will pause the operation of the subroutine.

[0073] The wake-up signal can be used to trigger the driving of the design under test to continue running, and can also be used to wake up the waiting signals of each subroutine when receiving the control signal sent by the control terminal, so as to avoid the situation that each subroutine cannot continue running and continuously stops at the preset position.

[0074] Exemplarily, in the case where the test program includes programs such as subroutine 1, subroutine 2, subroutine 3, ……, etc., the program scheduler can schedule subroutine 1, subroutine 2, subroutine 3, ……, etc. subroutines in sequence, and then when subroutine 1, subroutine 2, subroutine 3, ……, etc. subroutines all run to the preset position, send a wake-up signal to the control terminal.

[0075] When the control terminal receives the wake-up signal, it drives the design under test to continue running to the next clock cycle edge, so as to achieve the synchronous control of the test program and the design under test.

[0076] Refer to Figure 3 , which shows the schematic diagram of the execution sequence flow of the program in a model of the present invention, and specifically may include the following:

[0077] Based on coroutines in the software programming language to meet the hardware's need for parallel operations. Users can design multiple coroutines running simultaneously and write independent control logics in each coroutine.

[0078] In this model, a control terminal is used to manage the clock of the hardware, and the control terminal is also implemented by a coroutine. Since the design in chip verification only changes the state at the clock edge, the control terminal continuously stops at the clock edge, and only when it stops each time will it actually advance the clock of the DUT and directly push it to the next clock edge. Between ①② and between ②③, it is driven by the control terminal.

[0079] Exemplarily, refer to Figure 3, the test program refers to ①, ②, ③, etc. The test program ① includes a.value = 1, b.value = 2 and Await in subroutine 1, c.value = 1, d.value = 3 and Await in subroutine 2, e.value = 5, f.value = 6 and Await in subroutine 3, and other subroutines; when the program scheduler receives the control signal sent by the control terminal, it starts to schedule subroutine 1. When subroutine 1 runs to Await, the program scheduler can schedule subroutine 2. When subroutine 2 runs to Await, the program scheduler can schedule subroutine 3. Similarly, when subroutine 3 runs to Await, the program scheduler can schedule the next subroutine until all subroutines of the test program ① have run to the Await position, which means that the test program ① has finished running. Then, the control terminal can drive the design under test. When the design under test runs to the next clock cycle edge, the operation of the design under test is paused, and the operation of the test program ② starts. Similarly, the program scheduler starts to schedule subroutine 1, schedule subroutine 2, schedule subroutine 3, and sequentially execute (print(c.value), a.value = 2, Await) in subroutine 1, (c.valid = 0, d.valid = 1, Await) in subroutine 2, (print(e.value), e.value = 4, Await) in subroutine 3, ……, etc., to achieve the synchronous control of the test program and the design under test.

[0080] The control terminal issues (control signal) event signals to guide the operation of each coroutine. Every time the control terminal reaches a clock edge, it will stop and issue an event signal to inform other coroutines that the clock has reached the next edge. Other coroutines synchronize with the DUT clock by detecting this signal. When all coroutines have executed to waiting for the next clock signal, the control is returned to the control terminal to continue driving the DUT.

[0081] An embodiment of the present invention provides a program control method. The control system includes a control terminal and a program scheduler. During the program control process, when the program scheduler receives the control signal sent by the control terminal, it schedules the subroutines in sequence according to the execution order of each subroutine in the test program; when all subroutines in the test program have run to the preset position, it sends a wake-up signal to the control terminal; at the same time, the control terminal reads the clock signal of the design under test and starts to drive the design under test. When the clock signal reaches a clock cycle edge, the operation of the design under test is paused, and a control signal is sent to the program scheduler; that is, the scheduling of subroutines by the program scheduler and the driving of the design under test are executed alternately, so that the hardware clock can be controlled by a software programming language and parallel operations can be completed, improving the program control efficiency.

[0082] In an embodiment of the present invention, the program control method may specifically include the following steps:

[0083] Step S104: When the clock signal reaches an edge of a clock cycle, obtain a first operation result of the design under test.

[0084] In an embodiment of the present invention, during the process of program control, the control system may also obtain a first operation result of the design under test when the clock signal reaches an edge of a clock cycle.

[0085] In an embodiment of the present invention, the operation result of the design under test may include intermediate results generated during the operation of the design under test, or may also include final results output by the design under test. According to the operation result of the design under test, it can be verified whether the design under test meets the expected function.

[0086] The first operation result of the design under test may be one or a set of numerical values, or may also be status information or timing information, etc., which is not limited in the embodiments of the present invention.

[0087] Exemplarily, in an embodiment of the present invention, taking the design under test as an RTL circuit as an example, when the first result is data output, the data output may be one or a set of numerical values. Specifically, the data output may be a digital signal after being processed such as filtered and amplified.

[0088] Or, in an embodiment of the present invention, the first operation result of the design under test may be timing information represented by a square wave. For example, the first operation result may be timing information with a step size of 2 and an amplitude of 2 on the time axis.

[0089] Step S105: When at least one subroutine has all run to a preset position, obtain a second operation result corresponding to the at least one subroutine.

[0090] In an embodiment of the present invention, after obtaining the first operation result of the design under test when the clock signal reaches an edge of a clock cycle, the control system may also obtain a second operation result corresponding to the at least one subroutine when at least one subroutine has all run to a preset position.

[0091] Exemplarily, when subroutines such as subroutine 1, subroutine 2, subroutine 3,... have all run to a preset position, the second operation results corresponding to all subroutines can be obtained.

[0092] The second operation result of the subroutine may include intermediate results generated during the operation of the subroutine, or may also include final results output after the subroutine has finished running. The second operation result is used as a reference value for the first operation result of the design under test to verify whether the operation of the design under test is in error.

[0093] The second operation result of the subroutine can be one or a set of numerical values, or can be status information, timing information, etc., which are not limited in the embodiments of the present invention.

[0094] Exemplarily, in the embodiments of the present invention, taking the design under test as an RTL circuit as an example, when the second operation result of the subroutine is a numerical value, the output can be one or a set of numerical values. Specifically, the second operation result output by the subroutine can be a digital signal after being processed such as filtered and amplified.

[0095] Or, in the embodiments of the present invention, the second operation result of the subroutine can be timing information represented by a square wave. For example, the second operation result can be timing information with a step size of 2 and an amplitude of 2 on the time axis.

[0096] It can be understood that in the embodiments of the present invention, when at least one subroutine has run to a preset position, the second operation result obtained can include the operation results of each subroutine.

[0097] Exemplarily, when subroutine 1 runs to a preset position, the obtained operation result corresponding to subroutine 1 is [0, 2], and when subroutine 2 runs to a preset position, the obtained operation result corresponding to subroutine 2 is [0, 3],..., after all subroutines have run to the preset position, the second operation result corresponding to the at least one subroutine can be a set of the operation results corresponding to each subroutine.

[0098] Step S106: Match the first operation result with the second operation result.

[0099] In the embodiments of the present invention, when at least one subroutine has run to a preset position and the second operation result corresponding to the at least one subroutine is obtained, the control system can also match the first operation result with the second operation result, and determine whether the design under test runs incorrectly according to the matching result.

[0100] It can be understood that the situation where the first operation result matches the second operation result includes that the first operation result is the same as the second operation result, or the first operation result and the second operation result belong to the same reference interval, etc.

[0101] Exemplarily, in the embodiments of the present invention, when the first operation result of the design under test and the second operation result of the subroutine are both numerical values, the two sets of numerical values are compared. Assume that the first operation result of the design under test is 1, and the second operation result corresponding to the at least one subroutine is 2. At this time, the first operation result of the device under test is different from the second operation result of the subroutine, and it can be determined that the first operation result does not match the second operation result.

[0102] Alternatively, in the embodiments of the present invention, when both the first operation result of the design under test and the second operation result of the subroutine are timing information, the two sets of timing information are compared. When the step size and amplitude corresponding to the first operation result of the design under test are the same as those corresponding to the second operation result of the subroutine, at this time, the first operation result of the device under test is the same as the second operation result of the subroutine, and it can be determined that the first operation result matches the second operation result.

[0103] Step S107: When the first operation result matches the second operation result, it is determined that the design under test runs correctly.

[0104] In the embodiments of the present invention, after matching the first operation result and the second operation result, when the first operation result matches the second operation result, it is determined that the design under test runs correctly.

[0105] Step S108: When the first operation result does not match the second operation result, it is determined that the design under test runs errantly.

[0106] In the embodiments of the present invention, after matching the first operation result and the second operation result, the control system can also determine that the design under test runs errantly when the first operation result does not match the second operation result.

[0107] Further, when it is determined that the design under test runs errantly, the operation of the design under test and each subroutine can be paused, and the design under test can be debugged using simulation software.

[0108] In an alternative embodiment of the present invention, when the control terminal receives a wake-up signal, it drives the design under test to continue running to the next clock cycle edge, which may specifically include the following steps:

[0109] Step S1031: When the control terminal receives a wake-up signal, it calls the drive interface to send a drive signal to the design under test, driving the design under test to continue running to the next clock cycle edge.

[0110] In the embodiments of the present invention, the control terminal calling the drive interface can send a drive signal to the design under test, or call the drive interface to implement the transmission of the clock signal.

[0111] Wherein, the drive interface may be a logic module in the test platform for generating and controlling the input interface signals to the DUT. The core function of the drive interface is to provide the DUT with input stimuli (such as clocks, data, control signals) that conform to the protocol specifications, and simulate the interaction behavior in the real environment to verify whether the functions and timings of the DUT are normal.

[0112] Exemplarily, the control terminal can also send a driving signal to the design under test through a driving protocol.

[0113] In an alternative embodiment of the present invention, driving the design under test to continue running to the next clock cycle edge may specifically include the following steps:

[0114] Step S1032: Obtain the signal values of the first interfaces in each subroutine; the first interface is any interface in the subroutine;

[0115] Step S1033: Determine the second interface in the design under test that matches the first interface;

[0116] Step S1034: Input the signal value into the second interface and drive the design under test to continue running to the next clock cycle edge.

[0117] In an embodiment of the present invention, during the process of program control, the control terminal can obtain the signal values of the first interfaces in each subroutine; the first interface is any interface in the subroutine.

[0118] Among them, the signal values of the first interfaces in each subroutine are used to drive the design under test. Through the interfaces of the design under test, the signal values can be transmitted to the design under test, thereby controlling the operation of the design under test.

[0119] After obtaining the signal values of the first interfaces in each subroutine, the control terminal can also determine the second interface in the design under test that matches the first interface.

[0120] Among them, different mapping methods can be used to map the first interface and the second interface, and then the second interface in the design under test that matches the first interface can be determined.

[0121] Exemplarily, in an embodiment of the present invention, two groups of interfaces in the design under test, such as AXI4 and Tilelink, can be obtained first. That is, the interfaces of the design under test are determined. It is necessary to drive the AXI4 interface through each interface in each subroutine. At this time, a virtual AXI4 interface needs to be defined, and the verification code (each interface in each subroutine) is used to drive this virtual AXI4 interface.

[0122] Exemplarily, the process of matching the first interface with the second interface of the design under test may include: obtaining the name of the first interface in the first subroutine, and simultaneously capturing the name of the design under test. In the case where the name of the design under test only has a common prefix more than the name of the first interface in the first subroutine, prefix mapping can be used to match the first interface with the second interface of the design under test.

[0123] Exemplarily, when the design under test has a common prefix more than the names in the first interface of the first subroutine, such as io_a, io_b, io_cin, io_sum, io_cout, in this case, the prefix io_ can be specified as the mapping method to map to the DUT. That is, when the common prefix can be extracted, io_ is directly used as the mapping method, so that a is connected to io_a, b is connected to io_b, cin is connected to io_cin, sum is connected to io_sum, and cout is connected to io_cout. When the prefix of the new design under test is no longer io_, but inout_a, inout_b, inout_cin, inout_sum, inout_cout, in order to be able to connect, inout_ is used for mapping. That is, by identifying this prefix and then connecting the subsequent identical ones.

[0124] Alternatively, the process of matching the first interface with the second interface of the design under test may include: obtaining the name of the first interface in the first subroutine, and at the same time capturing the name of the design under test. When the name of the design under test can be represented by a regular expression, regular expression mapping can be used to match the first interface with the second interface of the design under test.

[0125] Exemplarily, when the signal names in the DUT can be matched by a regular expression and the captured names can match the names in the interface, this mapping method can be used. For example, the above can be matched by the regular expression r“io_(.*)”, and the characters captured by the parentheses just match the names in the interface. If there are multiple capture groups, then they are linked into a string in order and then matched. Among them, regular expression mapping means writing a matching rule and then matching the first interface in the first subroutine with the second interface of the design under test. The “io_(.*)” matching mode captures the (signal) after io_.

[0126] Alternatively, the process of matching the first interface with the second interface of the design under test may include: obtaining the name of the first interface in the first subroutine, and at the same time capturing the name of the design under test, and establishing a one-to-one mapping relationship by passing in a dictionary, so as to be able to match the first interface with the second interface of the design under test.

[0127] Exemplarily, a one-to-one mapping relationship is established by passing in a dictionary. This is consistent with the traditional connection method (however, mapping can be achieved through multi-level nesting, where the dictionary contains prefix mappings, and the prefix mappings include regular expression mappings), and the mapping is completed through the dictionary in the first interface of the first subroutine. For example, {"a": "io_a", "b": "io_b", "cin": "io_cin", "cout": "io_cout"}.

[0128] After determining the second interface in the design under test that matches the first interface, the control end can also input a signal value to the second interface and drive the design under test to continue running to the next clock cycle edge.

[0129] Among them, through the ports, values can be assigned to the design under test, that is, each subroutine transfers the data required for the operation of the design under test to the design under test, and then the design under test can be controlled through each interface in each subroutine.

[0130] In an optional embodiment of the present invention, when the program scheduler receives the control signal sent by the control end, it schedules the subroutines in sequence according to the execution order of each subroutine in the test program, which may specifically include the following steps:

[0131] Step S1021: When the program scheduler receives the control signal sent by the control end, it schedules the first subroutine in the test program according to the execution order of each subroutine in the test program, and monitors the running status of the first subroutine.

[0132] Step S1022: When the first subroutine runs to a preset position, the program scheduler schedules the second subroutine; where the second subroutine is the next subroutine corresponding to the first subroutine.

[0133] In the embodiment of the present invention, during the process of program control, when the program scheduler receives the control signal sent by the control end, it schedules the first subroutine in the test program according to the execution order of each subroutine in the test program, and monitors the running status of the first subroutine.

[0134] Exemplarily, in the embodiment of the present invention, the first subroutine is any one of the subroutines scheduled in the test program, which may be the first subroutine, or the last subroutine, or the middle subroutine scheduled in the test program, and is not limited in the embodiment of the present invention.

[0135] The program scheduler determines the execution progress of the first subroutine by monitoring the running status of the first subroutine. When the first subroutine runs to a preset position, it schedules the second subroutine; where the second subroutine is the next subroutine corresponding to the first subroutine.

[0136] Among them, the second subroutine is the next subroutine corresponding to the first subroutine.

[0137] Exemplarily, referring to Figure 3 , when the first subroutine is the first subroutine (subroutine 1), the second subroutine is the next subroutine adjacent to the first subroutine (subroutine 2). When the first subroutine is the middle subroutine in the scheduling test program, the second subroutine is the next subroutine adjacent to this middle subroutine. For example, if the first subroutine is subroutine 2, then the second subroutine is subroutine 3, which is not limited in the embodiments of the present invention.

[0138] In the embodiments of the present invention, when the program scheduler receives the control signal sent by the control terminal, during the process of sequentially scheduling the subroutines according to the execution order of each subroutine in the test program, each time a subroutine in the test program is scheduled, the running situation of this subroutine can be monitored at the same time. When this subroutine runs to the preset position, then the scheduling process for the next subroutine adjacent to this subroutine is started.

[0139] In the embodiments of the present invention, before the control terminal reads the clock signal of the design under test, the following steps may further be included:

[0140] According to the test logic of the test program, wait functions are added at the preset positions of each subroutine; the wait function is used to pause the running of the subroutine.

[0141] In the embodiments of the present invention, the test logic of the test program refers to the core part of the test program, which is used to check the running result and judge whether the test passes. Through well-designed test logic, the functional correctness of the DUT can be effectively verified.

[0142] Among them, the wait function refers to the execution code used to pause the running of the subroutine. When each subroutine runs to the wait function, the subroutine will stop running.

[0143] In the embodiments of the present invention, before the control terminal reads the clock signal of the design under test, the control system may further add wait functions at the preset positions of each subroutine according to the test logic of the test program.

[0144] Exemplarily, referring to Figure 3 , the wait function refers to the Await function added in each subroutine. During the process of the program scheduler scheduling subroutine 1, when subroutine 1 runs to the position of the Await function, it will stop here.

[0145] In summary, the embodiment of the present invention provides a program control method, which is applied to a control system. The control system includes a control end and a program scheduler. During the process of program control, when the program scheduler receives a control signal sent by the control end, it schedules the subprograms in sequence according to the execution order of each subprogram in the test program; when each subprogram in the test program runs to a preset position, it sends a wake-up signal to the control end; at the same time, the control end reads the clock signal of the design under test and starts to drive the design under test. When the clock signal reaches the edge of a clock cycle, the operation of the design under test is paused, and a control signal is sent to the program scheduler; that is, the scheduling of the subprograms by the program scheduler and the driving of the design under test by the control end are executed alternately, so that the hardware clock can be controlled by a software programming language and parallel operations can be completed, improving the program control efficiency.

[0146] It should be noted that, for the method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that the embodiments of the present invention are not limited by the described action sequence, because according to the embodiments of the present invention, some steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily essential to the embodiments of the present invention.

[0147] Device embodiments

[0148] Referring to Figure 4 , a structural block diagram of a program control device of the present invention is shown. The device is applied to a control system. The control system includes a control end and a program scheduler. The device includes:

[0149] A reading module 301, configured to read the clock signal of the design under test;

[0150] A sending module 302, configured to pause the operation of the design under test and send a control signal to the program scheduler when the clock signal reaches the edge of a clock cycle;

[0151] A scheduling module 303, configured to schedule the subprograms in sequence according to the execution order of each subprogram in the test program when receiving a control signal sent by the control end;

[0152] The sending module is configured to send a wake-up signal to the control end when each subprogram in the test program runs to a preset position;

[0153] A driving module 304, configured to drive the design under test to continue running to the next clock cycle edge when receiving a wake-up signal.

[0154] Optionally, the device further includes:

[0155] An acquisition module, configured to acquire a first operation result of the design under test when the clock signal reaches an edge of a clock cycle; and acquire a second operation result corresponding to at least one subroutine when all the at least one subroutines run to a preset position.

[0156] A matching module, configured to match the first operation result with the second operation result.

[0157] A determination sub-module, configured to determine that the design under test runs correctly when the first operation result matches the second operation result; and determine that the design under test runs incorrectly when the first operation result does not match the second operation result.

[0158] Optionally, the driving module includes:

[0159] A driving sub-module, configured to call a driving interface to send a driving signal to the design under test to drive the design under test to continue running to the next clock cycle edge when a wake-up signal is received.

[0160] Optionally, the driving module further includes:

[0161] An acquisition sub-module, configured to acquire a signal value of a first interface in each subroutine; the first interface is any interface in the subroutine.

[0162] A first determination sub-module, configured to determine a second interface in the design under test that matches the first interface.

[0163] An input module, configured to input the signal value into the second interface and drive the design under test to continue running to the next clock cycle edge.

[0164] Optionally, when the program scheduler receives a control signal sent by a control terminal, it schedules the subroutines in sequence according to the execution order of the subroutines in the test program, including:

[0165] A first scheduling sub-module, configured to schedule a first subroutine in the test program according to the execution order of the subroutines in the test program when a control signal sent by a control terminal is received.

[0166] A monitoring module, configured to monitor the running status of the first subroutine.

[0167] A second scheduling sub-module, configured to schedule a second subroutine when the first subroutine runs to a preset position; where the second subroutine is the next subroutine corresponding to the first subroutine.

[0168] Optionally, before the control terminal reads the clock signal of the design under test, the method further includes:

[0169] Adding a module, configured to add a wait function at a preset position of each subroutine according to the test logic of the test program; the wait function is used to pause the operation of the subroutine.

[0170] In summary, the embodiment of the present invention provides a program control device. During the process of program control, when the program scheduler receives a control signal sent by the control terminal, it schedules the subroutines in sequence according to the execution order of each subroutine in the test program; when each subroutine in the test program runs to a preset position, it sends a wake-up signal to the control terminal; at the same time, the control terminal reads the clock signal of the design under test and starts to drive the design under test. When the clock signal reaches an edge of a clock cycle, it pauses the operation of the design under test and sends a control signal to the program scheduler; that is, the scheduling of subroutines by the program scheduler and the driving of the design under test by the control terminal are executed alternately, so that the hardware clock can be controlled by a software programming language and parallel operations can be completed, improving the program control efficiency.

[0171] For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple. For related parts, refer to the partial description of the method embodiment.

[0172] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0173] Regarding the processor in the above embodiments, the specific manner in which each module performs operations has been described in detail in the embodiments related to the method, and will not be elaborated here.

[0174] Referring to Figure 5 , it is a structural block diagram of an electronic device for program control provided by an embodiment of the present invention. As Figure 5 shown, the electronic device includes: a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface complete mutual communication through the communication bus; the memory is used to store executable instructions, and the executable instructions cause the processor to execute the program control method of the foregoing embodiments.

[0175] The processor may be a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable devices, transistor logic devices, hardware components, or any combination thereof. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0176] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a peripheral component interconnect (PCI) bus, an extended industry standard architecture (EISA) bus, or the like. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 5 only one line is shown in the figure, but it does not mean that there is only one bus or one type of bus.

[0177] The memory may be a read only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM), or other type of dynamic storage device that can store information and instructions. It may also be an electrically erasable programmable read only memory (EEPROM), a compact disc read only memory (CD-ROM), magnetic tape, floppy disk, and optical data storage device, etc.

[0178] The embodiments of the present invention also provide a non-transitory computer-readable storage medium. When the instructions in the storage medium are executed by the processor of an electronic device (server or terminal), the processor is enabled to execute Figure 1 the program control method shown.

[0179] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0180] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, apparatus, or computer program product. Therefore, the embodiments of the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0181] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each flow and / or block in the flowchart and / or block diagram can be implemented by computer program instructions, and the combination of the flows and / or blocks in the flowchart and / or block diagram can also be implemented. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal devices generate a device for implementing the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0182] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal device to work in a predictive manner, so that the instructions stored in the computer-readable memory generate a manufactured product including an instruction device, and the instruction device implements the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0183] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device, so that a series of operation steps are executed on the computer or other programmable terminal device to generate a computer-implemented process, and thus the instructions executed on the computer or other programmable terminal device provide steps for implementing the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0184] Although the preferred embodiments of the embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications to these embodiments once they know the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the embodiments of the present invention.

[0185] Finally, it should also be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or terminal device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or terminal device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or terminal device comprising said element.

[0186] The above has introduced in detail a program control method, apparatus, electronic device and storage medium provided by the present invention. Specific examples are used in this text to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A program control method, characterized in that, Applied to a control system, the control system includes a control terminal and a program scheduler, and the method includes: The control terminal reads the clock signal of the design under test. When the clock signal reaches the edge of a clock cycle, the operation of the design under test is paused, and a control signal is sent to the program scheduler; When the program scheduler receives the control signal sent by the control terminal, it schedules the subroutines in sequence according to the execution order of the subroutines in the test program; when all the subroutines in the test program run to the preset position, a wake-up signal is sent to the control terminal; the execution order is determined in advance according to the test cases or the dependency relationship of the execution flow in the test program; the preset position is the position where a wait function is added in each of the subroutines; When the control terminal receives the wake-up signal, it drives the design under test to continue running to the next clock cycle edge.

2. The method according to claim 1, wherein The method further includes: When the clock signal reaches the edge of a clock cycle, the first operation result of the design under test is obtained; When at least one subroutine runs to the preset position, the second operation result corresponding to the at least one subroutine is obtained; The first operation result is matched with the second operation result; When the first operation result matches the second operation result, it is determined that the design under test runs correctly; When the first operation result does not match the second operation result, it is determined that the design under test runs errantly.

3. The method according to claim 1, characterized in that When the control terminal receives the wake-up signal and drives the design under test to continue running to the next clock cycle edge, it includes: When the control terminal receives the wake-up signal, it calls the drive interface, sends a drive signal to the design under test, and drives the design under test to continue running to the next clock cycle edge.

4. The method according to claim 1, characterized in that, Driving the design under test to continue running to the next clock cycle edge includes: Obtaining the signal value of the first interface in each of the subroutines; the first interface is any interface in the subroutine; Determining the second interface in the design under test that matches the first interface; Inputting the signal value into the second interface and driving the design under test to continue running to the next clock cycle edge.

5. The method according to claim 1, characterized in that, When the program scheduler receives the control signal sent by the control terminal and schedules the subroutines in sequence according to the execution order of the subroutines in the test program, it includes: When the program scheduler receives the control signal sent by the control terminal, it schedules the first subroutine in the test program according to the execution order of the subroutines in the test program, and monitors the running situation of the first subroutine; When the first subroutine runs to the preset position, the program scheduler schedules the second subroutine; wherein, the second subroutine is the next subroutine corresponding to the first subroutine.

6. The method according to claim 1, wherein Before the control terminal reads the clock signal of the design under test, the method further includes: According to the test logic of the test program, a wait function is added to the preset positions of each subroutine; the wait function is used to pause the operation of the subroutine.

7. A program control device, characterized in that, Applied to a control system, the control system includes a control terminal and a program scheduler, and the device includes: A reading module, configured to read the clock signal of the design under test; A sending module, configured to pause the operation of the design under test and send a control signal to the program scheduler when the clock signal reaches an edge of a clock cycle; A scheduling module, configured to sequentially schedule the subroutines in the execution order of each subroutine in the test program when receiving the control signal sent by the control terminal; the execution order is determined in advance according to the test cases in the test program or the dependency relationship of the execution flow; The sending module, configured to send a wake-up signal to the control terminal when each subroutine in the test program runs to a preset position; the preset position is the position where a wait function is added to each subroutine; A driving module, configured to drive the design under test to continue running to the next clock cycle edge when receiving the wake-up signal.

8. The device according to claim 7, characterized in that, The device further includes: An obtaining module, configured to obtain the first operation result of the design under test when the clock signal reaches an edge of a clock cycle; and obtain the second operation result corresponding to at least one subroutine when at least one subroutine runs to a preset position; A matching module, configured to match the first operation result with the second operation result; A determining sub-module, configured to determine that the design under test runs correctly when the first operation result matches the second operation result; and determine that the design under test runs incorrectly when the first operation result does not match the second operation result.

9. The device according to claim 7, characterized in that, The driving module includes: A driving sub-module, configured to call a driving interface and send a driving signal to the design under test to drive the design under test to continue running to the next clock cycle edge when receiving the wake-up signal.

10. An electronic device, characterized in that, The electronic device includes a processor, a memory, a communication interface, and a communication bus, and the processor, the memory, and the communication interface complete communication with each other through the communication bus; The memory is used to store executable instructions, and the executable instructions cause the processor to execute the program control method according to any one of claims 1 to 6.

11. A readable storage medium, characterized in that, When the instructions in the readable storage medium are executed by the processor of the electronic device, the processor is enabled to execute the program control method according to any one of claims 1 to 6.

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