Equipment instruction processing method, computer equipment and computer readable storage medium

Abstract

The invention provides an equipment instruction processing method, computer equipment and a computer readable storage medium. The equipment instruction processing method comprises the following steps: a main processor obtains a hash value of an operator to be executed according to an operator category of the operator to be executed and a required parameter of the operator to be executed; when the hash value of the operator to be executed exists in a pre-cache file of the main processor, the main processor obtains a first instruction string of the operator to be executed based on the pre-cache file, and the pre-cache file is used for pre-caching the instruction string of each operator generated by the main processor; the main processor corrects a temporary address field contained in the first instruction string to obtain a first corrected instruction string; and the main processor sends the first corrected instruction string to an instruction execution unit, so that the instruction execution unit executes the instruction content contained in the first corrected instruction string according to the corrected address field contained in the first corrected instruction string. The instruction processing efficiency of the computer equipment can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of computer data processing, and in particular to a device instruction processing method, a computer device, and a computer-readable storage medium. Background Art

[0002] With the continuous development of computer technology, more and more computing tasks need to rely on computer devices to complete. However, in some high-computation scenarios, such as the computing tasks of deep learning models, the computing power of traditional computer equipment can no longer meet the needs of high-computing scenarios. In view of this, in the related art, an instruction execution unit with higher computing power is loaded on the computer device. However, the inventors of this application found in the actual research and development process that when using the instruction execution unit to execute instructions offline, it often happens that the configuration time of the current instruction will be longer than the execution time of the previous instruction, resulting in a low instruction execution rate, and the high computing power performance of the instruction execution unit cannot be fully utilized. Summary of the invention

[0003] The present application provides a device instruction processing method, a computer device, and a computer-readable storage medium, which can improve the instruction processing efficiency of the computer device.

[0004] In a first aspect, the present application provides a device instruction processing method, which is applied to a computer device, wherein the computer device includes a main processor and an instruction execution unit, and the method includes:

[0005] The main processor obtains a hash value of the operator to be executed according to the operator category of the operator to be executed and the required parameters of the operator to be executed;

[0006] When the hash value of the operator to be executed exists in the pre-cache file of the main processor, the main processor obtains the first instruction string of the operator to be executed based on the pre-cache file, wherein the pre-cache file is used to pre-cache the instruction string of each operator generated by the main processor;

[0007] The main processor performs correction processing on the temporary address field included in the first instruction string to obtain a first corrected instruction string;

[0008] The main processor sends the first revised instruction string to the instruction execution unit, so that the instruction execution unit executes the instruction content included in the first revised instruction string according to the revised address field included in the first revised instruction string.

[0009] In some embodiments, the method further comprises:

[0010] The main processor generates an instruction string of the operator to be executed according to the operator information of the operator to be executed;

[0011] The main processor obtains the hash value of the operator to be executed according to the operator category of the operator to be executed and the required parameters of the operator to be executed;

[0012] The main processor associates the instruction string of the operator to be executed and the hash value of the operator to be executed and adds them to the pre-cache file.

[0013] In some embodiments, the main processor generates an instruction string of the operator to be executed according to the operator information of the operator to be executed, including:

[0014] The main processor configures the instruction simulation computing function according to preset instruction configuration information, wherein the instruction configuration information includes at least one of the instruction content position, instruction length position, and instruction quantity position of each operator category;

[0015] The main processor performs address configuration processing on the operator to be executed to obtain a temporary address field of the operator to be executed;

[0016] The main processor generates an instruction string of the operator to be executed according to the operator information of the operator to be executed and the temporary address field of the operator to be executed through the instruction simulation calculation function.

[0017] In some embodiments, the main processor associates the instruction string of the to-be-executed operator with the hash value of the to-be-executed operator and adds it to the pre-cache file, including:

[0018] The main processor performs serialization processing on the instruction string of the operator to be executed to obtain a serialized instruction string of the operator to be executed;

[0019] The main processor associates the serialized instruction string of the operator to be executed and the hash value of the operator to be executed and adds them to the hard disk pre-cache file of the computer device.

[0020] In some embodiments, the main processor obtains the first instruction string of the operator to be executed based on the pre-cache file, including:

[0021] The main processor loads a target serialized instruction string matching the hash value of the operator to be executed from each serialized instruction string of the pre-cache file;

[0022] The main processor deserializes the serialized instruction string to obtain a deserialized instruction string as the first instruction string of the operator to be executed.

[0023] In some embodiments, the address field includes a base register field and an offset field, and the base register field includes a base keyword and a base value;

[0024] The main processor performs correction processing on the temporary address field included in the first instruction string to obtain a first corrected instruction string, including:

[0025] The main processor determines a data memory address of the first instruction string;

[0026] The main processor modifies the base address register field in the first instruction string from a temporary base address value to the data memory address, and obtains a modified base address value of the base address register field;

[0027] A first modified instruction string is obtained based on the modified base address value of the base address register field.

[0028] In some embodiments, the method further comprises:

[0029] When the hash value of the operator to be executed does not exist in the pre-cache file of the main processor, the main processor generates a second instruction string of the operator to be executed according to the operator information of the operator to be executed;

[0030] The main processor performs correction processing on the temporary address field included in the second instruction string to obtain a second corrected instruction string;

[0031] The main processor sends the second revised instruction string to the instruction execution unit, so that the instruction execution unit executes the instruction content included in the second revised instruction string according to the revised address field included in the second revised instruction string.

[0032] In some embodiments, the corrected address field includes a corrected base address value and an offset value, the offset value is equal to a preset specified value, and the corrected base address value and the offset value are used by the instruction execution unit to determine the input memory address and output memory address of the operator to be executed.

[0033] In a second aspect, the present application further provides a computer device, comprising a processor and a memory, wherein the memory stores a computer program, and when the processor calls the computer program in the memory, it executes any device instruction processing method provided in the present application.

[0034] In a third aspect, the present application also provides a computer-readable storage medium on which a computer program is stored, and the computer program is loaded by a processor to execute the device instruction processing method.

[0035] In the present application, when the instruction execution unit is to actually execute the instruction, the hash value of the operator to be executed is obtained according to the operator category of the operator to be executed and the required parameters of the operator to be executed, and the first instruction string of the operator to be executed is read from the pre-cache file. On the one hand, since the main processor of the computer device can be used to complete the instruction configuration, there is no need to configure the instruction in the instruction execution unit, and the computing power of the main processor is relatively good, the configuration instruction time can be reduced, thereby avoiding the problem that the instruction configuration time of the instruction execution unit is longer than the instruction execution time, giving full play to the high computing power performance of the instruction execution unit, and improving the instruction execution rate. On the other hand, since the instruction string of each operator can be pre-configured and cached in the pre-cache file, when the hash value of the operator to be executed exists in the pre-cache file of the main processor, that is, when the instruction string of the operator to be executed exists in the pre-cache file, the pre-cached instruction string can be directly read for execution without the need to configure the instruction in real time, which can also improve the instruction processing efficiency of the computer device to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0037] Figure 1 is a schematic block diagram of the structure of a computer device provided in an embodiment of the present application;

[0038] Figure 2 It is a flow chart of a device instruction processing method provided in an embodiment of the present application;

[0039] Figure 3 It is a flowchart of an embodiment of the main processor configuration instruction and sending an instruction string to the instruction execution unit provided by the embodiment of the present application;

[0040] Figure 4 It is a schematic diagram illustrating an embodiment of an instruction pre-caching process of a main processor provided by an embodiment of the present application;

[0041] Figure 5 It is another flowchart of the device instruction processing method provided in the embodiment of the present application;

[0042] Figure 6 It is a schematic diagram illustrating the time required for instruction configuration and execution completion when the instruction execution unit configures instructions in an embodiment of the present application. DETAILED DESCRIPTION

[0043] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0044] The flowcharts shown in the accompanying drawings are only examples and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may also be decomposed, combined or partially merged, so the actual execution order may change according to actual conditions.

[0045] In the description of the embodiments of the present application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0046] In order to enable any person skilled in the art to implement and use the present application, the following description is provided. In the following description, details are listed for the purpose of explanation. It should be understood that those of ordinary skill in the art can recognize that the present application can also be implemented without using these specific details. In other examples, the known process will not be elaborated in detail to avoid unnecessary details that make the description of the present application embodiment obscure. Therefore, the present application is not intended to be limited to the embodiments shown, but is consistent with the widest range of principles and features disclosed in accordance with the embodiments of the present application.

[0047] The embodiment of the present application provides a device instruction processing method, a computer device and a computer-readable storage medium. The computer device may be a desktop computer, a notebook computer, a server, etc.

[0048] Some embodiments of the present application are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0049] Please refer to Figure 1 , Figure 1 It is a schematic block diagram of the structure of a computer device provided in an embodiment of the present application.

[0050] like Figure 1As shown, the computer device 100 includes a main processor 101 and an instruction execution unit 102. The main processor may be a central processing unit (CPU). The instruction execution unit 102 may be an application specific integrated circuit (ASIC) chip, and the instruction execution unit 102 may be used to execute instructions of a specific computing task to complete a specific computing task (for example, the computing task may be an operator to be executed). The instruction execution unit 102 may further include a microprocessor (MCU) and a computing subunit, and the MCU may directly read the instructions of the computing task from the memory and transmit them to the computing subunit, and the computing subunit is used to execute the corresponding instructions to complete the actual computing task; for example, taking the instruction execution unit 102 as a BM1690 chip, the BM1690 chip may include a microprocessor MCU and a computing subunit TPU (Tensor Processing Unit, a hardware accelerator specially optimized for machine learning tasks).

[0051] Furthermore, the computer device 100 may also include a memory 103. Specifically, the memory 103 may be a Flash chip, a read-only memory (ROM) disk, an optical disk, a USB flash drive, or a mobile hard disk, etc. The main processor 101, the instruction execution unit 102, and the memory 103 may be connected via a bus 104, such as an I2C (Inter-integrated Circuit) bus.

[0052] Those skilled in the art will understand that Figure 1 The structure shown in the figure is only a block diagram of a partial structure related to the embodiment of the present application, and does not constitute a limitation on the computer device to which the embodiment of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different arrangement of components.

[0053] The main processor 101 is used to run the computer program stored in the memory 103, and implement any one of the device instruction processing methods provided in the embodiments of the present application when executing the computer program. For example, the main processor 101 is used to run the computer program stored in the memory 103, and can implement the following steps when executing the computer program:

[0054] The main processor obtains a hash value of the operator to be executed according to the operator category of the operator to be executed and the required parameters of the operator to be executed; when the hash value of the operator to be executed exists in the pre-cache file of the main processor, the main processor obtains a first instruction string of the operator to be executed based on the pre-cache file, wherein the pre-cache file is used to pre-cache the instruction strings of each operator generated by the main processor; the main processor corrects the temporary address field included in the first instruction string to obtain a first corrected instruction string; the main processor sends the first corrected instruction string to the instruction execution unit, so that the instruction execution unit executes the instruction content included in the first corrected instruction string according to the corrected address field included in the first corrected instruction string.

[0055] It should be noted that those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the computer device described above can refer to the corresponding process in the following device instruction processing method embodiment, and will not be repeated here.

[0056] Please note: Figure 1 The scenarios are only used to explain the device instruction processing method provided in the embodiments of the present application, but do not constitute a limitation on the application scenarios of the device instruction processing method provided in the embodiments of the present application.

[0057] See also Figure 2 , Figure 2 201 to 204, wherein:

[0058] 201. The main processor obtains a hash value of the operator to be executed according to the operator category of the operator to be executed and the required parameters of the operator to be executed.

[0059] Among them, operator categories are specific operations or calculation types, such as convolution, pooling, or activation functions.

[0060] Among them, the operator to be executed can be set according to the actual business scenario requirements, for example, it can be a convolution operator, an activation operator, etc.

[0061] Each operator has specific parameters, and the required parameters of the operator to be executed are determined according to the operator category of the operator to be executed. For example, if the operator to be executed is a convolution operator, the required parameters of the operator to be executed (i.e., the convolution operator) include but are not limited to: convolution kernel size, stride, padding method, and number of input and output channels, etc. For another example, if the operator to be executed is an activation operator, the required parameters of the operator to be executed (i.e., the activation operator) include but are not limited to: the type of activation function (such as ReLU, Sigmoid), etc.

[0062] The operator to be executed refers to the operator currently to be executed.

[0063] The host processor (referred to as "Host end" in this embodiment) is the core processor of the computer device, which may be the central processing unit CPU of the computer device.

[0064] Among them, the instruction execution unit (referred to as "Device end" in this embodiment) is a unit used to execute instructions for specific computing tasks. Exemplarily, the instruction execution unit is a BM1690 chip.

[0065] Among them, the main processor (Host side) can load the operator information of the operator to be executed (such as operator type, input and output data type, data dimension, and required parameters of the operator) from external storage (such as hard disk, SSD), or obtain the operator information of the operator to be executed through sensors or other devices. The main processor (Host side) extracts information such as the operator category of the operator to be executed and the required parameters of the operator to be executed based on the operator information of the operator to be executed.

[0066] It can be understood that the instruction execution unit (Device end) can run the execution instruction string according to the PIO mode. When the instruction execution unit (Device end) runs according to the PIO mode, the instruction execution unit (Device end) completes the instruction configuration process, such as Figure 6 As shown in the figure, the instruction execution process of PIO mode operation is as follows: 1) The Host informs the Device of the memory space to be allocated in advance based on the input and output data size, and constructs parameters based on the operator category of the current computing task (that is, the operator information of the operator to be executed) to send to the Device. 2) After the Device receives the parameters, the microprocessor (such as MCU) in the Device parses the parameters and configures the computing subunit (such as TPU) instructions based on the results. Then, the microprocessor (such as MCU) sends the instructions to the computing subunit (such as TPU) on the Device for execution. Figure 6 As shown, Figure 6The length of time on the horizontal axis can represent the time required for the configuration and execution of the instructions of the corresponding functional module. When the length of the instruction to be configured is large (i.e., instruction), due to the relatively small computing power of the microprocessor (such as MCU) of the instruction execution unit (Device end) and the computing subunit (such as TPU) of the instruction execution unit (Device end), the instruction configuration time of the microprocessor (such as MCU) is greater than the time it takes for the instruction execution unit (Device end) to execute the previous instruction. Therefore, in this embodiment, an instruction pre-cache mechanism is adopted as follows:

[0067] ① The main processor (Host side) configures the instructions. Each time a computing task is received, the main processor (Host end) will complete the instruction configuration process for operator i of the computing task in advance. After the instruction string of operator i is configured, the instruction string of operator i of the main processor (Host end) is associated with the hash value of operator i and stored in the pre-cache file, thereby realizing the use of the main processor (Host end) to pre-cache the instruction string of operator i. Therefore, on the one hand, the instruction configuration process is transferred from the instruction execution unit (Device end) to the main processor (Host end). Since the main processor (Host end) has stronger computing power than the microprocessor of the instruction execution unit (Device end), the instruction configuration speed of the main processor (Host end) matches the instruction execution speed of the computing subunit of the instruction execution unit (Device end), thereby improving the instruction execution speed; avoiding the problem that the instruction configuration speed of the microprocessor of the instruction execution unit (Device end) is much lower than the instruction execution speed of the computing subunit of the instruction execution unit (Device end), thereby avoiding the problem that the computing subunit with high computing power of the instruction execution unit (Device end) cannot effectively improve the instruction execution speed due to the low instruction delivery speed. On the other hand, the main processor (Host end) can pre-cache the instruction string of operator i and add it to the pre-cache file, so as to pre-cache the instructions before the computing task is executed, thereby improving the instruction execution speed to a certain extent.

[0068] ② The instruction execution unit (Device side) executes the instructions configured by the main processor (Host side). Figure 3 When the computing task needs to be actually executed, for each operator i to be executed, first, the main processor (Host end) uses the hash algorithm to calculate according to the operator category of each operator i and the required parameters of each operator i to obtain the hash value of each operator i (refer to Figure 3 Then, the host processor (Host end) determines whether the hash value of operator i and the instruction string of operator i exist in the pre-cache file used to save the instruction (refer to Figure 3If the hash value of operator i and the instruction string of operator i exist in the pre-cache file, the main processor (Host end) reads the instruction string of operator i, and further sends the instruction string of operator i to the instruction execution unit (Device end) for execution (refer to Figure 3 "Load and deserialize the structure corresponding to the hash_key", "Configure the base address register", "Send the deserialized instruction string and address and other parameters to the Device" section); if the hash value of operator i and the instruction string of operator i do not exist in the pre-cache file, the main processor (Host side) first enters the instruction configuration process (for example, the instruction configuration process can refer to step 401) to complete the instruction configuration of operator i, and then enters the instruction string execution process. The specific implementation of the process of the main processor (Host side) generating instructions (i.e., the instruction configuration process) can refer to the relevant instructions below. For the sake of simplicity, it will not be repeated here. Among them, the hash algorithm may include but is not limited to MD5 (Message-Digest Algorithm 5), SHA-256 (Secure Hash Algorithm 256) SHA-1 (Secure Hash Algorithm 1).

[0069] 202. When the hash value of the operator to be executed exists in the pre-cache file of the main processor, the main processor obtains a first instruction string of the operator to be executed based on the pre-cache file.

[0070] The pre-cache file is used to pre-cache the instruction string of each operator generated by the main processor.

[0071] The first instruction string is an instruction string of an operator to be executed obtained based on the pre-cached file.

[0072] refer to Figure 3 In the "Load and deserialize the structure corresponding to the hash_key" part, similar to the instruction string storage method in step 403, there are multiple ways to obtain the first instruction string in step 202, illustratively including:

[0073] ① The instruction string is stored in a serialized format in the hard disk of the computer device. At this time, the pre-cache file is a hard disk pre-cache file, and the instruction string of each operator i can be pre-cached to the hard disk with reference to steps 4031A to 4032A (that is, the instruction string of each operator is added to the hard disk pre-cache file in a serialized format). At this time, the serialized instruction string in the pre-cache file needs to be deserialized, and step 202 may specifically include: the main processor loads the target serialized instruction string that matches the hash value of the operator to be executed from each serialized instruction string in the pre-cache file; the main processor deserializes the serialized instruction string to obtain a deserialized instruction string as the first instruction string of the operator to be executed.

[0074] ② The instruction string is stored in the memory of the computer device. At this time, the pre-cache file is a memory pre-cache file, and the instruction string of each operator i can be pre-cached into the memory with reference to step 4031B (that is, the instruction string of each operator is directly added to the memory pre-cache file). At this time, step 202 may specifically include: the main processor loads the instruction string that matches the hash value of the operator to be executed from each instruction string of the memory pre-cache file as the first instruction string of the operator to be executed.

[0075] 203. The main processor corrects the temporary address field included in the first instruction string to obtain a first corrected instruction string.

[0076] The first corrected instruction string is an instruction string of an operator to be executed obtained after correcting the temporary address field included in the first instruction string.

[0077] Among them, the cached instruction string may include instruction content (i.e., the operation code actually executed), address field, instruction type (such as the identification of long instructions or short instructions), bit length (byte length information of each instruction of the machine), and number of instructions (i.e., the number of instructions contained in the instruction string).

[0078] The address field is used to indicate the data memory address, including the memory address of the input data and the memory address of the output data. The address field includes two parts: the base register field (the base register field may include the base keyword base_addr_regs and the base value [tag]) and the offset field (the offset field may include the offset keyword offset and the offset value).

[0079] The base address keyword refers to a keyword used to represent a base address register.

[0080] The base address value refers to the specific value of the base address register.

[0081] The offset keyword is a keyword used to indicate an offset.

[0082] The offset value refers to a specific value of the offset. For example, the offset value is equal to a preset specified value (such as 0).

[0083] In the instruction string pre-cache stage, the offset value of the offset field is configured as 0, and the base address value [tag] of the base address register field is configured to start from 1 and increment backward in sequence. The temporary base address value [tag] of the base address register field is configured in this stage. In the actual execution stage of the instruction string, the actual data memory address calculation formula at runtime is shown in Formula 1:

[0084] real_mem_addr=base_addr_regs[tag]+offset Formula 1

[0085] In Formula 1, real_mem_addr represents the actual data memory address at runtime, base_addr_regs is a manually configurable base address register, the number of registers can be determined according to the device model, and each register can be configured with 64 bits of address information.

[0086] During the actual execution phase of the instruction string, since the memory of the input data and the memory of the output data are dynamically allocated, the base address value is modified to the input memory address and / or the output memory address (for example, the base address value of the base register field is modified from the temporary base address value [1] to the input memory address [0x1000], and the input memory address [0x1000] is the corrected base address value; for another example, the base address value of the base register field is modified from the temporary base address value [2] to the output memory address [0x20], and the output memory address [0x20] is the corrected base address value), so that the base address register of the input data is modified to the dynamically allocated input memory address, and the base address register of the output data is modified to the dynamically allocated output memory address. In this way, the base address register configuration unique to the instruction execution unit (Device end) can be used to simplify the implementation of instruction address information correction, so that the cached instruction can correct the address information when it is executed, ensuring that the instruction execution unit (Device end) can use the address information in the instruction to accurately read the input data from the input memory for processing and write the output data to the output memory.

[0087] refer to Figure 3In the "Configure Base Register" part, since the memory of the input data and the memory of the output data of the operator to be executed are dynamically allocated, when the instruction string of the operator to be executed is actually executed, it is necessary to modify the base register field, specifically, modify the base address value to the input memory address and / or the output memory address. At this time, step 203 may specifically include: the main processor determines the data memory address of the first instruction string; the main processor modifies the base register field in the first instruction string from the temporary base address value to the data memory address, and obtains the corrected base address value of the base register field; based on the corrected base address value of the base register field, obtains the first corrected instruction string.

[0088] For example, in some embodiments, taking the base address register configuration for input data as an example, at this time, the address field may include an input base address register field and an input offset field, and step 203 may specifically include: the main processor determines the input memory address of the first instruction string; the main processor modifies the base address value of the input base address register field in the first instruction data from a temporary base address value to the input memory address, and obtains a corrected base address value of the input base address register field; the main processor replaces the temporary value of the input base address register field in the first instruction data with the corrected base address value of the input base address register field, and obtains the first corrected instruction string containing the corrected address field.

[0089] For another example, in some embodiments, taking the configuration of the base address register for output data as an example, at this time, the address field may include an output base address register field and an output offset field, and step 203 may specifically include: the main processor determines the output memory address of the first instruction string; the main processor modifies the base address value of the output base address register in the first instruction data from a temporary base address value to the output memory address, and obtains a corrected base address value of the output base address register field; the main processor replaces the temporary value of the output base address register field in the first instruction data with the corrected base address value of the output base address register field, and obtains the first corrected instruction string containing the corrected address field.

[0090] For another example, in some embodiments, taking the case of performing base register configuration for input data and output data at the same time, at this time, the address field may include an input base register field, an input offset field, an output base register field and an output offset field, and step 203 may specifically include: the main processor determines the input memory address of the first instruction string; the main processor modifies the base address value of the input base register field in the first instruction data from a temporary base address value to the input memory address, and obtains a revised base address value of the input base register field; the main processor modifies the base address value of the output base register in the first instruction data from a temporary base address value to the output memory address; the main processor replaces the temporary value of the input base register field in the first instruction data with the revised base address value of the input base register field, and replaces the temporary value of the output base register field in the first instruction data with the revised base address value of the output base register field, and obtains a first revised instruction string containing a revised address field.

[0091] 204. The main processor sends the first revised instruction string to the instruction execution unit, so that the instruction execution unit executes the instruction content included in the first revised instruction string according to the revised address field included in the first revised instruction string.

[0092] The temporary address field refers to the address field of the instruction string of the operator to be executed that is configured in the instruction cache stage.

[0093] The corrected address field refers to the address field of the instruction string of the operator to be executed, which is obtained after the temporary address field of the operator to be executed is corrected during the instruction execution phase.

[0094] For ease of understanding, the following first introduces how the main processor (Host side) and the instruction execution unit (Device side) cooperate to complete the calculation process of the operator, as follows:

[0095] 1. The main processor (Host side) first allocates appropriate space for input data and output data locally. Secondly, the main processor (Host side) calls the memory allocation interface to start the allocation of input memory and output memory on the instruction execution unit (Device side) to allocate appropriate space for input data and output data on the instruction execution unit (Device side). In order to ensure that there is enough space to store input data and output data, the main processor (Host side) uses dynamic memory to allocate input memory and output memory. Among them, input memory is memory for storing input data, and output memory is memory for storing output data. Local input memory and local output memory can be used to store input data and output data stored by the main processor (Host side), respectively, and input memory and output memory on the instruction execution unit (Device side) can be used to store input data and output data on the instruction execution unit (Device side), respectively.

[0096] 2. The main processor (Host side) prepares the input data of operator i. The input data of operator i can be loaded from external storage (such as hard disk, SSD), or obtained through sensors or other devices.

[0097] 3. The main processor (Host end) generates the instruction data of operator i and adds it to the pre-cache file. In some embodiments, the instruction data may be a serialized instruction string, and the instruction data is stored in the hardware pre-cache file (i.e., the instruction string is serialized and stored in the hard disk). In some embodiments, the instruction data may be an instruction string in a directly operable format, and the instruction data is directly stored in the memory pre-cache file (i.e., the instruction string is directly stored in the memory).

[0098] 4. The main processor (Host side) adds the input data to the input memory on the instruction execution unit (Device side) to ensure that the instruction execution unit (Device side) can read the input data from the input memory according to the address field in the instruction string.

[0099] 5. The instruction execution unit (Device side) executes the instruction. After the host processor (Host side) sends the instruction string to the instruction execution unit (Device side), the instruction execution unit (Device side) can read the input data from the input memory on the instruction execution unit (Device side) according to the address field in the instruction string, and execute the instruction content in the instruction string according to the input data of operator i to obtain the output data of operator i.

[0100] 5. The instruction execution unit (Device side) can store the output data of operator i into the output memory according to the address field in the instruction string.

[0101] 6. The host processor (Host side) reads back the output data of operator i from the output memory on the instruction execution unit (Device side).

[0102] Exemplarily, it can be seen that after the main processor (Host end) sends the first instruction string to the instruction execution unit (Device end), the instruction execution unit (Device end) can determine the input memory address and the output memory address according to the corrected address field in the first instruction string, and read the input data of the operator to be executed from the input memory on the instruction execution unit (Device end) according to the input memory address; then, the instruction execution unit (Device end) executes the instruction content contained in the first instruction string according to the input data of the operator to be executed to obtain the output data of the operator to be executed, and writes the output data into the output memory on the instruction execution unit (Device end) according to the output memory address. Finally, the main processor (Host end) reads back the output data of the operator to be executed from the output memory on the instruction execution unit (Device end).

[0103] Please refer to Figure 3 When the hash value of the operator to be executed and the instruction string of the operator to be executed do not exist in the pre-cache file, the main processor (Host end) first enters the instruction configuration process (for example, the instruction configuration process can refer to step 401) to complete the instruction configuration of the operator to be executed, and then enters the instruction string execution process. Please refer to Figure 5 , that is, the device instruction processing method further includes the following steps 205 to 207:

[0104] 205. When the hash value of the operator to be executed does not exist in the pre-cache file of the main processor, the main processor generates a second instruction string of the operator to be executed according to the operator information of the operator to be executed.

[0105] The second instruction string is an instruction string of the operator to be executed that is generated in real time when the instruction string of the operator to be executed does not exist in the pre-cache file.

[0106] In some embodiments, the main processor (Host end) generates an instruction string and directly puts it into the memory for execution by the instruction execution unit (Device end). At this time, first, similar to steps 4011 to 4013, the main processor configures the instruction simulation calculation function according to the preset instruction configuration information, wherein the instruction configuration information includes at least one of the instruction content position, instruction length position, and instruction quantity position of each operator category; the main processor performs address configuration processing on the operator to be executed to obtain the temporary address field of the operator to be executed; the main processor generates the instruction string of the operator to be executed according to the operator information of the operator to be executed and the temporary address field of the operator to be executed through the instruction simulation calculation function. Then, the instruction string generated for the operator to be executed is directly used as the instruction string of the operator to be executed.

[0107] In some embodiments, the main processor (Host end) generates an instruction string, serializes it, puts it into the hard disk, and then loads and deserializes it for execution by the instruction execution unit (Device end). At this time, first, similar to steps 4011 to 4013, the main processor configures the instruction simulation calculation function according to the preset instruction configuration information, wherein the instruction configuration information includes at least one of the instruction content position, instruction length position, and instruction quantity position of each operator category; the main processor performs address configuration processing on the operator to be executed to obtain the temporary address field of the operator to be executed; the main processor generates the instruction string of the operator to be executed according to the operator information of the operator to be executed and the temporary address field of the operator to be executed through the instruction simulation calculation function. Then, the main processor serializes the instruction string of the operator to be executed to obtain the serialized instruction string of the operator to be executed; the main processor associates the serialized instruction string of the operator to be executed and the hash value of the operator to be executed and adds it to the hard disk pre-cache file of the computer device. Finally, the main processor loads the target serialized instruction string that matches the hash value of the operator to be executed from each serialized instruction string of the pre-cache file; the main processor deserializes the serialized instruction string to obtain a deserialized instruction string as the second instruction string of the operator to be executed.

[0108] 206. The main processor corrects the temporary address field included in the second instruction string to obtain a second corrected instruction string.

[0109] The second corrected instruction string is an instruction string of the operator to be executed obtained after correcting the temporary address field included in the second instruction string.

[0110] 207. The main processor sends the second revised instruction string to the instruction execution unit, so that the instruction execution unit executes the instruction content included in the second revised instruction string according to the revised address field included in the second revised instruction string.

[0111] The implementation of steps 206 to 207 is similar to that of steps 203 to 204. For details, please refer to the relevant descriptions above and will not be repeated here.

[0112] For ease of understanding, the instruction pre-caching process of the host processor (Host side) is first introduced below. In some embodiments, such as Figure 4 As shown, the instruction pre-caching process of the main processor (Host end) may include the following steps 401 to 403:

[0113] 401. The main processor generates an instruction string of the operator to be executed according to the operator information of the operator to be executed.

[0114] Exemplarily, the instruction configuration process of the main processor (Host end) in step 401 may specifically include the following steps 4011 to 4013:

[0115] 4011. The main processor configures the instruction simulation computing function according to preset instruction configuration information.

[0116] The instruction configuration information includes at least one of the instruction content location, instruction length location, and instruction quantity location of each operator category. The preset instruction configuration information is used to instruct the instruction execution unit (Device end) to save the location of each category of instruction content, the location of each category of instruction byte length, and the location of each category of instruction quantity when configuring instructions.

[0117] refer to Figure 3 In the "Simulation Calculation Function Configuration" section, exemplarily, in this step, it is necessary to configure the instruction simulation calculation function according to the preset instruction configuration information such as the location where the content of each category of instructions is saved, the location where the byte length of each category of instructions is saved, and the location where the number of each category of instructions is saved when the instruction execution unit (Device end) runs in the PIO mode. Through the instruction simulation calculation function, the instruction string can be automatically generated according to the configuration parameters, so that the generated instruction string can be verified by simulation whether it meets the expectations, ensuring that the instruction string can be correctly executed at runtime.

[0118] 4012. The main processor performs address configuration processing on the operator to be executed to obtain a temporary address field of the operator to be executed.

[0119] refer to Figure 3In the "Configure temporary address parameters" section, similar to the instruction string pre-cache stage, the offset value of the offset field is configured to 0, and the base address value [tag] of the base address register field is configured to increase sequentially from 1. At this time, the temporary base address value [tag] of the base address register field is configured.

[0120] 4013. The main processor generates an instruction string of the operator to be executed according to the operator information of the operator to be executed and the temporary address field of the operator to be executed through the instruction simulation calculation function.

[0121] 402. The main processor obtains a hash value of the operator to be executed according to the operator category of the operator to be executed and the required parameters of the operator to be executed.

[0122] In some embodiments, the MD5 algorithm can be used to calculate the hash value of the operator to be executed, and the calculation process of the hash value of the operator to be executed can be as follows: first, according to a preset combination strategy, the operator category of the operator to be executed and the required parameters of the operator to be executed are combined into a string; then, this string is converted into a byte format; then, the MD5 algorithm is used to perform processing such as initialization, padding, block processing, loop operation, etc. on the byte format string to finally obtain the hash value of the operator to be executed.

[0123] In some embodiments, the SHA-256 algorithm can be used to calculate the hash value of the operator to be executed, and the calculation process of the hash value of the operator to be executed can be as follows: first, according to a preset combination strategy, the operator category of the operator to be executed and the required parameters of the operator to be executed are combined into a string; then, this string is converted into a byte format; then, the SHA-256 algorithm is used to perform processing on the byte format string such as initialization, padding, block processing, loop operation, etc., and finally the hash value of the operator to be executed is obtained.

[0124] 403. The main processor associates the instruction string of the operator to be executed and the hash value of the operator to be executed and adds them to the pre-cache file.

[0125] There are many ways to implement step 403, which include, for example:

[0126] ① The instruction string is stored in a serialized format in the hard disk of the computer device. At this time, the pre-cache file is a hard disk pre-cache file, and step 403 specifically includes the following steps 4031A to 4032A:

[0127] 4031A. The main processor serializes the instruction string of the operator to be executed to obtain a serialized instruction string of the operator to be executed.

[0128] 4032A. The main processor associates the serialized instruction string of the operator to be executed and the hash value of the operator to be executed and adds them to the hard disk pre-cache file of the computer device.

[0129] refer to Figure 3 In the "Generate instruction string and serialize" part, for example, after the instruction string of the operator to be executed is generated in step 401, first, the instruction string of the operator to be executed is converted into a format suitable for transmission or storage, such as JSON format, XML format, etc. The instruction string of the operator to be executed after the format conversion is the serialized instruction string of the operator to be executed, and the serialization processing of the instruction string of the operator to be executed is completed, so that the saved data structure can retain the integrity and readability of the instruction. Then, the serialized instruction string of the operator to be executed and the hash value of the operator to be executed are associated and added to the hard disk pre-cache file of the computer device, so that the subsequent operator to be executed can actually be executed, and the serialized instruction string of the operator to be executed can be loaded from the hard disk pre-cache file and deserialized before execution.

[0130] ② The instruction string is stored in the memory of the computer device. At this time, the pre-cache file is a memory pre-cache file, and step 403 specifically includes the following step 4031B:

[0131] 4031B. The main processor associates the instruction string of the operator to be executed and the hash value of the operator to be executed and adds them to the memory pre-cache file of the computer device.

[0132] From the above content, it can be seen that when the instruction execution unit is to actually execute the instruction, the hash value of the operator to be executed is obtained according to the operator category of the operator to be executed and the required parameters of the operator to be executed, and the first instruction string of the operator to be executed is read from the pre-cache file. On the one hand, since the main processor of the computer device can be used to complete the instruction configuration, there is no need to configure the instruction in the instruction execution unit, and the computing power of the main processor is relatively good, the configuration instruction time can be reduced, thereby avoiding the problem that the instruction configuration time of the instruction execution unit is longer than the instruction execution time, giving full play to the high computing power performance of the instruction execution unit, and improving the instruction execution rate. On the other hand, since the instruction string of each operator can be pre-configured and cached in the pre-cache file, when the hash value of the operator to be executed exists in the pre-cache file of the main processor, that is, when the instruction string of the operator to be executed exists in the pre-cache file, the pre-cached instruction string can be directly read for execution without the need to configure the instruction in real time, which can also improve the instruction processing efficiency of the computer device to a certain extent. On the third aspect, after the main processor corrects the temporary address field contained in the first instruction string to obtain the first corrected instruction string, the first corrected instruction string is sent to the instruction execution unit for execution, and the address information in the execution string can be corrected to: the memory address of the input data and the memory address of the output data dynamically allocated for the operator to be executed, ensuring that the instruction execution unit (Device end) can use the address information in the instruction to accurately read the input data from the input memory for processing and write the output data to the output memory. On the fourth aspect, since the entire instruction string buffering and instruction string loading process is transparent to the external device user, all instruction string caching, loading and deletion management can be completed within the interface, realizing the flexibility of the original PIO mode execution instruction. On the fifth aspect, since the instruction string is cached, it can be easily used by the simulator, etc., and the computer device can complete the instruction configuration without sending the instruction configuration task to other devices, and can realize the instruction configuration and execution in an offline manner, so that new debugging methods can be added to improve the adjustability.

[0133] A person of ordinary skill in the art can understand that all or part of the steps in the above-mentioned device instruction processing method can be completed by instructions, or by controlling related hardware through instructions. The instructions can be stored in a computer-readable storage medium and loaded and executed by a processor.

[0134] To this end, an embodiment of the present application provides a computer-readable storage medium, in which multiple computer programs are stored, and the computer program can be loaded by a processor to execute any device instruction processing method provided in the embodiment of the present application. For example, the computer program can be loaded by a processor to execute the following steps:

[0135] The main processor obtains a hash value of the operator to be executed according to the operator category of the operator to be executed and the required parameters of the operator to be executed; when the hash value of the operator to be executed exists in the pre-cache file of the main processor, the main processor obtains a first instruction string of the operator to be executed based on the pre-cache file, wherein the pre-cache file is used to pre-cache the instruction strings of each operator generated by the main processor; the main processor corrects the temporary address field included in the first instruction string to obtain a first corrected instruction string; the main processor sends the first corrected instruction string to the instruction execution unit, so that the instruction execution unit executes the instruction content included in the first corrected instruction string according to the corrected address field included in the first corrected instruction string.

[0136] The computer-readable storage medium may include: a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0137] In the above-mentioned device instruction processing method, computer-readable storage medium, and computer device embodiments, the description of each embodiment has its own emphasis. For parts not described in detail in a certain embodiment, reference can be made to the relevant description of other embodiments. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working process and beneficial effects of the above-mentioned computer-readable storage medium, computer device and its corresponding units can refer to the description of the device instruction processing method in the above embodiment, and will not be repeated here.

[0138] The above is a detailed introduction to a device instruction processing method, a computer device and a computer-readable storage medium provided in an embodiment of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A device instruction processing method, characterized in that: Applied to a computer device, the computer device includes a main processor and an instruction execution unit, and the method includes: The main processor obtains a hash value of the operator to be executed according to the operator category of the operator to be executed and the required parameters of the operator to be executed; When the hash value of the operator to be executed exists in the pre-cache file of the main processor, the main processor obtains the first instruction string of the operator to be executed based on the pre-cache file, wherein the pre-cache file is used to pre-cache the instruction string of each operator generated by the main processor; The main processor performs correction processing on the temporary address field included in the first instruction string to obtain a first corrected instruction string; The main processor sends the first revised instruction string to the instruction execution unit, so that the instruction execution unit executes the instruction content included in the first revised instruction string according to the revised address field included in the first revised instruction string.

2. The device instruction processing method according to claim 1, characterized in that: The method further comprises: The main processor generates an instruction string of the operator to be executed according to the operator information of the operator to be executed; The main processor obtains the hash value of the operator to be executed according to the operator category of the operator to be executed and the required parameters of the operator to be executed; The main processor associates the instruction string of the operator to be executed and the hash value of the operator to be executed and adds them to the pre-cache file.

3. The device instruction processing method according to claim 2, characterized in that: The main processor generates an instruction string of the operator to be executed according to the operator information of the operator to be executed, including: The main processor configures the instruction simulation computing function according to preset instruction configuration information, wherein the instruction configuration information includes at least one of the instruction content position, instruction length position, and instruction quantity position of each operator category; The main processor performs address configuration processing on the operator to be executed to obtain a temporary address field of the operator to be executed; The main processor generates an instruction string of the operator to be executed according to the operator information of the operator to be executed and the temporary address field of the operator to be executed through the instruction simulation calculation function.

4. The device instruction processing method according to claim 2, characterized in that: The main processor associates the instruction string of the to-be-executed operator with the hash value of the to-be-executed operator and adds it to the pre-cache file, including: The main processor performs serialization processing on the instruction string of the operator to be executed to obtain a serialized instruction string of the operator to be executed; The main processor associates the serialized instruction string of the operator to be executed and the hash value of the operator to be executed and adds them to the hard disk pre-cache file of the computer device.

5. The device instruction processing method according to claim 4, characterized in that: The main processor obtains the first instruction string of the operator to be executed based on the pre-cache file, including: The main processor loads a target serialized instruction string matching the hash value of the operator to be executed from each serialized instruction string of the pre-cache file; The main processor deserializes the serialized instruction string to obtain a deserialized instruction string as the first instruction string of the operator to be executed.

6. The device instruction processing method according to claim 1, characterized in that: The address field includes a base address register field and an offset field, and the base address register field includes a base address keyword and a base address value; The main processor performs correction processing on the temporary address field included in the first instruction string to obtain a first corrected instruction string, including: The main processor determines a data memory address of the first instruction string; The main processor modifies the base address register field in the first instruction string from a temporary base address value to the data memory address, and obtains a modified base address value of the base address register field; A first modified instruction string is obtained based on the modified base address value of the base address register field.

7. The device instruction processing method according to claim 1, characterized in that: The method further comprises: When the hash value of the operator to be executed does not exist in the pre-cache file of the main processor, the main processor generates a second instruction string of the operator to be executed according to the operator information of the operator to be executed; The main processor performs correction processing on the temporary address field included in the second instruction string to obtain a second corrected instruction string; The main processor sends the second revised instruction string to the instruction execution unit, so that the instruction execution unit executes the instruction content included in the second revised instruction string according to the revised address field included in the second revised instruction string.

8. The device instruction processing method according to claim 1, characterized in that: The corrected address field includes a corrected base address value and an offset value, the offset value is equal to a preset specified value, and the corrected base address value and the offset value are used by the instruction execution unit to determine the input memory address and output memory address of the operator to be executed.

9. A computer device, characterized in that: The method comprises a processor and a memory, wherein a computer program is stored in the memory, and when the processor calls the computer program in the memory, the method for processing device instructions according to any one of claims 1 to 8 is executed.

10. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and the computer program is loaded by a processor to execute the device instruction processing method according to any one of claims 1 to 8.

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