Method for expanding RISC-V instruction set containing post format instruction and RISC-V processor

Abstract

The invention provides a method for expanding an RISC-V instruction set containing a post format instruction. The method comprises the following steps: modifying the RISC-V instruction set to enable the RISC-V instruction set to support the post format instruction; the RISC-V instruction set modification comprises modification of an operation code and use of a specific operation code as an identifier of a position format instruction; using a funct3 field code, a funct5 field code or a functp field code to distinguish the specific type of the instruction in the position format; respectively representing the address of a source operand 1, the address of a source operand 2 and the address of a destination register by using rs1, rs2 and rd field codes; the invention further provides an RISC-V processor which is used for executing the RISC-V instruction set generated by the method for expanding the RISC-V instruction set containing the post-format instruction, and the target operand exponential bit width of the post-format instruction is selected by using the es field coding. The invention further provides the RISC-V processor which is used for executing the RISC-V instruction set generated by the method for expanding the RISC-V instruction set containing the post-format instruction.

Description

Technical Field

[0001] The present invention belongs to the technical field of RISC-V instruction set architecture, and in particular to a RISC-V instruction set expansion method including POSIT format instructions and a RISC-V processor. Background Art

[0002] As an interface for software and hardware to interact, the instruction set architecture (ISA) plays the role of a bridge connecting the two worlds and has a fundamental impact on the performance of computer systems. It not only defines the rules for the processor to perform operations, but is also directly related to the efficiency of the algorithm and the utilization efficiency of hardware resources. In particular, by customizing specific application instruction sets, it is possible to optimize the operation process for professional fields such as image processing, reduce unnecessary calculation steps, and improve processing speed and efficiency.

[0003] RISC-V, as a modern, open-source reduced instruction set architecture, has become an ideal platform for innovation with its modular and highly scalable design. It not only integrates the successful elements of previous ISAs, but also avoids historical problems, provides basic instruction sets (such as RV32I and RV64I serving 32-bit and 64-bit environments) and a variety of extended instruction sets (covering multiplication and division, atomic operations, floating-point operations, compressed instructions, etc.), and reserves space for custom instructions, greatly enhancing its ability to adapt to different application scenarios.

[0004] The Posit format is a more flexible and precise numerical representation method than the traditional IEEE 754 floating-point number. It has become an emerging choice in the field of embedded systems and low-power computing due to its higher numerical density, smaller rounding error, and wider dynamic range. In particular, the Posit format has shown significant advantages in resource-constrained scenarios, such as IoT devices, signal processing, and machine learning reasoning. Since the existing mainstream processor architecture is usually optimized for the IEEE 754 format, the hardware support for the Posit format is not yet perfect.

[0005] At the same time, the CORDIC (Coordinate Rotation Digital Computer) algorithm is an iterative algorithm suitable for transcendental function calculations (such as trigonometric functions, logarithms, exponentials) and complex operations such as square roots. Its high efficiency and hardware friendliness make it one of the main methods for embedded processors to implement transcendental functions. Traditional CORDIC algorithms are mostly based on the IEEE754 floating-point format, and expanding it to support the calculation requirements of the Posit format requires redesigning the data path and operation mechanism, which is not suitable for application.

[0006] Therefore, it is necessary to develop a method for extending the Posit format transcendental function and data conversion instruction set based on the RISC-V instruction set so that embedded processors can support Posit format calculations. Summary of the invention

[0007] The present invention provides a RISC-V instruction set expansion method including POSIT format instructions and a RISC-V processor. Through custom instruction expansion, the Posit format number representation is combined with the CORDIC algorithm, which can not only realize efficient transcendental function calculation, but also support efficient data conversion between IEEE 754 floating-point numbers and Posit format numbers.

[0008] Other purposes and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0009] To achieve one or part or all of the above purposes or other purposes, a technical solution of the present invention provides a RISC-V instruction set expansion method including posit format instructions, including modifying the RISC-V instruction set so that the RISC-V instruction set supports posit format instructions; the RISC-V instruction set modification includes modifying the opcode, using a specific opcode as an identifier of the posit format instruction; using funct3 field encoding, funct5 field encoding or functp field encoding to distinguish the specific type of the posit format instruction; using rs1, rs2, rd field encoding to represent the address of source operand 1, the address of source operand 2 and the destination register address respectively; using es field encoding to select the destination operand exponent bit width of the posit format instruction.

[0010] Use the custom-0 encoding field reserved by the RISC-V instruction set as the opcode of the posit format instruction.

[0011] The es field is encoded as a 25-26 bit field of the RISC-V instruction encoding.

[0012] The types of posit format instructions include: posit format number conversion instructions, posit format number load and store instructions, and posit transcendental function instructions; the posit format number conversion instructions are distinguished by funct3 field encoding, or the funct3 field encoding is distinguished by the functp field encoding; the posit format number load and store instructions use the RISC-V instruction set single-precision load and store instruction encoding format, and the opcode of the RISC-V instruction set single-precision load and store instruction encoding format is replaced with a posit format instruction opcode; the posit transcendental function instructions are distinguished by the funct5 field encoding.

[0013] The funct3 field code is used to distinguish instructions for converting Posit format numbers to single-precision floating point numbers, Posit format numbers to integer data, integer data to Posit format numbers, and single-precision floating point numbers to Posit format numbers. The funct3 field code and the functp field code are used together to distinguish instructions for converting Posit format numbers to each other.

[0014] The instruction encoding for converting between Posit format numbers also includes es-rs and es-rd field encodings, which respectively represent the exponent field bit widths of the source operand and the destination operand; the es-rd field encoding is the 25-26 bit field of the RISC-V instruction encoding, and the es-rs field encoding is the 27-28 bit field of the RISC-V instruction encoding.

[0015] If the es-rd field code and the es-rs field code of the Posit format number conversion instruction are the same, there is no need to perform Posit format number conversion; if the es-rd field code and the es-rs field code of the Posit format number conversion instruction are different, the Posit format number conversion is performed according to the es-rd field.

[0016] After the Posit format instruction is encoded, the compiler's riscv-opcodes is modified so that the Posit format instruction can be recognized by the compiler, and a machine code containing the Posit format is generated for the processor to execute.

[0017] The funct3 field encoding of the posit format number conversion instruction and the funct5 field encoding of the posit transcendental function instruction are both written in Gray code; the funct5 field encoding of the posit format number conversion instruction and the funct3 field encoding of the posit transcendental function instruction are both 0.

[0018] Another technical solution of the present invention provides a RISC-V processor, which is used to execute a RISC-V instruction set generated by a RISC-V instruction set expansion method including posit format instructions as described above, wherein the RISC-V processor at least includes a decoding module, an execution module and a register stack, wherein the decoding module customizes a posit format instruction decoding data path for decoding posit format instructions; the execution module includes a posit format number execution unit, and the posit format number execution unit includes a posit processing unit and a CORDIC unit; the register stack includes a posit format number register; the decoding module parses the Posit format instruction to generate a function control logic signal, and fetches the Posit format number from the posit format number register to the execution module according to the control logic signal; the posit format number conversion unit in the posit processing unit is used to perform type conversion of the posit format number; and the CORDIC unit performs different transcendental function operations on the input posit format number.

[0019] The posit format number execution unit also includes the Posit decoder and the Posit encoder; the posit processing unit and the CORDIC unit share the same Posit decoder and Posit encoder; the Posit decoder decomposes the input Posit format number into an exponent, a mantissa and a sign bit; the posit processing unit and the CORDIC unit respectively receive the output results of the Posit decoder; the calculation results of the posit processing unit and the CORDIC unit are selected by the multiplexer and output to the Posit encoder, and the Posit encoder converts the calculated exponent, mantissa and sign bit into a posit format number; the multiplexer, the posit processing unit and the CORDIC unit are all controlled by two different enable signals.

[0020] The CORDIC unit includes two Posit multiplication and addition units, a Posit multiplication unit, a Posit addition unit and a storage unit for iterative calculation of the CORDIC algorithm; the storage unit stores angle, State factor and The scaling factor is called incrementally during the calculation process.

[0021] The Posit multiplication unit is a configurable Posit multiplication unit, which selects Posit multipliers with different bit widths according to different bit width parameter selection signals; the multiplier bit widths of the configurable Posit multiplication unit include: 8×8 bits, 16×8 bits, 32×8 bits, 16×16 bits, 32×16 bits and 32×32 bits.

[0022] Compared with the prior art, the beneficial effects of the present invention mainly include: 1. Posit format number transcendental function instructions and Posit format number type conversion instructions are added to the RISC-V instruction set architecture, filling the vacancy of the Posit format transcendental function instruction set, and at the same time providing instructions for converting Posit numbers to other types of data and conversion instructions for Posit format numbers of different precisions. The designed instructions are comprehensive and concise, which is beneficial to the subsequent supplement of Posit format instructions.

[0023] 2. The Posit CORDIC instruction set of the present invention greatly compresses the number of instructions of the Posit transcendental function; the designed instructions are encoded using Gray code to improve the reliability of data transmission; when designing custom instruction encoding, more bits of the funct5 field and the funct3 field are kept at a low level to the greatest extent, thereby reducing circuit power consumption.

[0024] 3. Through the unique encoding form, the Posit number can select the exponent in a small range, increase the flexibility of the accuracy and range of data operations, and enhance the flexibility and versatility of multiple precision calculations. Compared with the basic RISC-V floating-point instruction set, the Posit format instruction designed by the present invention can change the data accuracy without changing the RISC-V instruction set, greatly improving the accuracy and flexibility of the processor data operation.

[0025] 4. The posit processing unit and the CORDIC unit share the posit encoder, posit decoder, and some multiplication and addition units to reduce processor resource overhead; at the same time, a configurable multiplication unit with multi-bit broadband enable is used to reasonably use multipliers of different bits according to the mantissa of the posit format number, greatly reducing circuit power consumption.

[0026] In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0028] Figure 1 This is the Posit number format used in the present invention.

[0029] Figure 2 This is a basic architecture diagram of the RISC-V processor used in the present invention.

[0030] Figure 3 A Posit format number type conversion and transcendental function instruction encoding format customized for the present invention.

[0031] Figure 4 This is the encoding format of the Posit format number conversion instruction of the present invention.

[0032] Figure 5 This is the Posit format number loading instruction encoding format of the present invention.

[0033] Figure 6 This is the Posit format number storage instruction encoding format of the present invention.

[0034] Figure 7 The invention provides a custom instruction encoding for the Posit format number type conversion instruction, the load and store instruction, and the transcendental function instruction.

[0035] Figure 8 It is a basic architecture diagram of the Posit format number conversion unit and the Posit CORDIC unit of the present invention.

[0036] Fig. 9 FIG. 4 is a basic architecture diagram of the Posit CORDIC unit of the present invention.

[0037] Fig.10 It is a schematic diagram of the Posit configurable multiplication unit of the present invention. DETAILED DESCRIPTION

[0038] The above and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front or back, etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and not to limit the present invention.

[0039] Example 1 Embodiment 1 provides a RISC-V instruction set expansion method including posit format instructions, characterized in that it includes modifying the RISC-V instruction set so that the RISC-V instruction set supports posit format instructions; the RISC-V instruction set modification includes modifying the opcode, using a specific opcode as an identifier of the posit format instruction; using funct3 field encoding, funct5 field encoding or functp field encoding to distinguish the specific type of the posit format instruction; using rs1, rs2, rd field encodings to represent the address of source operand 1, the address of source operand 2 and the destination register address respectively; and using es field encoding to select the destination operand exponent bit width of the posit format instruction.

[0040] The technical solution in Example 1 is explained in detail below with reference to the accompanying drawings.

[0041] Embodiment 1 provides a RISC-V instruction set expansion method including POSIT format instructions. Based on the basic architecture of the RISC-V instruction set, the RISC-V instruction set is modified to support POSIT format number type conversion instructions, POSIT format number load and store instructions, and POSIT format transcendental function instructions.

[0042] like Figure 1 The figure shows the specific representation of a 32-bit (0-31) Posit format number. The s field indicates the positive or negative value of the Posit format number. The regime field is the scale bit, indicating the dynamic range of the exponent. The exponent field indicates the exponent. The fraction field indicates the mantissa.

[0043] Embodiment 1 When designing an instruction set for Posit format numbers, according to the existing framework of RISC-V and in combination with the usual floating-point instruction set design structure, the existing RISC-V instruction set architecture is modified to make it compatible with Posit format instructions.

[0044] The modifications include: 1. Modify the RISC-V instruction set opcode (i.e. Figure 3 1. Use the opcode code in the POSIT format to identify instructions in this format. 2. Use funct5, funct3, and functp to identify specific instruction types. 3. Use rs1, rs2, and rd as the source operand register number 1 address, source operand register number 2 address, and destination register address, respectively. 4. Add the es field to select the exponent bit width of the POSIT format number.

[0045] 1. Modify the RISC-V instruction set opcode Use the custom-0 encoding field reserved by the RISC-V instruction set as the opcode for the posit format instruction (i.e. Figure 3 The opcode code in ). Posit format instructions are not included in the RISC-V basic instruction set, so the space prepared for custom instruction sets in the RISC-V instruction set is used, and the custom-0 field is used for the Posit format custom instruction set encoding design (custom-0 field is used as the opcode). This does not affect the decoding path of the floating-point instruction set, and makes the decoding of Posit format instructions more convenient, and can be designed in a unified way, so that the Posit format hardware modules can be configured separately, which conforms to the advantages of modular configuration of the RISC-V instruction set.

[0046] 2. Use funct5, funct3, and functp to identify specific instruction types The types of POSIT format instructions include: POSIT format number conversion instructions, POSIT format number load and store instructions, and POSIT transcendental function instructions.

[0047] 2.1、posit format number conversion instruction The posit format number conversion instructions include the posit format number to single-precision floating point number instruction, the posit format number to integer data instruction, the integer data to posit format number instruction, the single-precision floating point number to posit format number instruction, and the posit format number conversion instructions. The posit format number conversion instructions are distinguished by the funct3 field code, or the funct3 field code and the functp field code are combined to distinguish.

[0048] Figure 3 It is a general posit format number conversion instruction, which is distinguished by the funct3 field encoding and includes the posit format number to single-precision floating point number instruction Pcvt.sp ( Figure 7 Visible), Posit format number to integer data instruction Pcvt.wp, integer data to Posit format number instruction Pcvt.pw and single-precision floating point number to Posit format number instruction Pcvt.ps.

[0049] Figure 4 The Pcvt.pp encoding format is for the posit format number conversion instruction. The posit format number conversion instruction is used to convert data of different precisions in the posit format. The Pcvt.pp instruction is identified by combining the functp field encoding and the funct3 field encoding. Figure 4The instruction encoding for converting posit format numbers includes es-rd field encoding and es-rs field encoding, which respectively represent the exponent bit width of the destination operand and the source operand. If the es-rd field encoding and the es-rs field encoding are the same, and the exponent bits of the source operand and the destination operand are the same, no conversion is required. If the bit widths are different, data format conversion is required according to the specific es-rd field encoding. The specific conversion is performed by the hardware circuit, and only the improvement of the instruction set architecture is introduced here.

[0050] 2.2、posit format number load and store instructions See also Figure 5 as well as Figure 6 , the posit format load and store instructions use the RISC-V instruction set single-precision load and store instruction encoding format (the existing instruction type in the RISC-V instruction set architecture), and replace the RISC-V instruction set single-precision load and store instruction encoding format operation code (opcode code) with the posit format instruction operation code (that is, the custom-0 encoding field), so that the instruction fetch stage can determine that the load and store instructions are used for posit format numbers based on the operation code type. See Figure 7 , posit format number load instruction Plw, loads a posit data value from the data storage area to the posit format number register. The posit format number store instruction Psw, stores a posit value in the posit register to the data storage area.

[0051] 2.3、posit transcendental function instruction The posit transcendental function instruction is distinguished by the funct5 field encoding, see Figure 7 , the posit transcendental function instruction types are Psin, Pcos, Ptan, Partan, Psinh, Pcosh, Ptanh, Partanh, Pexp, and Pln.

[0052] Combination Figure 7 Except for the load and store instructions, all other instructions are single-operand instructions, so the source operand 2 (rs2) is 0.

[0053] The funct3 field of the Posit format number conversion instruction is written in Gray code, and the funct5 field of the Posit format number transcendental function instruction is written in Gray code, which greatly improves the stability of the circuit and reduces the probability of misdecoding. At the same time, the funct5 field of the Posit format number conversion instruction and the funct3 field of the transcendental function instruction are all 0, which reduces the flip frequency when the circuit is working. This method greatly improves the reliability of processor decoding and reduces the power consumption of the processor when it is running.

[0054] 3. Use rs1, rs2 and rd as the source operand register number 1 address, source operand register number 2 address and destination register address respectively. When the RISC-V processor processes the posit format instruction, the decoding module generates the corresponding control signal, and reads the operand from the register according to the register addresses rs1 and rs2, and the destination register receives the operation result according to the rd address.

[0055] 4. Add es fields In the 32-bit instruction field encoding, bits [26:25] are used as the es field to make the exponent width of the Posit format number optional, greatly increasing the flexibility and selectivity of the precision and range during data operations. Its dynamic range characteristics can effectively cover values ​​from very small to very large, which is wider in representation range than traditional RISC-V floating-point instructions. Since there is no NaN (abbreviation for "Not a Number", a special value in the IEEE 754 floating-point standard) in the Posit format number, the processing complexity and error propagation are reduced, which can greatly improve the computing performance, resource efficiency and credibility of the results in edge computing and approximate computing scenarios.

[0056] After encoding the Posit format instructions, the compiler's riscv-opcodes are modified to make them recognizable by the compiler, and then machine code containing the Posit format instructions is generated to improve the accuracy and flexibility of data operations. The addition of Posit transcendental instructions reduces the number of instructions for ordinary Posit instructions to execute transcendental functions, thereby improving computing efficiency.

[0057] Example 2 Embodiment 2 provides a RISC-V processor for executing a RISC-V instruction set generated by a RISC-V instruction set expansion method including posit format instructions in embodiment 1, wherein the RISC-V processor comprises at least a decoding module, an execution module, and a register stack, wherein the decoding module defines a posit format instruction decoding data path for decoding posit format instructions; the execution module comprises a posit format number execution unit, and the posit format number execution unit comprises a posit processing unit (Posit Processing Unit, PPU for short, i.e. Figure 2 The PPU module in the PPU module) and the CORDIC unit; the register stack includes a posit format number register (Posit Register File, referred to as PRF, that is, Figure 2The PRF module in the posit processing unit is used to perform type conversion of the posit format number; the CORDIC unit performs different transcendental function operations on the input posit format number.

[0058] The RISC-V processor of Example 2 is further explained below in conjunction with the accompanying drawings.

[0059] like Figure 2 As shown, it is a RISC-V processor framework diagram of the present invention, which is a 5-stage pipeline sequential single-issue processor core. The processor core includes the following structures: a program counter, an instruction memory, a decoding module, an execution module, a load storage module, a register file, and a data memory.

[0060] The program counter is responsible for generating the instruction address according to the current conditions, and the instruction memory fetches instructions according to the instruction address; the decoding module is responsible for decoding the 32-bit data pointed to by the instruction, and obtaining the source operand address, the destination operand address and the instruction control signal. The instruction control signal includes the load storage signal, the ALU control signal, the jump control signal, the FPU control signal, the Posit and the CORDIC control signal. At the same time, according to the source operand and the destination operand address, the data of the corresponding address is taken out from the corresponding register stack, the integer instruction is taken out from the general register, the floating point type instruction is taken out from the floating point register, and the Posit type instruction is taken out from the Posit register stack; in the execution stage, according to the decoded corresponding instruction control signal, the corresponding data is operated, the final result is selected through the multiplexer, and the final output result is transmitted to the load storage module; if the instruction is load-storage related, the instruction memory interacts with the register stack, and the register stack includes the general register stack, the floating point register stack, and the Posit register stack. If not, the data is transmitted to the write-back stage.

[0061] The following is a detailed explanation of the RISC-V processor of Example 2 based on the processing process of each stage of the RISC-V processor.

[0062] 1. Instruction fetch stage The program counter starts generating instruction addresses by reading a 32-bit instruction from the current address in the instruction memory.

[0063] 2. Decoding stage The 32-bit instruction fetched from the instruction fetch stage is sent to the decoding module through the instruction fetch decoding register to perform decoding operations on the instruction. According to the difference between the opcode, funct5, funct3, functp, and es fields of the posit format instruction, the decoding module generates the control signal of the corresponding instruction, and reads the operand from the register according to the register address rs1 and rs2. The destination register receives the operation result according to the rd address. es represents the width of the posit format number exponent bit. The default value is 00, and the corresponding posit format data exponent bit width is 2 bits. The posit format number exponent bit width corresponding to the es, es-rd, and es-rs field encoding values ​​is shown in Table 1 below.

[0064] Table 1: Correspondence between es, es-rd, es-rs field encoding values ​​and posit format number exponent bit width 3. Execution Unit The execution module in Example 2 is designed with a Posit format number execution unit, which executes different instruction operations together with the ALU calculation unit, MUL calculation unit, etc. in the conventional execution module of the RISC-V processor. The Posit format number execution unit includes a posit processing unit and a CORDIC unit, see Figure 8 , the posit processing unit and the CORDIC unit both use the posit decoder and posit encoder to improve the multiplexing unit and reduce the circuit resource consumption. The posit processing unit includes a posit data conversion unit.

[0065] Specifically: see Figure 8 The input Posit format number enters the Posit decoder for processing, and the 32-bit Posit number is divided into three parts: exponent, mantissa and sign bit. According to the two enable signals Pcvt-en and P-CORDIC-en, it is determined whether to perform Posit data conversion or CORDIC calculation, and input it into the corresponding unit for corresponding operation. After the operation is completed, the corresponding result is output to the Posit encoder through the data selector according to the two enable signals. After the operation, the Posit encoder converts the 32-bit exponent, mantissa and sign bit into Posit format data.

[0066] As shown in Figure 9, this is the structure diagram of the CORDIC operation unit in Posit format, which is used for iterative operation of the CORDIC algorithm. The CORDIC unit also includes 2 Posit format multiplication and addition units, 1 Posit multiplication unit, and 1 Posit addition unit. The 2 Posit format multiplication and addition units are Posit format multiplication and addition fusers, the 1 Posit multiplication unit is a Posit multiplier, and the 1 Posit addition unit is a Posit adder.

[0067] Specifically, when the CORDIC operation unit performs the iterative operation of the CORDIC algorithm, the Posit multiplication and addition module, the Posit addition module and the Posit multiplication module of the CORDIC operation unit are used to perform the operation according to the following formulas (1), (2) and (3), and at the same time angle, State factor and The scaling factors are stored in the storage unit of the CORDIC operation unit and are gradually called during the calculation process.

[0068] The CORDIC unit can work in vector mode and rotation mode. In rotation mode, CORDIC rotates an initial vector to a specified angle, with the goal of obtaining the final coordinates through a series of rotations. In vector mode, CORDIC is mainly used to calculate the composite result of two known vectors. It can calculate the coordinates (x, y) of a given vector and its angle with the reference axis, and the calculated polar coordinates (r, ), where r is the magnitude of the vector, It's the angle.

[0069] The iterative calculation formula of generalized CORDIC is as follows: When the CORDIC operates in rotation mode, ;When CORDIC operates in vector mode, ;when When m=0, it is applicable to circular coordinates; when m=-1, it is applicable to hyperbolic coordinates. In the above formula, and are the coordinates of each iteration, is the accumulated value of the rotation angle, is the direction of rotation (1 or -1), indicating clockwise or counterclockwise rotation, is the angle of rotation at step i.

[0070] As shown in Figure 10, it is a configurable Posit multiplication unit. Due to the particularity of the Posit format number, the mantissa result that appears in the Posit decoding stage contains different bit width forms. The present invention selects signals according to different bit width parameters. When performing Posit multiplication or multiplication and addition operations of the CORDIC unit, Posit multipliers with different bit widths can be selected according to the different mantissa bit widths, which greatly reduces the power consumption of the circuit and meets the characteristics of variable bit width after the mantissa of the Posit data is decoded. The Posit configurable multiplication unit includes 6 different bit widths of configurable multiplication units, namely 8×8, 16×8, 32×8, 16×16, 32×16 and 32×32 bits. After the mantissa bit width result appears in the Posit decoder, the Posit configurable multiplication unit is configured according to the mantissa bit width result, and circuit resources are efficiently utilized.

[0071] In the execution phase, the corresponding data enters different execution units according to the control signal generated in the decoding phase. The posit processing unit is responsible for the conversion between posit numbers and single-precision floating-point numbers and integers, and the CORDIC unit is responsible for the transcendental function calculation of posit numbers. A data selector is included at the end of the execution phase. Since the execution phase includes ALU, FPU, posit and other execution units, all of which will generate calculation results, a data selector is added at the end of the execution phase to select the correct output result through the control signal of the decoding phase.

[0072] 4. Load and store phase If it is a load-store instruction, it interacts with the data memory. If it is a non-load-store instruction, the data is output to the register file through the pipeline register. Different register files are selected according to the data category. The register stacks include the general register stack GPR, the floating-point register stack FPR, and the Posit register stack PRF.

[0073] The above is a detailed introduction to a RISC-V instruction set expansion method including POSIT format instructions and a RISC-V processor provided by the present invention. This article uses specific examples to illustrate the structure and working principle of the present invention. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, the present invention can also be improved and modified, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A RISC-V instruction set expansion method including posit format instructions, characterized in that: The method comprises modifying the RISC-V instruction set so that the RISC-V instruction set supports posit format instructions; The RISC-V instruction set modification includes modifying the opcode and using a specific opcode as an identifier of a posit format instruction; Use funct3 field encoding, funct5 field encoding or functp field encoding to distinguish the specific type of posit format instructions; Use rs1, rs2, and rd field encodings to represent the address of source operand 1, source operand 2, and destination register address, respectively; The es field is used to encode the destination operand exponent width for instructions in POSIT format.

2. A RISC-V instruction set expansion method comprising posit format instructions according to claim 1, characterized in that: Use the custom-0 encoding field reserved by the RISC-V instruction set as the opcode of the posit format instruction.

3. A RISC-V instruction set expansion method comprising posit format instructions according to claim 1, characterized in that: The es field is encoded as a 25-26 bit field of the RISC-V instruction encoding.

4. A RISC-V instruction set expansion method comprising posit format instructions according to claim 1, characterized in that: The types of the posit format instructions include: posit format number conversion instructions, posit format number load and store instructions, and posit transcendental function instructions; The posit format number conversion instruction is distinguished by the funct3 field code, or the funct3 field code is distinguished in combination with the functp field code; The posit format data load and store instructions use the RISC-V instruction set single-precision load and store instruction encoding format, and the opcode of the RISC-V instruction set single-precision load and store instruction encoding format is replaced with a posit format instruction opcode; The posit transcendental function instruction is distinguished by the funct5 field encoding.

5. A RISC-V instruction set expansion method comprising posit format instructions according to claim 4, characterized in that: The funct3 field code is used to distinguish the instructions for converting Posit format numbers to single-precision floating-point numbers, Posit format numbers to integer data, integer data to Posit format numbers, and single-precision floating-point numbers to Posit format numbers; The instructions for converting Posit format numbers are distinguished by combining the funct3 field code with the functp field code.

6. A RISC-V instruction set expansion method comprising posit format instructions according to claim 5, characterized in that: The Posit format number conversion instruction encoding also includes es-rs and es-rd field encodings, which represent the exponent field bit widths of the source operand and the destination operand respectively; The es-rd field is encoded as a 25-26 bit field of the RISC-V instruction encoding, and the es-rs field is encoded as a 27-28 bit field of the RISC-V instruction encoding.

7. A RISC-V instruction set expansion method comprising posit format instructions according to claim 6, characterized in that: If the es-rd field code and es-rs field code of the Posit format number conversion instruction are the same, there is no need to perform the Posit format number conversion; If the es-rd field encoding and the es-rs field encoding of the Posit format number conversion instruction are different, the Posit format number conversion is performed based on the es-rd field.

8. A RISC-V instruction set expansion method comprising posit format instructions according to claim 1, characterized in that: After the Posit format instruction is encoded, the riscv-opcodes of the compiler are modified so that the Posit format instruction can be recognized by the compiler, and a machine code containing the Posit format instruction is generated for the processor to execute.

9. A RISC-V instruction set expansion method comprising posit format instructions according to claim 4, characterized in that: The funct3 field encoding of the posit format number conversion instruction and the funct5 field encoding of the posit transcendental function instruction are both written in Gray code; The funct5 field code of the posit format number conversion instruction and the funct3 field code of the posit transcendental function instruction are both 0.

10. A RISC-V processor, used to execute a RISC-V instruction set generated by a RISC-V instruction set expansion method containing posit format instructions as described in any one of claims 1 to 9, wherein the RISC-V processor comprises at least a decoding module, an execution module and a register stack, and is characterized in that: The decoding module customizes the posit format instruction decoding data path for decoding the posit format instruction; The execution module includes a posit format number execution unit, and the posit format number execution unit includes a posit processing unit and a CORDIC unit; The register file includes a posit format number register; The decoding module parses the Posit format instruction to generate a function control logic signal, and fetches the Posit format number from the Posit format number register to the execution module according to the control logic signal; The posit format number conversion unit in the posit processing unit is used to perform type conversion of the posit format number; The CORDIC unit performs different transcendental function operations on the input posit format number.

11. A RISC-V processor according to claim 10, characterized in that: The posit format number execution unit also includes a Posit decoder and a Posit encoder; The posit processing unit and the CORDIC unit share the same posit decoder and posit encoder; The Posit decoder decomposes the input Posit format number into an exponent, a mantissa and a sign bit; The posit processing unit and the CORDIC unit receive the output results of the Posit decoder respectively; The operation results of the posit processing unit and the CORDIC unit are selected by a multiplexer and output to the Posit encoder, and the Posit encoder converts the calculated exponent, mantissa and sign bit into a posit format number; The multiplexer, the posit processing unit and the CORDIC unit are all controlled by two different enable signals.

12. A RISC-V processor according to claim 10, characterized in that: The CORDIC unit includes two Posit multiplication and addition units, a Posit multiplication unit, a Posit addition unit and a storage unit for iterative calculation of the CORDIC algorithm; The storage unit stores angle, State factor and The scaling factor is called incrementally during the calculation process.

13. A RISC-V processor according to claim 12, characterized in that: The Posit multiplication unit is a configurable Posit multiplication unit, and the configurable Posit multiplication unit selects signals according to different bit width parameters and selects Posit multipliers with different bit widths; The multiplier bit width of the configurable Posit multiplication unit includes: 8×8 bits, 16×8 bits, 32×8 bits, 16×16 bits, 32×16 bits and 32×32 bits.

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