Instruction conversion access conflict optimization method based on instruction stream feature recognition

Abstract

The invention discloses an instruction stream feature recognition-based instruction conversion memory access conflict optimization method, which comprises the following steps of: in a process of pre-executing an executable file in an ARM (Advanced RISC Machines) many-core system in a dynamic instruction conversion manner, determining shared memories among processes by adopting instruction stream analysis to form a first shared memory list, and on the basis, determining the memory access conflict among the processes; the executable file is loaded and executed again, the memory access type to-be-converted instruction with the memory address located in the first shared memory list is converted into an instruction sequence composed of a locking instruction sequence, a second ARM instruction sequence and an unlocking instruction sequence, and meanwhile conversion execution of the executable file is completed based on a cache consistency protocol. The memory access conflict of the x86 program on the ARM many-core system is obviously reduced, and powerful support is provided for realizing high-performance dynamic instruction conversion.

Description

Technical Field

[0001] The invention belongs to the technical field of computer instruction conversion and multi-core system, and in particular relates to an instruction conversion memory access conflict optimization method based on instruction stream feature recognition. Background Art

[0002] When the ARM many-core system executes x86 programs in a dynamic instruction conversion mode, multiple ARM computing cores will access the memory at the same time, which is prone to memory access conflicts, thereby reducing the performance of the ARM many-core system. The existing memory access conflict resolution method is difficult to effectively deal with complex memory access situations, which will lead to a significant increase in memory access latency and the overall performance of the ARM many-core system cannot meet expectations. Summary of the invention

[0003] In view of this, the present invention provides an instruction conversion memory access conflict optimization method based on instruction stream feature recognition, which uses instruction stream analysis to realize feature recognition of shared memory and completes dynamic conversion of x86 instructions to ARM instructions.

[0004] The present invention provides an instruction conversion memory access conflict optimization method based on instruction stream feature recognition, which specifically includes the following steps: Step 1: pre-execute an executable file in an ARM many-core system in a dynamic instruction conversion manner, use instruction stream analysis to determine a first x86 instruction sequence related to an x86 system call, parse a first ARM instruction sequence converted from the first x86 instruction sequence to determine a shared memory between processes to form a first shared memory list; Step 2, load and execute the executable file in a dynamic instruction conversion mode, if the current instruction to be converted is a memory access instruction and the memory address is in the first shared memory list, convert the current instruction to be converted into an instruction sequence consisting of a lock instruction sequence, a second ARM instruction sequence and an unlock instruction sequence, and execute step 3 when the current instruction to be converted is a read operation, and execute step 4 when it is a write operation; otherwise, execute step 5; Step 3: If the cache line corresponding to the current computing core is in an invalid state, a read request is sent to the bus to read the data and the state of the cache line is set to a shared state or an exclusive state after the read is completed; if it is a shared state or an exclusive state, data is read from the cache line; and then step 5 is executed; Step 4: If the cache line corresponding to the current computing core is in an exclusive state, the data in the cache line is modified and set to a modified state; if it is in a shared state, an invalidation message is sent to other computing cores, and after the response is confirmed, it is set to a modified state, and then a write operation is performed; if it is in an invalid state, a read-exclusive request is sent to the bus, and after obtaining the data, it is set to a modified state, and then a write operation is performed; if it is in a modified state, a write operation is performed; Step 5: If the executable file has not completed execution, execute step 2; otherwise, end this process.

[0005] Furthermore, the method of using instruction stream analysis to determine the first x86 instruction sequence related to the x86 system call in step 1 is: after using instruction stream analysis to identify the system call number of the shared memory related x86 system call, the first x86 instruction sequence is formed from the instruction containing the system call number to the soft interrupt trigger instruction.

[0006] Furthermore, the manner in which the first ARM instruction sequence converted from the first x86 instruction sequence is parsed in step 1 to determine the shared memory between processes to form the first shared memory list is: If the first ARM instruction sequence includes a system call for creating or obtaining a shared memory segment, an ARM instruction A for saving a shared memory key value is added after the first ARM instruction sequence; if the first ARM instruction sequence includes a system call for attaching a shared memory segment to an address space of a calling process, an ARM instruction B for saving a shared memory address is added after the first ARM instruction sequence; the process ID, shared memory key value and shared memory address of the current process are obtained, a shared memory list is formed by the shared memory key value, the shared memory address and the process ID for creating the shared memory, and the shared memory list is used as the first shared memory list.

[0007] Furthermore, the process ID in the shared memory list is traversed as the target process, and the page table entries of all shared memory pages of the target process are obtained and recorded as original page table entries; the mapping relationship between the above shared memory page and the physical memory page is released, and then the information of the original page table entry is saved in the page table of the target process, and the shared memory address that triggers the page fault exception and the exception address belongs to the shared memory list is saved in the first shared memory list.

[0008] Furthermore, the locking instruction sequence in step 2 is composed of an instruction for setting a lock variable, an atomic operation LDREXB for loading an exclusive byte, and an atomic operation STREXB for storing an exclusive byte.

[0009] Furthermore, the unlocking instruction sequence in step 2 is composed of instructions for modifying lock variables.

[0010] Furthermore, in the step 2, the second ARM instruction sequence is composed of ARM instructions having the same function as the current instruction to be converted and other memory access related instructions.

[0011] Furthermore, the method of sending a read request to the bus to read data in step 3 is to read data from a cache line or memory of other computing cores.

[0012] Furthermore, the x86 system calls in step 1 include: shmget, shmat, shmdt and shmctl. Beneficial Effects

[0013] In the process of pre-executing an executable file in an ARM many-core system by means of dynamic instruction conversion, the present invention adopts instruction stream analysis to determine the shared memory between processes to form a first shared memory list, and on this basis, loads and executes the executable file again, and for memory access instructions to be converted whose memory addresses are in the first shared memory list, converts them into an instruction sequence consisting of a locking instruction sequence, a second ARM instruction sequence and an unlocking instruction sequence, and simultaneously completes the conversion and execution of the executable file based on a cache consistency protocol, significantly reducing the memory access conflicts of x86 programs on the ARM many-core system, and providing strong support for realizing high-performance dynamic instruction conversion. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A flow chart of an instruction conversion memory access conflict optimization method based on instruction stream feature recognition provided by the present invention. DETAILED DESCRIPTION

[0015] The present invention is described in detail below with reference to the accompanying drawings and with reference to the embodiments.

[0016] The present invention provides an instruction conversion memory access conflict optimization method based on instruction stream feature recognition, the core idea of ​​which is: in the process of pre-executing an executable file in a dynamic instruction conversion manner in an ARM many-core system, instruction stream analysis is used to determine the shared memory between processes to form a first shared memory list, and on this basis, the executable file is loaded and executed again, and for the memory access instructions to be converted whose memory addresses are located in the first shared memory list, they are converted into an instruction sequence consisting of a locking instruction sequence, a second ARM instruction sequence and an unlocking instruction sequence, and the conversion and execution of the executable file is completed based on a cache consistency protocol.

[0017] The present invention provides an instruction conversion memory access conflict optimization method based on instruction stream feature recognition, the specific process is as follows: Figure 1 As shown, the specific steps include: Step 1, pre-execute an executable file in an ARM many-core system in a dynamic instruction conversion manner, identify the system call number of the shared memory related x86 system call through instruction stream analysis, form a first x86 instruction sequence from the instruction containing the system call number to the soft interrupt trigger instruction, and convert the first x86 instruction sequence into a first ARM instruction sequence; if the first ARM instruction sequence contains a system call for creating or obtaining a shared memory segment, then add an ARM instruction A for saving a shared memory key value after the first ARM instruction sequence; if the first ARM instruction sequence contains a system call for attaching a shared memory segment to the address space of a calling process, then add an ARM instruction B for saving a shared memory address after the first ARM instruction sequence; obtain the process ID, shared memory key value and shared memory address of the current process, and save the shared memory key value, shared memory address and the process ID for creating the shared memory in a shared memory list.

[0018] There are multiple system calls in the existing x86 architecture for implementing shared memory related operations, including: shmget, shmat, shmdt, shmctl, etc., among which shmget is used to create or obtain a shared memory segment, shmat is used to attach a shared memory segment to the address space of the calling process, shmdt is used to separate a shared memory segment from the address space of the calling process, and shmctl is used to control the shared memory segment. Usually, the system calls related to shared memory in the ARM architecture and the x86 architecture are the same. For example, the system call in the ARM architecture similar to the shmget in the x86 architecture is also shmget.

[0019] Step 2: traverse the process ID in the shared memory list as the target process, obtain the page table entries of all shared memory pages of the target process, and record them as original page table entries; release the mapping relationship between all the above shared memory pages and physical memory pages, so that all processes cannot use all the above shared memory pages, and then save the information of the original page table entries into the page table of the target process.

[0020] Each process has its own independent virtual address space, and the process's page table is used to convert the virtual address used by the process into the actual physical memory address.

[0021] Step 3: When a page fault exception is triggered and the exception address belongs to the shared memory list, the shared memory address corresponding to the exception memory page is saved in the first shared memory list, and then the mapping relationship between the exception memory page and the physical memory page is restored to complete the pre-execution of the executable file.

[0022] The present invention can pre-acquire an instruction sequence related to a system call in the executable file, i.e., a first x86 instruction sequence, by pre-executing an executable file in an ARM many-core system in a dynamic instruction conversion manner, convert the first x86 instruction sequence into a first ARM instruction sequence in accordance with the existing dynamic instruction conversion manner, and then add different ARM instructions according to different system calls included in the first ARM instruction sequence to save the relevant information of the shared memory, preliminarily determine the relevant shared memory, and then construct a trigger condition for a page fault exception by modifying the page table entry of the shared memory and the page table of the process that creates the shared memory, so as to further determine that the shared memory that will actually be shared among multiple processes forms a first shared memory list.

[0023] Step 4: Load and execute the executable file in the ARM many-core system in a dynamic instruction conversion manner to obtain the current instruction to be converted. If the current instruction to be converted is a memory access instruction and the relevant memory address is in the first shared memory list, then execute step 5 when the current instruction to be converted is a read operation, and execute step 6 when the current instruction to be converted is a write operation; otherwise, execute step 7.

[0024] Step 5, convert the current instruction to be converted into an instruction sequence consisting of a lock instruction sequence, a second ARM instruction sequence and an unlock instruction sequence. At the same time, if the state of the cache line corresponding to the current instruction to be converted in the current computing core is invalid, the current computing core sends a read request to the bus to read the data and sets the state of the cache line where the data is located to a shared state or an exclusive state after the reading is completed; if it is a shared state or an exclusive state, the current computing core directly reads the data from the cache line; then execute step 7.

[0025] The lock instruction sequence consists of instructions for setting lock variables, atomic operations LDREXB for loading exclusive bytes, and atomic operations STREXB for storing exclusive bytes, and the unlock instruction sequence consists of instructions for modifying lock variables. The current computing core sends a read request to the bus to read data by reading data from the cache line or memory of other computing cores. The second ARM instruction sequence consists of ARM instructions with the same function as the current instruction to be converted and other memory access related instructions.

[0026] For example, when computing core A executes a read instruction to access data at a certain address, its cache line status is invalid. Computing core A issues a read request. If computing core B has the data in its cache and it is in a modified state, computing core B first writes the data back to the main memory and then sends the data to computing core A. At the same time, the cache line status of computing cores B and A both become shared.

[0027] In addition, the cache line of computing core A is in a shared state. When a read instruction is executed to access data corresponding to the cache line, the data is directly read from the cache and the state is still shared.

[0028] Step 6: Convert the current instruction to be converted into an instruction sequence consisting of a lock instruction sequence, a second ARM instruction sequence and an unlock instruction sequence. At the same time, if the state of the cache line corresponding to the current instruction to be converted in the current computing core is an exclusive state, the current computing core directly modifies the data in the cache line and sets the state of the cache line to a modified state; if it is a shared state, send an invalidation message to other computing cores, and set the state of the cache line to a modified state after other computing cores respond and confirm, and then perform a write operation; if it is an invalid state, send a read-exclusive request to the bus, and set the state of the cache line to a modified state after obtaining the data, and then perform a write operation; if it is a modified state, directly perform the write operation.

[0029] Specifically, when the cache line state is exclusive, since the data only exists in the cache of the current computing core and is consistent with the main memory data, the computing core can directly modify the data in the cache line and change the cache line state to modified state. At this time, there is no need to communicate with other computing cores. For example, the cache line of computing core A is in exclusive state. After executing a write instruction to modify the cache line data, the cache line state changes to modified state.

[0030] When a computing core wants to write to a cache line in a shared state, it needs to first send an invalidate message (Invalidate message) to other computing cores to notify other computing cores to invalidate the copies of the data. After receiving the message, the other computing cores will set the corresponding cache line status in their own cache to an invalid state. When all other computing cores respond with confirmation, the computing core that initiated the write operation changes its own cache line status to a modified state and then performs the write operation. For example, the cache lines of computing cores A, B, and C all have copies of certain data, and the status is a shared state. When computing core A executes a write instruction, it sends an invalidate message to computing cores B and C. After receiving the message, computing cores B and C set the corresponding cache line status to an invalid state and reply with a confirmation. After receiving the confirmation, computing core A changes its own cache line status to a modified state and then performs the write operation.

[0031] When the cache line is invalid, the computing core needs to obtain a valid copy of the data first, so it will issue a read-exclusive request to the bus, which means that it wants to read the data and has exclusive access to the subsequent write of the data. If there is a valid copy of the data in the cache line of other computing cores, the computing core with the copy will send the data to the core that initiated the request and set its own cache line state to invalid; if other computing cores do not have a valid copy, the data will be read from the main memory. After obtaining the data, the cache line state is set to modified, and then a write operation is performed. For example, the cache line of computing core A is in an invalid state, and a read-exclusive request is issued when executing a write instruction. If computing core B has a valid copy of the data, computing core B sends the data to computing core A and sets its own cache line to invalid. After receiving the data, computing core A changes the cache line state to modified, and then performs a write operation.

[0032] When the cache line is in the modified state, the computing core can directly modify the data in the cache line because the computing core has the only valid copy of the data and it has been modified. The cache line state remains in the modified state. For example, the cache line of computing core A is in the modified state. When executing a write instruction to modify the data, the cache line is directly operated and the state remains in the modified state.

[0033] Step 7: If the executable file has not been executed, execute step 4; otherwise, end this process. Example

[0034] In this embodiment, an instruction conversion memory access conflict optimization method based on instruction stream feature recognition provided by the present invention is adopted, and a low memory access conflict conversion execution of an x86 architecture executable file on an ARM many-core system is realized by modifying a memory access code generation module in a dynamic instruction conversion engine, including the following steps: S1. Detect the shared memory area of ​​the target program based on instruction stream feature detection. The specific steps are as follows: S1.1. Identify memory allocation related function calls during dynamic instruction conversion. Under the x86 architecture, for the underlying system calls related to shared memory creation, the assembly level calls are as follows: moveax, <shmgetsyscallnumber> / / Put the system call number into the eax register movebx, <key> / / Put the shared memory key value into the ebx register to identify the shared memory movecx, <size> / / Insert the shared memory size movedx, <flags> / / Put in flags, such as permissions and other related settings int0x80 / / trigger soft interrupt, enter kernel state and execute system call After the ARM architecture conversion, the ARM system call corresponding to shmget is implemented as follows: movr7, <shmgetsyscallnumberforarm> / / Put the shmget system call number under ARM into register r7 movr0, <key> / / Put the shared memory key value into register r0 movr1, <size> / / Shared memory size is put into register r1 movr2, <flags> / / Put the flag into register r2 svc0x00 / / trigger system call (use svc instruction in ARM instead of x86 int instruction) Insert the following code after the converted ARM instruction to save the shared memory address, where r0 is the return value after svc0x00: strr0,[shared_memory_id] / / Subsequent code can read the return value from shared_memory_id at any time for analysis A mapping between a shared memory ID and a shared memory size is established, where the shared memory ID is stored in the address shared_memory_id and the shared memory size is stored in the r1 register.

[0035] S1.2, Track memory mapping related operations. In the x86 architecture, after obtaining the shared memory segment identifier, it needs to be mapped to the address space of the process, which is usually achieved by calling the shmat function. The assembly level call is as follows: moveax, <shmatsyscallnumber> / / Put the system call number into eax movebx, <shmid> / / Put the shared memory segment identifier obtained previously into ebx movecx, <addr> / / Write the expected mapped address into ecx movedx, <flags> / / Map the relevant flags into edx int0x80 / / Execute system call for memory mapping The instructions after ARM architecture conversion are: movr7, <shmatsyscallnumberforarm> / / The shmat system call number under ARM is placed in r7 movr0, <shmid> / / Put the shared memory segment identifier into r0 movr1, <addr> / / Expected mapping address to be placed in r1 movr2, <flags> / / Map the flag into r2 svc0x00 / / trigger system call to complete mapping Insert the following code after the converted ARM instruction to save the shared memory address, where r0 is the return value after svc0x00: strr0,[shared_memory_address] / / Subsequent code reads the return value from shared_memory_address for analysis Based on the mapping between the shared memory ID and the shared memory size established in the previous step, a mapping between the shared memory address and the shared memory size is established.

[0036] S1.3. A shared memory list is constructed through the established mapping, recorded as sharedMemoryList. Each element of the list includes a starting address and length of a shared memory, and the ID of the process that created the shared memory area.

[0037] Existing shared memory detection methods mainly rely on identifying specific system call function names to determine shared memory creation operations. However, in dynamic instruction conversion scenarios, function names may undergo complex conversions, obfuscations, or optimizations, causing traditional methods to fail. The present invention proposes an intelligent recognition method based on instruction stream features. By analyzing specific patterns and register operation features in the instruction stream and identifying from the lowest level of system calls, it is possible to more accurately determine whether a shared memory creation operation exists.

[0038] S2, track the shared memory in sharedMemoryList to determine the memory that will actually be accessed by other processes. S1 can only determine whether the memory is used as shared memory but cannot determine whether it will be accessed by other processes. However, memory access conflicts may occur only if there are memory spaces that will be accessed by other processes, so judgment and identification are still needed.

[0039] The specific steps are as follows: S2.1. Traverse all processes in sharedMemoryList. For each process, record the process ID as processID, obtain the page table entry of its shared memory page, and copy the page table entry as originalPageTable.

[0040] S2.2. For the shared memory pages recorded in sharedMemoryList, release their mapping relationship to the physical memory pages, thereby releasing the mapping of all processes to them, and then use the page fault exception to track and record the access process, release the page mapping, and hold mmap_lock, as follows: pte_t*pte=get_pte(target_vma->vm_mm,target_addr) pte_clear(target_vma->vm_mm,target_addr,pte) flush_tlb_page(target_vma,target_addr) S2.3. Traverse all processes in sharedMemoryList, and for each process with ID processID, copy originalPageTable back to the page table of process processID, that is, restore the process page table that was released in the previous step, so that the page fault exception will be triggered only when other processes access the shared memory in sharedMemoryList.

[0041] S2.4. When a page fault exception is triggered when the process accesses the page, if the address where the exception occurs is in sharedMemoryList, this memory page is counted into usedSharedMemoryList; the mapping is restored to handle the current exception and enable the current process to continue execution normally. The specific examples are as follows: set_pte_at(vmf->vma->vm_mm,vmf->address,vmf->pte,orig_pte) / / Reset the original PTE structpage*page=pte_page(orig_pte) / / Increase the reference count of the physical page (to prevent it from being released) get_page(page) / / Increase refcount if(vmf->flags&FAULT_FLAG_WRITE) / / Mark page as accessed / dirty pte = pte_mkdirty (orig_pte) / / refresh TLB, optional, set_pte_at may be implicitly processed flush_tlb_page(vmf->vma,vmf->address) returnVM_FAULT_NOPAGE / / Inform the kernel that the mapping has been restored S3. For the shared memory that is determined to be accessed by multiple processes, that is, the shared memory recorded in usedSharedMemoryList, a conflict avoidance method based on a lock mechanism is used to ensure exclusive access to the shared memory. The specific steps are as follows: S3.1. Implementation and initialization of the lock. In the generated ARM memory access instruction, use atomic operations and specific memory areas as lock variables. First, allocate a byte in the memory as the lock flag and initialize it to 0, indicating an unlocked state. Assuming that the address of the lock is stored in r0, the following is the ARM assembly code for initializing the lock: LDRr1,=0 STRBr1,[r0] S3.2, check whether the memory access address is within the range of a shared memory in the established shared memory list. If so, perform the following steps: Lock operation. When the ARM computing core needs to access the shared memory area, it will try to acquire the lock. Use the atomic operations LDREXB (load exclusive byte) and STREXB (store exclusive byte) to implement locking. If the value loaded by LDREXB is 0 and STREXB successfully stores 1, it means that the core successfully acquires the lock; otherwise, it will retry. The following is the ARM assembly code for the lock operation: lock_loop: LDREXBr2,[r0] CMPr2,#0 BNElock_loop MOVr3,#1 STREXBr4,r3,[r0] CMPr4,#0 BNElock_loop LDRr5,[r6] / / Assume that the shared data address is stored in r6 ADDr5,r5,#1 STRr5,[r6] Unlock operation. When the operation is completed, the unlock operation is performed by storing 0 to the lock variable. Assuming that the address of the lock is stored in r0, the following is the ARM assembly code for the unlock operation: LDRr1,=0 STRBr1,[r0] LDRr8,=1 STRBr8,[r7] / / Assume that the memory flag is used as a semaphore and stored in r7 The existing lock mechanism may be based on the library function of the high-level language, while the present invention uses the atomic operation of ARM assembly to implement the lock, avoiding the extra overhead of the high-level language, and can more accurately control the granularity of the lock, and can achieve concurrent control of memory access at a lower level, which is suitable for fine-grained access control of shared memory in the ARM multi-core environment, and improves the synchronization and security of memory access. At the same time, the unlocking operation is combined with the subsequent notification mechanism, so that after unlocking, the operations of multiple cores can be coordinated more flexibly, avoiding blind waiting of other cores, thereby improving the parallelism of the overall system.

[0042] S4. Use the cache consistency protocol to manage cache status to avoid inconsistent memory access. The cache stores a copy of the shared memory. Each computing core maintains its own private cache, and a copy of the same shared memory may exist in the private cache. The specific steps are as follows: S4.1. Use ARM's cache consistency protocol, such as MESI, to reduce memory access conflicts. ARM many-core systems usually follow the MESI protocol to maintain cache consistency. In the translation engine, ensure that the instructions after program translation fully utilize the advantages of the MESI protocol. For example, when performing memory access, the operation is determined based on the MESI status (Modified, Exclusive, Shared, Invalid).

[0043] S4.2, when a core reads data, if the cache status is Invalid, a read request is initiated to obtain data from the memory or the cache of other cores, and the cache status is updated to Shared or Exclusive. Assuming that the data address is stored in r0, the following is an ARM assembly code example for the read operation: LDRr1,[r0] MRCp15,0,r2,c0,c0,0 / / Check cache status CMPr2,#0 / / If the status is Invalid, initiate a read request BEQread_request Buse_data / / If the status is Shared or Exclusive, use the data directly read_request: / / Initiates a read request to obtain data from memory or other core caches LDRr1,[r0] MCRp15,0,r3,c0,c0,0 / / Update the cache status to Shared or Exclusive. The cache status is set by the coprocessor instruction. The specific instructions vary depending on the hardware. LDRr5,[r4] / / Assume the monitoring address is stored in r4, if the data is modified, it may need to be re-read CMPr5,#1 / / Assume 1 means the data is being modified BEQreread Buse_data reread: LDRr1,[r0] MCRp15,0,r6,c0,c0,0 / / Update cache status again use_data: Existing program conversions may not fully consider the importance of cache consistency protocols in memory access conflicts. The present invention ensures active management of cache status in a multi-core environment by utilizing ARM's MESI protocol at the assembly level, avoiding inconsistent access to the same data by multiple cores at the same time, reducing memory access conflicts caused by cache inconsistencies, and improving data access consistency and performance. Consideration of the cache monitoring mechanism has been added. When reading data, it not only checks the current cache status, but also checks whether other cores are modifying the data, further enhancing the guarantee of data consistency and avoiding data conflicts caused by cache update delays. It is an innovative extension on the original basis.

[0044] In summary, the above are only preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.< / flags> < / addr> < / shmid> < / shmatsyscallnumberforarm> < / flags> < / addr> < / shmid> < / shmatsyscallnumber> < / flags> < / size> < / key> < / shmgetsyscallnumberforarm> < / flags> < / size> < / key> < / shmgetsyscallnumber>

Claims

1. A method for optimizing instruction conversion memory access conflicts based on instruction stream feature recognition, characterized in that: The specific steps include: Step 1: pre-execute an executable file in an ARM many-core system in a dynamic instruction conversion manner, use instruction stream analysis to determine a first x86 instruction sequence related to an x86 system call, parse a first ARM instruction sequence converted from the first x86 instruction sequence to determine a shared memory between processes to form a first shared memory list; Step 2, load and execute the executable file in a dynamic instruction conversion mode, if the current instruction to be converted is a memory access instruction and the memory address is in the first shared memory list, convert the current instruction to be converted into an instruction sequence consisting of a lock instruction sequence, a second ARM instruction sequence and an unlock instruction sequence, and execute step 3 when the current instruction to be converted is a read operation, and execute step 4 when it is a write operation; otherwise, execute step 5; Step 3: If the cache line corresponding to the current computing core is in an invalid state, a read request is sent to the bus to read the data and the state of the cache line is set to a shared state or an exclusive state after the read is completed; if it is a shared state or an exclusive state, data is read from the cache line; and then step 5 is executed; Step 4: If the cache line corresponding to the current computing core is in an exclusive state, the data in the cache line is modified and set to a modified state; if it is in a shared state, an invalidation message is sent to other computing cores, and after the response is confirmed, it is set to a modified state, and then a write operation is performed; if it is in an invalid state, a read-exclusive request is sent to the bus, and after obtaining the data, it is set to a modified state, and then a write operation is performed; if it is in a modified state, a write operation is performed; Step 5: If the executable file has not completed execution, execute step 2; otherwise, end this process.

2. The instruction conversion memory access conflict optimization method according to claim 1, characterized in that: The method of using instruction stream analysis to determine the first x86 instruction sequence related to the x86 system call in step 1 is: after using instruction stream analysis to identify the system call number of the shared memory related x86 system call, the first x86 instruction sequence is formed from the instruction containing the system call number to the soft interrupt trigger instruction.

3. The instruction conversion memory access conflict optimization method according to claim 1, characterized in that: The method of determining the shared memory between processes to form the first shared memory list by parsing the first ARM instruction sequence converted from the first x86 instruction sequence in step 1 is: If the first ARM instruction sequence includes a system call for creating or obtaining a shared memory segment, an ARM instruction A for saving a shared memory key value is added after the first ARM instruction sequence; if the first ARM instruction sequence includes a system call for attaching a shared memory segment to an address space of a calling process, an ARM instruction B for saving a shared memory address is added after the first ARM instruction sequence; the process ID, shared memory key value and shared memory address of the current process are obtained, a shared memory list is formed by the shared memory key value, the shared memory address and the process ID for creating the shared memory, and the shared memory list is used as the first shared memory list.

4. The instruction conversion memory access conflict optimization method according to claim 3, characterized in that: Traverse the process ID in the shared memory list as the target process, obtain the page table entries of all shared memory pages of the target process, and record them as original page table entries; release the mapping relationship between the above shared memory page and the physical memory page, and then save the information of the original page table entry into the page table of the target process, and save the shared memory address that triggers the page fault exception and the exception address belongs to the shared memory list into the first shared memory list.

5. The instruction conversion memory access conflict optimization method according to claim 1, characterized in that: The locking instruction sequence in step 2 is composed of an instruction to set a lock variable, an atomic operation LDREXB to load an exclusive byte, and an atomic operation STREXB to store an exclusive byte.

6. The instruction conversion memory access conflict optimization method according to claim 1, characterized in that: The unlocking instruction sequence in step 2 is composed of instructions for modifying lock variables.

7. The instruction conversion memory access conflict optimization method according to claim 1, characterized in that: In the step 2, the second ARM instruction sequence is composed of ARM instructions with the same functions as the current instruction to be converted and other memory access related instructions.

8. The instruction conversion memory access conflict optimization method according to claim 1, characterized in that: The method of sending a read request to the bus to read data in step 3 is to read data from the cache line or memory of other computing cores.

9. The instruction conversion memory access conflict optimization method according to claim 1, characterized in that: The x86 system calls in step 1 include: shmget, shmat, shmdt and shmctl.

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