Memory controller, operating method of memory controller, and operating method of memory device

Abstract

The invention provides an operating method of a memory controller, an operating method of a memory device, and a memory controller. The memory controller includes a buffer memory, an address manager, and a DMA engine and controls the non-volatile memory device. The DMA engine is a direct memory access engine. The operating method includes: receiving a read request including a host address from an external host device; storing, by the address manager, mapping information on the host address and a command identifier corresponding to the read request in a translation table in response to the read request; setting, by the DMA engine, a destination address of read data corresponding to the read request as a virtual address corresponding to the command identifier, and transmitting the read data to the virtual address; and translating, by the address manager, the destination address of the read data from the virtual address to the host address based on the translation table.

Description

Technical Field

[0001] The inventive concept relates to a semiconductor memory, and more particularly, to a memory controller, an operating method of the memory controller, and an operating method of a memory device. Background Art

[0002] Semiconductor memories can be classified into volatile memory devices that lose stored data when power is interrupted (e.g., static random access memory (RAM) (SRAM), dynamic RAM (DRAM), etc.) and non-volatile memory devices that retain stored data even when power is interrupted (e.g., flash memory, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc.).

[0003] The storage device may transmit data stored in the nonvolatile memory device to the host device. The storage controller may perform an error correction operation, such as a low-density parity check (LDPC), on the read data read from the nonvolatile memory device. Thereafter, the storage controller may store the error-corrected read data in a buffer memory, such as an SRAM. A first direct memory access (DMA) engine included in the storage controller may read data from the nonvolatile memory device and write the read data to the buffer memory. A second DMA engine included in the storage controller may read the data stored in the buffer memory and transmit the read data to the host device. Summary of the invention

[0004] The inventive concept provides a memory controller, an operating method of the memory controller, and an operating method of a memory device having improved performance.

[0005] According to one aspect of the present invention, there is provided an operating method of a storage controller, which includes a buffer memory, an address manager and a direct memory access (DMA) engine and controls a non-volatile memory device, the operating method including: receiving a read request including a host address from an external host device; storing, by the address manager in response to the read request, mapping information about the host address and a command identifier corresponding to the read request in a conversion table; setting, by the DMA engine, a destination address of read data corresponding to the read request to a virtual address corresponding to the command identifier and transferring the read data to the virtual address; and converting, by the address manager based on the conversion table, the destination address of the read data from the virtual address to the host address.

[0006] According to another aspect of the present invention, there is provided an operating method of a storage device, the storage device comprising a nonvolatile memory device and a storage controller, the storage controller comprising a host interface circuit, an address manager, a direct memory access (DMA) engine and a nonvolatile memory interface circuit and controlling the nonvolatile memory device, the operating method comprising: receiving a read request including a host address from an external host device by the host interface circuit; storing mapping information about the host address and a command identifier corresponding to the read request received from the host interface circuit in a conversion table by the address manager; generating mode information by the address manager and transmitting the mode information to the DMA engine; setting a destination address of read data to a virtual address based on the mode information and transmitting the read data to the virtual address by the DMA engine; converting the destination address of the read data from the virtual address to the host address by the address manager; and transmitting the read data to the host address by the host interface circuit.

[0007] According to another aspect of the present invention, a storage controller is provided, which includes: a host interface circuit, the host interface circuit is configured to receive a read request from an external host device and transmit read data corresponding to the read request to the external host device; an address manager, the address manager is configured to receive a command identifier and a host address from the host interface circuit, store mapping information about the command identifier and the host address in a conversion table, and perform an address conversion operation to convert a destination address of the read data from a virtual address to a host address; and a direct memory access DMA engine, the direct memory access engine is configured to set the destination address of the read data to the virtual address based on mode information received from the address manager, and transmit the read data to the virtual address. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a block diagram showing a storage system according to an embodiment;

[0010] Figure 2 is a block diagram showing a storage system according to an embodiment;

[0011] Figure 3 is a flowchart illustrating an example of an operating method of a storage controller according to an embodiment;

[0012] Figure 4A and Figure 4B is a diagram for describing an operating method of a storage controller according to an embodiment;

[0013] Figure 5is a flowchart illustrating an example of an operating method of a storage controller according to an embodiment;

[0014] Fig. 6A and Figure 6B is a diagram for describing an operating method of a storage controller according to an embodiment;

[0015] Fig. 7A and Figure 7B is a diagram for describing an operating method of a storage controller according to an embodiment;

[0016] Figure 8 is a flowchart illustrating an example of an operating method of a storage controller according to an embodiment;

[0017] Fig. 9 is a flowchart illustrating an example of an operating method of a storage controller according to an embodiment;

[0018] Fig.10 is a block diagram showing an example of a nonvolatile memory device according to an embodiment;

[0019] Fig.11 is a block diagram showing a solid state drive (SSD) system to which a storage device according to an embodiment is applied; and

[0020] Fig.12 is a diagram illustrating a data center to which a storage device according to an embodiment is applied. DETAILED DESCRIPTION

[0021] Hereinafter, embodiments of the inventive concept will be described clearly and in detail so that those having ordinary skill in the art can easily practice the inventive concept.

[0022] Figure 1 is a block diagram illustrating a memory system 1000 according to an embodiment.

[0023] refer to Figure 1 , the storage system 1000 may include a host device 10 and a storage device 1100. The storage system 1000 may be implemented as an electronic device, such as a personal computer (PC), a laptop computer, a mobile phone, a smart phone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, an audio device, a portable multimedia player (PMP), a personal navigation device or a portable navigation device (PND), an MP3 player, a handheld game console, or an e-book. In addition, the storage system 1000 may be implemented as various types of electronic devices, such as a wearable device, for example, a watch or a head-mounted display (HMD).

[0024] The host device 10 may control a data processing operation (e.g., a data read operation or a data write operation) with respect to the storage device 1100. The host device 10 may refer to a data processing device capable of processing data, such as a central processing unit (CPU), a processor, a microprocessor, or an application processor (AP). The host device 10 may run an operating system (OS) and / or various applications.

[0025] Specifically, the host device 10 may include a host controller 11 and a host memory 12. The host controller 11 may be a device configured to control the overall operation of the host device 10 or control the storage device 1100 on the host device side. The host memory 12 may be a buffer memory, a cache memory, or a working memory used in the host device 10.

[0026] In an embodiment, the host memory 12 may be used as a buffer memory configured to temporarily store data to be transmitted to or from the storage device 1100. The host device 10 may transmit a request to the storage device 1100 and receive a response from the storage device 1100. For example, when the request is a write request, the request may include write data. As another example, when the request is a read request, the response to the request may include read data.

[0027] The storage device 1100 may operate under the control of the host device 10. The storage device 1100 may include a storage controller 1200 and a non-volatile memory (NVM) device 1300. The storage controller 1200 may perform various management operations in order to effectively use the NVM device 1300. The NVM device 1300 may include a plurality of NVMs.

[0028] The storage device 1100 may receive a request from the host device 10 and transmit a response to the host device 10. For example, when the request is a write request, the storage controller 1200 may control the NVM device 1300 to write data to the NVM device 1300 in response to the write request from the host device 10. In another example, when the request is a read request, the storage controller 1200 may control the NVM device 1300 to read data stored in the NVM device 1300 in response to the read request from the host device 10.

[0029] When the NVM device 1300 includes a flash memory, the flash memory may include a two-dimensional (2D) NAND memory array or a three-dimensional (3D) (or vertical) NAND (VNAND) memory array. As another example, the memory device 1100 may include various other types of NVM. For example, magnetic random access memory (RAM) (MRAM), spin transfer torque MRAM, conductive bridge RAM (CBRAM), ferroelectric RAM (FeRAM), phase change RAM (PRAM), resistive RAM (RRAM) and various other types of memory may be applied to the memory device 1100.

[0030] The memory controller 1200 may include an address manager 1210, a first direct memory access (DMA) engine 1220, and a cache manager 1230. For example, the address manager 1210, the first DMA engine 1220, and the cache manager 1230 may be implemented in software, hardware, or a combination of software and hardware.

[0031] The memory controller 1200 may transfer read data read from the NVM device 1300 to the host device 10 without passing through the buffer memory. The memory controller 1200 may directly transfer the read data to the host device 10 using a virtual address without writing the read data to the buffer memory.

[0032] The address manager 1210 may manage address translation information (e.g., a translation table (TT)) between a command identifier and a host address. For example, a TT is a data structure that stores mappings between command identifiers and host addresses. The address manager 1210 may store mapping information between command identifiers and host addresses in the TT.

[0033] The TT may include information obtained by mapping the relationship between the host address and the command identifier. The TT may include multiple entries. Each of the entries in the TT may include a command identifier and a host address. The TT is a table for converting a virtual address into a host address.

[0034] The address manager 1210 may perform an address conversion operation. The address manager 1210 may perform an address conversion operation based on the TT. The address conversion operation may refer to an operation of converting a virtual address to a host address. The address manager 1210 may convert a virtual address to a host address by referring to the TT.

[0035] The first DMA engine 1220 may perform a DMA operation based on the mode information received from the address manager 1210. The first DMA engine 1220 may transfer the read data to the host device 10 without passing through the buffer memory. The first DMA engine 1220 may transfer the read data to the host device 10 using a virtual address. The first DMA engine 1220 may set the destination address of the read data to the virtual address and transfer the read data to the virtual address. In an embodiment, the first DMA engine 1220 may read the read data from the NVM device 1300. The first DMA engine 1220 may transfer the read data to the virtual address.

[0036] The address manager 1210 may perform DMA operations based on a virtual lookup table (VLUT). The first DMA engine 1220 may transfer read data to a virtual address by referring to the VLUT. The first DMA engine 1220 may retrieve a virtual address corresponding to a command identifier. The first DMA engine 1220 may retrieve a virtual address based on a command identifier corresponding to the read data by referring to the VLUT.

[0037] The VLUT may include information obtained by mapping the relationship between the virtual address and the command identifier. The VLUT is a table for transferring read data to the virtual address. The VLUT may be predetermined or updated.

[0038] The storage controller 1200 may generate and store a VLUT. The storage controller 1200 may manage the VLUT. The storage controller 1200 may assign a virtual address to a command identifier. The storage controller 1200 may assign different virtual addresses to the command identifier. That is, the command identifier may have different virtual addresses.

[0039] The virtual addresses assigned to the command identifiers may be referred to as virtual address ranges. The virtual address ranges may include the assigned virtual addresses. For example, the size of the virtual address range may be equal to the result of multiplying the number of command identifiers and the page size (eg, 4KB).

[0040] In an embodiment, cache manager 1230 may implement a cache. The cache may include a sub-buffer and a latch 1331 of NVM device 1300. When read data is stored in the sub-buffer and the latch 1331 of NVM device 1300, cache manager 1230 may load the read data from the sub-buffer or the latch 1331 of NVM device 1300. For example, the sub-buffer may be an error correction code (ECC) engine (e.g., ECC engine 1280 ( Figure 2 ))'s memory.

[0041] In an embodiment, the cache manager 1230 may determine whether a cache hit has occurred. The cache manager 1230 may determine whether the read data corresponding to the read request is stored in a cache (e.g., a cache in the NVM device 1300). When the cache manager 1230 determines that a cache hit has occurred, the cache manager 1230 may load the read data from the cache. That is, when the read data is stored in the cache, the cache manager 1230 may load the read data from the cache instead of reading the data from the memory cell array of the NVM device 1300. Therefore, the read latency may be reduced. Reference Figure 8 and Fig. 9 The operation method of cache manager 1230 is described in more detail.

[0042] As described above, the storage device 1100 may transmit read data corresponding to a read request to the host device 10 by using a virtual address without writing the read data to the buffer memory 1270 ( Figure 2 ). Therefore, the memory device 1100 can provide a short read latency and reduce the size of the buffer memory 1270 included in the memory controller 1200.

[0043] Figure 2 is a block diagram illustrating a storage system according to an embodiment.

[0044] refer to Figure 2 , the memory system 1000 may include a host device 10 and a memory device 1100. The host device 10 may include a host controller 11 and a host memory 12. The memory device 1100 may include a memory controller 1200 and an NVM device 1300. The NVM device 1300 may include a latch 1331. For convenience of explanation, detailed descriptions of the above elements are omitted.

[0045] The storage controller 1200 may include an address manager 1210, a first DMA engine 1220, a cache manager 1230, a CPU 1240, a flash translation layer (FTL) 1250, a buffer memory 1270, an ECC engine 1280, a host interface circuit (HOST IF) HI, an NVM interface circuit (MEMORY IF) MI, and a bus BUS. The storage controller 1200 may also include a packet manager (not shown), an advanced encryption standard (AES) engine (not shown), and the like.

[0046] The memory controller 1200 may further include a working memory (not shown) into which the FTL 1250 is loaded. The CPU 1240 may execute the FTL 1250 to control a data write operation and a data read operation with respect to the NVM device 1300.

[0047] In an embodiment, the CPU 1240 may be implemented as a multi-core processor. For example, the CPU 1240 may be implemented as a dual-core processor or a quad-core processor. The address manager 1210, the cache manager 1230, and the FTL 1250 may be loaded into a working memory of the storage controller 1200. For example, the working memory may be implemented as a volatile memory (e.g., a static RAM (SRAM) or a dynamic RAM (DRAM)) or a non-volatile memory (e.g., a flash memory or a PRAM).

[0048] The FTL 1250 may perform several functions such as address mapping, wear leveling, and garbage collection. Address mapping is an operation of converting a logical address received from the host device 10 into a physical address for actually storing data in the NVM device 1300. Wear leveling is a technique for preventing / preventing excessive degradation of a specific block by allowing the blocks in the NVM device 1300 to be used uniformly. For example, wear leveling may be implemented by a firmware technique for balancing the erase counts of physical blocks. Garbage collection is a technique for ensuring available capacity within the NVM device 1300 by copying valid data of a block to a new block and then erasing the existing block.

[0049] The buffer memory 1270 may be configured to temporarily store write data received from the host device 10 or data read from the NVM device 1300 under the control of the storage controller 1200. For example, the buffer memory 1270 may be configured to be controlled by the CPU 1240, the first DMA engine 1220, and the second DMA engine 1260. Hereinafter, it is assumed that the buffer memory 1270 is an SRAM. However, the scope of the inventive concept is not limited thereto.

[0050] For example, the buffer memory 1270 may include a high-speed RAM such as a DRAM and a synchronous DRAM (SDRAM). Alternatively, the buffer memory 1270 may include an NVM such as a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, a PRAM, an MRAM, an RRAM, a ferroelectric RAM (FRAM), or a thyristor RAM (TRAM).

[0051] ECC engine 1280 may perform error detection and correction functions on read data read from NVM device 1300. More specifically, ECC engine 1280 may generate parity bits for write data to be written to NVM device 1300, and the generated parity bits may be stored together with the write data in NVM device 1300. When reading data from NVM device 1300, ECC engine 1280 may correct errors in the read data by using the parity bits read from NVM device 1300 and the read data, and may output the error-corrected read data.

[0052] In an embodiment, the ECC engine 1280 can correct errors by using coded modulation such as soft decoding, low-density parity check (LDPC) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, turbo codes, Reed-Solomon codes, convolutional codes, recursive systematic codes (RSC), trellis-coded modulation (TCM), or block coded modulation (BCM), or various other schemes.

[0053] The AES engine (not shown) may perform at least one of an encryption operation and a decryption operation on data input to the memory controller 1200 by using a symmetric key algorithm.

[0054] The host interface circuit HI may transmit and receive packets to and from the host device 10. The packets transmitted from the host device 10 to the host interface circuit HI may include commands, requests, or data to be written to the NVM device 1300. The packets transmitted from the host interface circuit HI to the host device 10 may include responses to commands or data read from the NVM device 1300.

[0055] NVM interface circuit MI may transmit data to be written to NVM device 1300, or may receive data read from NVM device 1300. NVM interface circuit MI may be implemented to comply with a standard protocol such as Toggle or Open NAND flash interface (ONFI).

[0056] For example, Figure 2As shown, the first DMA engine 1220 and the second DMA engine 1260 can be implemented as separate hardware circuits. Although not shown, the first DMA engine 1220 and the second DMA engine 1260 can be implemented as a single hardware circuit and operate separately from each other in terms of function. For example, the first DMA engine 1220 can be a flash DMA (FDMA) engine. The second DMA engine 1260 can be a host DMA (HDMA) engine.

[0057] The first DMA engine 1220 may be a hardware device that controls a DMA operation between the buffer memory 1270 and the NVM device 1300 without intervention of the CPU 1240. The first DMA engine 1220 according to an embodiment may be a hardware device that controls a DMA operation between the host device 10 and the NVM device 1300. The second DMA engine 1260 may be a hardware device that controls a DMA operation between the host device 10 and the buffer memory 1270 without intervention of the CPU 1240.

[0058] For example, the storage device 1100 may operate in a DMA mode in order to increase the data transfer rate. The DMA mode is an operation mode in which data is transferred under the control of the first DMA engine 1220 and the second DMA engine 1260 with or without the intervention of the CPU 1240 (or processor, core, etc.) included in the storage controller 1200. That is, because the data does not need to be controlled or processed by the CPU 1240 while being transferred, the data transfer rate can be increased.

[0059] In DMA mode, the first DMA engine 1220 can control or manage data transmission between the buffer memory 1270 and the NVM device 1300, the first DMA engine 1220 can control or manage data transmission between the host device 10 and the NVM device 1300, and the second DMA engine 1260 can control or manage data transmission between the buffer memory 1270 and the host device 10.

[0060] In an embodiment, the first DMA engine 1220 may be configured to read read data (i.e., data corresponding to an address included in the read request) from the NVM device 1300 without the control of the CPU 1240 when the storage controller 1200 receives a read request from the host device 10, and store the read data in the buffer memory 1270. After the read data is stored in the buffer memory 1270, the second DMA engine 1260 may be configured to read the read data stored in the buffer memory 1270 without the control of the CPU 1240, and transmit the read data to the host device 10.

[0061] In an embodiment, the first DMA engine 1220 may be configured to read the read data from the NVM device 1300 and transmit the read data to the host device 10 without the control of the CPU 1240 when the storage controller 1200 receives a read request from the host device 10. The first DMA engine 1220 may transmit the read data to a virtual address corresponding to the read data. The address manager 1210 may convert the virtual address into a host address corresponding to the read data and transmit the read data to the host device 10.

[0062] Hereinafter, for the convenience of explanation, the embodiment is described based on a read operation in which the storage device 1100 responds to a read request from the host device 10. In addition, during the read operation, the operation performed by the first DMA engine 1220, i.e., the operation of reading data from the NVM device 1300 and transferring the read data to the virtual address, is referred to as a "first DMA operation". During the read operation, the operation performed by the first DMA engine 1220, i.e., the operation of reading data from the NVM device 1300 and writing the read data to the buffer memory 1270, is referred to as a "second DMA operation". During the read operation, the operation performed by the first DMA engine 1220, i.e., the operation of reading data from the NVM device 1300, transferring the read data to the virtual address, and writing the read data to the buffer memory 1270, is referred to as a "third DMA operation".

[0063] For example, the CPU 1240 may perform initial settings on the first DMA engine 1220 so as to perform the first DMA operation to the third DMA operation. The CPU 1240 may perform initial settings on the second DMA engine 1260 so as to perform the DMA operation. Each of the first DMA engine 1220 and the second DMA engine 1260 may perform DMA operations according to the initial settings of the CPU 1240. For example, the initial settings performed by the CPU 1240 are operations that point to or input or set a target address, address size, input / output (I / O) device, quantity, I / O information, etc. to the first DMA engine 1220 and the second DMA engine 1260.

[0064] The memory controller 1200 may perform initial settings on the first DMA engine 1220 and the second DMA engine 1260 in response to the read request. For example, the CPU 1240 of the memory controller 1200 may perform initial settings on the first DMA engine 1220 and the second DMA engine 1260 for the purpose of DMA operation.

[0065] In an embodiment, the address manager 1210 may generate mode information MINFO and transmit the mode information MINFO to the first DMA engine 1220. The mode information MINFO may indicate information requesting the first DMA engine 1220 to perform one of the first DMA operation to the third DMA operation. For example, the mode information MINFO may indicate one of the first mode M1 to the third mode M3. The first mode M1 may refer to a mode in which the first DMA engine 1220 performs the first DMA operation. The second mode M2 ​​may refer to a mode in which the first DMA engine 1220 performs the second DMA operation. The third mode M3 may refer to a mode in which the first DMA engine 1220 performs the third DMA operation.

[0066] In other words, the first mode M1 may refer to a mode in which the first DMA engine 1220 transfers the read data to the virtual address. That is, the first mode M1 may refer to a mode in which the read data is directly transferred to the host device 10 without passing through the buffer memory 1270. The second mode M2 ​​may refer to a mode in which the first DMA engine 1220 transfers the read data to the buffer memory 1270 (or a mode in which the read data is written to the buffer memory 1270). That is, the second mode M2 ​​may refer to a mode in which the read data is transferred to the host device 10 through the buffer memory 1270. The third mode M3 may refer to a mode in which the first DMA engine 1220 transfers the read data to the virtual address and simultaneously transfers the read data to the buffer memory 1270. That is, the third mode M3 may refer to a mode in which the read data is directly transferred to the host device 10 without passing through the buffer memory 1270 and the data is written to the buffer memory 1270.

[0067] In an embodiment, the ECC engine 1280 may perform an error correction operation on the read data read from the NVM device 1300. The ECC engine 1280 may generate error-corrected read data. The first DMA engine 1220 may transfer the read data to the virtual address. The first DMA engine 1220 may transfer the error-corrected read data to the virtual address. Alternatively, the first DMA engine 1220 may write the error-corrected read data to the buffer memory 1270. That is, the read data transferred by the first DMA engine 1220 may be the read data error-corrected by the ECC engine 1280.

[0068] As described above, the storage controller 1200 may directly transmit the read data stored in the NVM device 1300 to the host device 10 without passing through the buffer memory 1270. In the first mode M1, the storage controller 1200 may not allocate buffer resources for a read request. That is, the storage controller 1200 may not allocate an area of ​​the buffer memory 1270 for a read request. The read latency may not be associated with whether the resources of the buffer memory 1270 are sufficient. A storage device 1100 with reduced read latency and improved performance is provided.

[0069] Figure 3 is a flowchart illustrating an example of an operating method of the memory controller 1200 according to an embodiment.

[0070] refer to Figure 2 and Figure 3 In operation S110, the storage controller 1200 may receive a read request from the host device 10. For example, the read request may include a host address where read data read from the NVM device 1300 is to be stored. The host address may indicate an area of ​​the host memory 12 allocated in association with the read request. The host interface circuit HI may receive a read request including the host address from the host device 10.

[0071] In operation S120, the storage controller 1200 may update the TT. The storage controller 1200 may assign a command identifier to the read request. The storage controller 1200 may store mapping information about the command identifier and the host address in the TT. For example, the address manager 1210 may store mapping information about the host address and the command identifier corresponding to the read request in the TT in response to the read request.

[0072] In operation S130, the storage controller 1200 may perform a DMA operation using a virtual address. The storage controller 1200 may not write the read data read from the NVM device 1300 to the buffer memory 1270. The storage controller 1200 may transfer the read data to the virtual address. That is, the first DMA engine 1220 may set the destination address of the read data corresponding to the read request to the virtual address corresponding to the command identifier, and may transfer the read data corresponding to the read request to the virtual address.

[0073] In operation S140, the storage controller 1200 may perform an address conversion operation. The storage controller 1200 may convert the destination address of the read data from the virtual address to the host address. That is, the address manager 1210 may convert the destination address of the read data from the virtual address to the host address based on the TT. The storage controller 1200 may convert the destination address of the read data to the host address and transmit the read data to the host device 10. The storage controller 1200 may write the read data to the host address.

[0074] Figure 4A and Figure 4B is a diagram for describing an operating method of the memory controller 1200 according to an embodiment.

[0075] In an embodiment, the storage controller 1200 may generate a VLUT in an initialization operation. The storage controller 1200 may assign virtual addresses to command identifiers. Referring to the VLUT, the first command identifier CID1 may correspond to the first virtual address VA1, the second command identifier CID2 may correspond to the second virtual address VA2, the third command identifier CID3 may correspond to the third virtual address VA3, and the fourth command identifier CID4 may correspond to the fourth virtual address VA4.

[0076] refer to Figure 1 , Figure 4A and Figure 4B In operation S201, the host interface circuit HI of the storage controller 1200 may receive a first read request RQ1 from the host device 10. The first read request RQ1 may include a first host address HA1. The first host address HA1 may indicate an address of the host memory 12 where the read data corresponding to the first read request RQ1 is to be stored. For example, the host address may be a physical region page (PRP) address of the NVMe standard protocol.

[0077] In operation S202, the host interface circuit HI may transmit a first command identifier CID1 and a first host address HA1 to the address manager 1210. In an embodiment, the storage controller 1200 may assign a command identifier (or a descriptor, a tag, etc.) to the first read request RQ1. For example, since the command identifiers are respectively assigned to the commands, the command identifiers may be unique information that allows the storage controller 1200 to distinguish between the commands. The storage controller 1200 may assign the first command identifier CID1 to the first read request RQ1. With respect to the first read request RQ1, the host interface circuit HI may transmit the first command identifier CID1 and the first host address HA1 to the address manager 1210.

[0078] In operation S203, the address manager 1210 may update the TT. The TT may include mapping information between the command identifier and the host address. The address manager 1210 may receive the first command identifier CID1 and the first host address HA1. The address manager 1210 may update the TT based on the first command identifier CID1 and the first host address HA1. With respect to the command identifier, the address manager 1210 may store the corresponding host address in the TT. For example, with respect to the first command identifier CID1, the address manager 1210 may store the first host address HA1 in the TT.

[0079] In operation S204, the address manager 1210 may transmit the mode information MINFO to the first DMA engine 1220. The address manager 1210 may generate the mode information MINFO. The address manager 1210 may determine (e.g., select / choose) to process the first read request RQ1 by performing the first DMA operation. For example, when the resources of the buffer memory 1270 are insufficient, the address manager 1210 may instruct the first DMA engine 1220 to perform the first DMA operation.

[0080] The address manager 1210 may generate mode information MINFO indicating the first mode M1 so that the first DMA engine 1220 performs the first DMA operation. The address manager 1210 may transmit the mode information MINFO indicating the first mode M1 to the first DMA engine 1220. For example, the first mode M1 may refer to a mode in which read data is transferred to a virtual address without writing the read data to the buffer memory 1270.

[0081] The first DMA engine 1220 may receive the mode information MINFO. The first DMA engine 1220 may perform a DMA operation based on the mode information MINFO. The first DMA engine 1220 may perform a first DMA operation in response to the mode information MINFO indicating the first mode M1. The first DMA engine 1220 may transfer read data read from the NVM device 1300 to a virtual address.

[0082] In operation S205, the first DMA engine 1220 may receive read data from the NVM interface circuit MI. The first DMA engine 1220 may read read data (ie, first read data RD1) corresponding to the first read request RQ1 from the NVM device 1300 through the NVM interface circuit MI.

[0083] The memory controller 1200 may transmit a read command for reading data corresponding to the first read request RQ1 to the NVM device 1300. The NVM device 1300 may output first read data RD1 to the memory controller 1200 in response to the read command. The memory controller 1200 may receive the first read data RD1.

[0084] In operation S206, the first DMA engine 1220 may refer to the VLUT. The VLUT may include mapping information between the command identifier and the virtual address. Since the mode information MINFO indicates the first mode M1, the first DMA engine 1220 may transfer the first read data RD1 to the virtual address. The first DMA engine 1220 may determine (e.g., identify / select) the virtual address by referring to the VLUT.

[0085] The first DMA engine 1220 may refer to the VLUT based on the command identifier corresponding to the first read data RD1. The first DMA engine 1220 may retrieve a virtual address corresponding to the first command identifier CID1 by referring to the VLUT. The first DMA engine 1220 may retrieve a first virtual address VA1 corresponding to the first command identifier CID1. The first DMA engine 1220 may set the first virtual address VA1 corresponding to the first command identifier CID1 as the destination address of the first read data RD1.

[0086] In operation S207, the first DMA engine 1220 may transfer the read data to the virtual address. The first DMA engine 1220 may transfer the first read data RD1 to the first virtual address VA1. The bus BUS( Figure 2 ) may determine whether the destination address is within the virtual address range. When the destination address is within the virtual address range, the bus BUS may route the packet (or data) to the address manager 1210. The bus BUS may route the first read data RD1 transmitted by the first DMA engine 1220 to the address manager 1210. That is, the first DMA engine 1220 may set the destination address of the first read data RD1 to the first virtual address VA1, and transmit the first read data RD1 to the address manager 1210. The address manager 1210 may receive the first read data RD1.

[0087] In operation S208 ( Figure 4B ), the address manager 1210 may refer to TT. The address manager 1210 may perform an address conversion operation by referring to TT. The address manager 1210 may convert the destination address of the first read data RD1 from a virtual address to a host address by referring to TT. The address manager 1210 may determine the host address by referring to TT.

[0088] The address manager 1210 may refer to TT based on an identifier corresponding to the first read data RD1. The address manager 1210 may retrieve a host address corresponding to the first command identifier CID1 by referring to TT. The address manager 1210 may retrieve a first host address HA1 corresponding to the first command identifier CID1. The address manager 1210 may convert a destination address of the first read data RD1 from the first virtual address VA1 to the first host address HA1.

[0089] In operation S209, the address manager 1210 may transfer the first read data RD1 to the host interface circuit HI. The address manager 1210 may set the destination address of the first read data RD1 to the first host address HA1 and transfer the first read data RD1 to the host interface circuit HI.

[0090] In operation S210, the host interface circuit HI may transmit the read data to the host device 10. The host interface circuit HI may transmit the first read data RD1 to a first host address HA1 indicating an area allocated to the host memory 12.

[0091] As described above, the memory controller 1200 may directly transfer the read data read from the NVM device 1300 to the host device 10 without storing the read data in the buffer memory 1270. The first DMA engine 1220 of the memory controller 1200 may transfer the read data read from the NVM device 1300 to the virtual address, and then, the address manager 1210 may convert the destination address of the read data from the virtual address to the host address and transfer the read data to the host device 10. By bypassing (or bypassing) the buffer memory 1270 and directly transferring the read data read from the NVM device 1300 to the host device 10, the read latency may be reduced and the performance of the memory device 1100 may be improved.

[0092] Figure 5 is a flowchart illustrating an example of an operating method of the memory controller 1200 according to an embodiment.

[0093] refer to Figure 2 , Figure 3 and Figure 5 , in an embodiment, Figure 3 Operation S130 may include operations S131 to S137. Figure 3In operation S120 of , the storage controller 1200 may update TT. Subsequently, in operation S125, the storage controller 1200 may transmit mode information MINFO to the first DMA engine 1220. The storage controller 1200 may determine (e.g., select / select) one of the first to third DMA operations. The storage controller 1200 may generate mode information MINFO indicating one of the first to third modes M1 to M3.

[0094] For example, the memory controller 1200 may determine whether to allow the first DMA engine 1220 to transfer the read data to the virtual address without writing the read data read from the NVM device 1300 to the buffer memory 1270. Alternatively, the memory controller 1200 may determine whether to allow the first DMA engine 1220 to write the read data to the buffer memory 1270, allow the second DMA engine 1260 to read the read data from the buffer memory 1270, and determine whether to transfer the read data to the host device 10. Alternatively, the memory controller 1200 may determine whether to transfer the read data to the virtual address and write the read data to the buffer memory 1270.

[0095] In operation S131, the memory controller 1200 may determine whether the mode information MINFO indicates the first mode M1. When the mode information MINFO indicates the first mode M1, the memory controller 1200 may perform operation S132, and when the mode information MINFO does not indicate the first mode M1, the memory controller 1200 may perform operation S133.

[0096] In operation S132, the storage controller 1200 may transfer the read data to the virtual address. Because the mode information MINFO indicates the first mode M1, the storage controller 1200 may not write the read data to the buffer memory 1270. The storage controller 1200 may retrieve the virtual address corresponding to the command identifier by referring to the virtual lookup table VLUT. The storage controller 1200 may transfer the read data to the virtual address corresponding to the command identifier. Subsequently, the storage controller 1200 may perform operation S140. The storage controller 1200 may perform an address conversion operation and transfer the read data to the host address.

[0097] In operation S133, the memory controller 1200 may determine whether the mode information MINFO indicates the second mode M2. When the mode information MINFO indicates the second mode M2, the memory controller 1200 may perform operation S134, and when the mode information MINFO does not indicate the second mode M2, the memory controller 1200 may perform operation S135.

[0098] In operation S134, the memory controller 1200 may transfer the read data to the buffer memory 1270. The memory controller 1200 may transfer the read data to the physical address of the buffer memory 1270. The memory controller 1200 may transfer the read data to the area of ​​the buffer memory 1270 allocated for read data. The memory controller 1200 may write the read data to the buffer memory 1270. Subsequently, the second DMA engine 1260 of the memory controller 1200 may read the read data from the buffer memory 1270. The second DMA engine 1260 may transfer the read data to the host address. The second DMA engine 1260 may transfer the read data to the host device 10.

[0099] In operation S135, the memory controller 1200 may determine whether the mode information MINFO indicates the third mode M3. When the mode information MINFO indicates the third mode M3, the memory controller 1200 may perform operation S136, and when the mode information MINFO does not indicate the third mode M3, the memory controller 1200 may perform operation S137.

[0100] In operation S136, the memory controller 1200 may transfer the read data to the virtual address and transfer the read data to the buffer memory 1270. Because the mode information MINFO indicates the third mode M3, the memory controller 1200 may write the read data to the buffer memory 1270 and transfer the read data to the virtual address. In order to reduce the delay of the read request, the memory controller 1200 may transfer the read data to the virtual address. In order to reduce the expected delay of the read request, the memory controller 1200 may transfer the read data to the buffer memory 1270.

[0101] The host device 10 may repeatedly request to read data for the same address. When the read request for the same address is repeated, the storage device 1100 may write the data corresponding to the read request to the buffer memory 1270 to improve the hit rate. The storage device 1100 may provide the data stored in the buffer memory 1270 to the host device 10 in response to the new read request. Instead of reading data from the NVM device 1300 and providing the read data to the host device 10, the storage device 1100 may directly provide the data stored in the buffer memory 1270 to the host device 10. Therefore, the storage device 1100 can reduce the read latency.

[0102] The memory controller 1200 may perform operation S140 after operation S136. The memory controller 1200 may perform an address conversion operation and transfer the read data to the host address. In operation S137, the memory controller 1200 may process an error. Since the mode information MINFO indicates an invalid mode, the error may be processed.

[0103] As described above, the first DMA engine 1220 may determine which mode among the first to third modes M1 to M3 the mode information MINFO indicates. When the first DMA engine 1220 determines that the mode information MINFO indicates the first mode M1, the first DMA engine 1220 may set the destination address of the read data to the virtual address corresponding to the command identifier, and transfer the read data to the virtual address. When the first DMA engine 1220 determines that the mode information MINFO indicates the second mode M2, the first DMA engine 1220 may set the destination address of the read data to the address of the buffer memory 1270, and transfer the read data to the address of the buffer memory 1270. When the first DMA engine 1220 determines that the mode information MINFO indicates the third mode M3, the first DMA engine 1220 may transfer the read data to the virtual address and transfer the read data to the address of the buffer memory 1270.

[0104] Fig. 6A and Figure 6B is a diagram for describing an operating method of the memory controller 1200 according to an embodiment.

[0105] refer to Figure 2 , Fig. 6A and Figure 6B In operation S301, the memory controller 1200 may receive a second read request RQ2. The host interface circuit HI may receive the second read request RQ2. The second read request RQ2 may include a second host address HA2.

[0106] In operation S302, the host interface circuit HI may transmit the second command identifier CID2 and the second host address HA2 to the address manager 1210. The memory controller 1200 may assign the second command identifier CID2 to the second read request RQ2. The host interface circuit HI may transmit the second command identifier CID2 and the second host address HA2 to the address manager 1210.

[0107] In an embodiment, the host interface circuit HI may transmit only the second command identifier CID2 to the address manager 1210. The address manager 1210 may retrieve the host address corresponding to the second command identifier CID2 by referring to a descriptor table (not shown). The address manager 1210 may determine the host address corresponding to the second read request RQ2 in the descriptor table based on the second command identifier CID2. The address manager 1210 may retrieve the second host address HA2 in the descriptor table.

[0108] In operation S303, the address manager 1210 may update TT. The address manager 1210 may receive a second command identifier CID2 and a second host address HA2. The address manager 1210 may update TT based on the second command identifier CID2 and the second host address HA2. Regarding the second command identifier CID2, the address manager 1210 may store the second host address HA2 in TT.

[0109] In an embodiment, the address manager 1210 may omit operation S303. The address manager 1210 may not perform operation S303. When the address manager 1210 determines to process the second read request RQ2 by performing the second DMA operation, the address manager 1210 may not perform operation S303.

[0110] In operation S304, the address manager 1210 may transmit mode information MINFO to the first DMA engine 1220. The address manager 1210 may determine / select to process the second read request RQ2 by performing the second DMA operation. The address manager 1210 may generate mode information MINFO indicating the second mode M2 ​​so that the first DMA engine 1220 performs the second DMA operation. The address manager 1210 may transmit mode information MINFO indicating the second mode M2 ​​to the first DMA engine 1220. The second mode M2 ​​may refer to a mode in which read data is written to the buffer memory 1270.

[0111] The first DMA engine 1220 may receive the mode information MINFO indicating the second mode M2. The first DMA engine 1220 may perform the second DMA operation in response to the mode information MINFO indicating the second mode M2. The first DMA engine 1220 may transfer the read data read from the NVM device 1300 to the buffer memory 1270.

[0112] In operation S305, the first DMA engine 1220 may receive read data from the NVM interface circuit MI. The first DMA engine 1220 may read read data corresponding to the second read request RQ2 (ie, second read data RD2) from the NVM device 1300 through the NVM interface circuit MI.

[0113] In operation S306, the first DMA engine 1220 may transfer the second read data RD2 to the buffer memory 1270. The first DMA engine 1220 may write the second read data RD2 to an area allocated to the buffer memory 1270. The first DMA engine 1220 may transfer the second read data RD2 to a physical address of the buffer memory 1270.

[0114] In operation S307 ( Figure 6B), the second DMA engine 1260 may read (eg, load) the second read data RD2 from the buffer memory 1270. The second DMA engine 1260 may read the second read data RD2 stored in the buffer memory 1270. The second DMA engine 1260 may receive the second read data RD2 from the buffer memory 1270.

[0115] In operation S308, the second DMA engine 1260 may transfer the second read data RD2 to the host interface circuit HI. The second DMA engine 1260 may set the destination address of the second read data RD2 to the second host address HA2 and transfer the second read data RD2 to the host interface circuit HI.

[0116] In operation S309, the host interface circuit HI may transmit the second read data RD2 to the host device 10. The host interface circuit HI may transmit the second read data RD2 to a second host address HA2 indicating an area allocated to the host memory 12.

[0117] As described above, the memory controller 1200 may process the read request by performing the second DMA operation. That is, in the second mode M2, the memory controller 1200 may write the read data read from the NVM device 1300 to the buffer memory 1270, may read the read data stored in the buffer memory 1270, and may transmit the read data to the host device 10.

[0118] Compared with the first mode M1, in the second mode M2, the memory controller 1200 may additionally perform an operation of writing data to the buffer memory 1270 and an operation of reading data from the buffer memory 1270. That is, the read latency in the second mode M2 ​​may be greater than the read latency in the first mode M1. In the second mode M2, the read latency of the read request may also include the time to write data to the buffer memory 1270 and the time to read data from the buffer memory 1270.

[0119] In addition, the storage controller 1200 may allocate an area of ​​the buffer memory 1270 to a read request (or a command identifier). Because the capacity of the buffer memory 1270 is limited, it may take time to allocate an area of ​​the buffer memory 1270 for a new read request. Before available resources (e.g., the buffer memory 1270) are ensured, read latency may increase and performance may deteriorate.

[0120] Fig. 7A and Figure 7B is a diagram for describing an operating method of the memory controller 1200 according to an embodiment.

[0121] refer to Figure 2 , Fig. 7A and Figure 7B In operation S401, the memory controller 1200 may receive a third read request RQ3. The host interface circuit HI may receive the third read request RQ3. The third read request RQ3 may include a third host address HA3.

[0122] In operation S403, the host interface circuit HI may transmit the third command identifier CID3 and the third host address HA3 to the address manager 1210. The memory controller 1200 may assign the third command identifier CID3 to the third read request RQ3. The host interface circuit HI may transmit the third command identifier CID3 and the third host address HA3 to the address manager 1210.

[0123] In operation S403, the address manager 1210 may update TT. The address manager 1210 may receive a third command identifier CID3 and a third host address HA3. The address manager 1210 may update TT based on the third command identifier CID3 and the third host address HA3. Regarding the third command identifier CID3, the address manager 1210 may store the third host address HA3 in TT.

[0124] In operation S404, the address manager 1210 may transmit mode information MINFO to the first DMA engine 1220. The address manager 1210 may determine (e.g., select / choose) to process the third read request RQ3 by performing the third DMA operation. The address manager 1210 may generate mode information MINFO indicating the third mode M3 so that the first DMA engine 1220 performs the third DMA operation. The address manager 1210 may transmit mode information MINFO indicating the third mode M3 to the first DMA engine 1220. The third mode M3 may refer to a mode in which read data is transferred to a virtual address and the read data is written to the buffer memory 1270.

[0125] The first DMA engine 1220 may receive mode information MINFO indicating the third mode M3. The first DMA engine 1220 may perform a third DMA operation in response to the mode information MINFO indicating the third mode M3. The first DMA engine 1220 may transfer read data read from the NVM device 1300 to the virtual address and transfer the read data to the buffer memory 1270.

[0126] In operation S405, the first DMA engine 1220 may receive read data from the NVM interface circuit MI. The first DMA engine 1220 may read read data corresponding to the third read request RQ3 (ie, third read data RD3) from the NVM device 1300 through the NVM interface circuit MI.

[0127] In operation S406, the first DMA engine 1220 may refer to the VLUT. Since the mode information MINFO indicates the third mode M3, the first DMA engine 1220 may transfer the third read data RD3 to the virtual address. The first DMA engine 1220 may determine the virtual address by referring to the VLUT. The first DMA engine 1220 may retrieve the third virtual address VA3 corresponding to the third command identifier CID3 by referring to the VLUT. The first DMA engine 1220 may set the third virtual address VA3 corresponding to the third command identifier CID3 as the destination address of the third read data RD3.

[0128] In operation S407, the first DMA engine 1220 may transfer the read data to the virtual address. The first DMA engine 1220 may transfer the third read data RD3 to the third virtual address VA3. Because the third virtual address is included in the virtual address range, the bus BUS may route the third read data RD3 to the address manager 1210. That is, the first DMA engine 1220 may set the destination address of the third read data RD3 to the third virtual address VA3, and transfer the third read data RD3 to the address manager 1210. The address manager 1210 may receive the third read data RD3.

[0129] In operation S408, the first DMA engine 1220 may transfer the third read data RD3 to the buffer memory 1270. The first DMA engine 1220 may write the third read data RD3 to a region allocated to the buffer memory 1270. The first DMA engine 1220 may transfer the third read data RD3 to a physical address of the buffer memory 1270.

[0130] For simplicity of the drawings and convenience of explanation, operation S407 is illustrated as being performed before operation S408, but the scope of the inventive concept is not limited thereto. The operations may be performed simultaneously or in a different order.

[0131] In operation S409 ( Figure 7B ), the address manager 1210 may refer to TT. The address manager 1210 may perform an address conversion operation by referring to TT. The address manager 1210 may convert a destination address of the third read data RD3 from the third virtual address VA3 to the third host address HA3 by referring to TT.

[0132] In operation S410, the address manager 1210 may transmit the third read data RD3 to the host interface circuit HI. The address manager 1210 may set the destination address of the third read data RD3 to the third host address HA3 and transmit the third read data RD3 to the host interface circuit HI.

[0133] In operation S411, the host interface circuit HI may transmit the read data to the host device 10. The host interface circuit HI may transmit the third read data RD3 to a third host address HA3 indicating an area allocated to the host memory 12.

[0134] As described above, the memory controller 1200 can process the read request by performing the third DMA operation. That is, in the third mode M3, the memory controller 1200 can directly transfer the read data to the host device 10 without passing through the buffer memory 1270. At the same time, the memory controller 1200 can store the read data in the buffer memory 1270. Therefore, the memory controller 1200 can increase the hit rate of the host device 10 that repeatedly requests read data for the same address. A memory device with reduced read latency and improved performance is provided.

[0135] Figure 8 is a flowchart illustrating an example of an operating method of the memory controller 1200 according to an embodiment.

[0136] refer to Figure 2 and Figure 8 In operation S510, the memory controller 1200 may receive a read request from the host device 10. In operation S520, the memory controller 1200 may update TT. Because operations S510 and S520 are similar to Figure 3 Operations S110 and S120 are described in detail, so their detailed description is omitted.

[0137] In operation S530, the storage controller 1200 (e.g., cache manager 1230) may determine whether a cache hit has occurred. For example, the storage controller 1200 may determine whether data corresponding to a read request exists in a cache (or cache memory). A cache hit may refer to a situation where read data corresponding to a read request exists in a cache. A cache miss may refer to a situation where read data corresponding to a read request does not exist in a cache. When the storage controller 1200 determines that a cache hit has occurred, the storage controller 1200 may perform operation S540, and when the storage controller 1200 determines that a cache miss has occurred, the storage controller 1200 may perform operation S550.

[0138] In operation S540, the memory controller 1200 may read data from the cache. The memory controller 1200 (e.g., the cache manager 1230) may load the data stored in the cache. In an embodiment, the memory controller 1200 may determine whether the read data is cached in the sub-buffer. When the read data is cached in the sub-buffer, the memory controller 1200 may load the read data from the sub-buffer.

[0139] In an embodiment, memory controller 1200 may determine whether the read data is cached in latch 1331 of NVM device 1300. When the read data is cached in NVM device 1300, memory controller 1200 may load the read data from NVM device 1300.

[0140] In operation S550, the memory controller 1200 may read data from the NVM device 1300. The memory controller 1200 (e.g., the NVM interface circuit MI) may read data from the memory cell array of the NVM device 1300. The memory controller 1200 may receive the read data after a reference time (tR) has passed from a time point when a read command is transmitted to the NVM device 1300.

[0141] In operation S560, the memory controller 1200 may perform a DMA operation using a virtual address. In operation S570, the memory controller 1200 may perform an address conversion operation. Because operations S560 and S570 are similar to Figure 3 Operations S130 and S140 are described in detail, so a detailed description thereof is omitted.

[0142] As described above, the memory controller 1200 may implement caching using the sub-buffer and the latch 1331 of the NVM device 1300. When the memory controller 1200 determines that a cache hit has occurred, the memory controller 1200 may load data from the cache in response to a read request. Thus, a memory device 1100 having reduced read latency and improved performance is provided.

[0143] Fig. 9 is a flowchart illustrating an example of an operating method of the memory controller 1200 according to an embodiment.

[0144] refer to Figure 2 , Figure 8 and Fig. 9, in operation S520, the storage controller 1200 may update TT. In operation S530, the storage controller 1200 may determine whether a cache hit has occurred. For example, the cache manager 1230 may determine whether data exists in the cache memory. When the storage controller 1200 determines that a cache hit has occurred, the storage controller 1200 may perform operation S541, and when the storage controller 1200 determines that a cache miss has occurred, the storage controller 1200 may perform operation S551. In an embodiment, operation S540 may include operations S541 to S545, and operation S550 may include operations S551 and S552.

[0145] In operation S541, the memory controller 1200 may determine whether the read data is stored in a sub-buffer of the memory controller 1200. The cache manager 1230 may determine whether the read data is cached in the sub-buffer. The sub-buffer may be a memory other than a cache memory.

[0146] In an embodiment, the storage controller 1200 may further include a sub-buffer. It is assumed that the sub-buffer is an SRAM. However, the scope of the inventive concept is not limited thereto. For example, the sub-buffer memory may include a high-speed RAM such as a DRAM or an SDRAM. Alternatively, the buffer memory 1270 may include an NVM such as a ROM, a PROM, an EPROM, an EEPROM, a flash memory, a PRAM, an MRAM, an RRAM, a FRAM, or a TRAM. For example, the sub-buffer may be a memory used by the ECC engine 1280. The sub-buffer may be an LDPC SRAM.

[0147] When the memory controller 1200 determines that the read data is stored (eg, cached) in the sub-buffer, the memory controller 1200 may perform operation S542 , and when the memory controller 1200 determines that the read data is not stored in the sub-buffer, the memory controller 1200 may perform operation S543 .

[0148] In operation S542, the memory controller 1200 may load the read data from the sub-buffer. The memory controller 1200 may not transmit the read command to the NVM device 1300. The memory controller 1200 may not receive the read data from the NVM device 1300. The memory controller 1200 may read the read data stored in the sub-buffer. Subsequently, the memory controller 1200 may perform operation S560.

[0149] In operation S543, the memory controller 1200 may determine whether data is stored in the latch 1331 of the NVM device 1300. When the memory controller 1200 determines that the read data is stored in the latch 1331, the memory controller 1200 may perform operation S544.

[0150] In operation S544, the memory controller 1200 may transmit a random data output command to the NVM device 1300. The memory controller 1200 may read the data stored in the latch 1331 by transmitting the random data output command instead of the read command.

[0151] In operation S545, the memory controller 1200 may receive read data from the NVM device 1300. The NVM device 1300 may output the read data stored in the latch 1331 in response to the random data output command. The memory controller 1200 may receive data stored in the latch 1331 before the reference time (tR) from the NVM device 1300.

[0152] In operation S551, the storage controller 1200 (e.g., the NVM interface circuit MI) may transmit a read command to the NVM device 1300. In operation S552, the storage controller 1200 (e.g., the NVM interface circuit MI) may receive read data from the NVM device 1300. The NVM device 1300 may read the read data from the memory cell array in response to the read command. The NVM device 1300 may output the read data to the storage controller 1200. The NVM device 1300 may transmit the read data to the storage controller 1200 after a reference time (tR) from a time point of receiving the read command.

[0153] As described above, the storage controller 1200 may configure a cache and load read data from the cache. When the storage controller 1200 determines that a cache hit has occurred, the storage controller 1200 may load read data from the cache and transmit the read data to the host device 10. The storage controller 1200 may load read data from the cache instead of reading the read data from the memory cell array of the NVM device 1300. The storage controller 1200 may load read data in a time less than the reference time (tR). Therefore, a storage device 1100 having reduced read latency and improved performance is provided.

[0154] Fig.10 is a block diagram illustrating an example of an NVM device 1300 according to an embodiment.

[0155] refer to Figure 1 and Fig.10 , the NVM device 1300 may include a memory cell array 1310 , an address decoder 1320 , a page buffer circuit 1330 , an I / O circuit 1340 , and a control logic circuit 1350 .

[0156] The memory cell array 1310 may include a plurality of memory blocks. Each of the memory blocks may include a plurality of cell strings. Each of the cell strings may include a plurality of cell transistors connected in series between a bit line and a common source line. The cell transistors may be connected to a string selection line SSL, a word line WL, and a ground selection line GSL. Each of the cell transistors (e.g., memory cells) may be configured to store at least 1 bit of data according to a programming operation of the NVM device 1300.

[0157] The address decoder 1320 may be connected to the memory cell array 1310 through the string selection line SSL, the word line WL, and the ground selection line GSL. The address decoder 1320 may decode an address received from the memory controller 1200 and control voltages of the string selection line SSL, the word line WL, and the ground selection line GSL based on the decoded address.

[0158] The page buffer circuit 1330 may be connected to the memory cell array 1310 through a plurality of bit lines BL. The page buffer circuit 1330 may be configured to temporarily store data read from the memory cell array 1310 or data provided from the I / O circuit 1340. Although not shown, the page buffer circuit 1330 may include a plurality of page buffers corresponding to the bit lines BL, respectively. Each of the page buffers may include a latch 1331 (e.g., a data latch or a cache latch) configured to temporarily store data.

[0159] The I / O circuit 1340 may be connected to the page buffer circuit 1330 through a plurality of data lines DL. The data lines DL may be connected to or correspond to the above-mentioned page buffers, respectively. The I / O circuit 1340 may exchange data with the memory controller 1200 through a plurality of data (DQ) lines DQ.

[0160] The control logic circuit 1350 may control the overall operation of the NVM device 1300 . For example, the control logic circuit 1350 may be configured to control the address decoder 1320 , the page buffer circuit 1330 , and the I / O circuit 1340 in response to a control signal CTRL from the memory controller 1200 .

[0161] The NVM device 1300 may read data corresponding to the received address from the memory cell array 1310 in response to the read command. For example, the NVM device 1300 may read data corresponding to the received address from the memory cell array 1310 and prepare the read data in the I / O circuit 1340. The above-mentioned data preparation operation may be performed during a reference time (e.g., tR). For example, within the reference time (tR), the NVM device 1300 may provide a ready / busy signal (R / B) of a logic low (i.e., a busy state) to the memory controller 1200.

[0162] In other words, the memory controller 1200 may transmit a read command to the NVM device 1300 and receive read data from the NVM device 1300 after the reference time (tR) has elapsed. On the other hand, the memory controller 1200 may transmit a random data output (or random data read) command to the NVM device 1300 and receive read data from the NVM device 1300 before the reference time (tR) has elapsed.

[0163] In the case of a cache hit, NVM device 1300 may not read data from memory cell array 1310 because the read data is already stored in latch 1331. NVM device 1300 may transfer the read data stored in latch 1331 to memory controller 1200 without performing a data preparation operation. In the case of a cache hit, read latency may be reduced by using a random data output command instead of a read command.

[0164] Fig.11 is a block diagram illustrating a solid state drive (SSD) system 2000 to which a storage device according to an embodiment is applied.

[0165] refer to Fig.11 , the SSD system 2000 may include a host 2100 and an SSD 2200. The SSD 2200 may exchange a signal SIG with the host 2100 through a signal connector 2201, and receive power PWR through a power connector 2202. The SSD 2200 may include an SSD controller 2210, a plurality of flash memories 2221 to 222n, an auxiliary power supply 2230, and a buffer memory 2240.

[0166] The SSD controller 2210 may control the flash memories 2221 to 222n in response to a signal SIG received from the host 2100. The flash memories 2221 to 222n may operate under the control of the SSD controller 2210. The auxiliary power supply 2230 may be connected to the host 2100 through the power connector 2202. The auxiliary power supply 2230 may receive power PWR from the host 2100 and may be charged with the power PWR. When the power supply from the host 2100 is not stable, the auxiliary power supply 2230 may provide power to the SSD 2200. The buffer memory 2240 may work as a buffer memory of the SSD 2200.

[0167] For example, the SSD controller 2210 may include an address manager, a first DMA engine, and a cache manager, as shown in FIG. Figures 1 to 10The SSD controller 2210 may perform the first to third DMA operations based on the read data received from the flash memories 2221 to 222n. The SSD controller 2210 may implement cache using the sub-buffers and latches of the flash memories 2221 to 222n. In the case of a cache hit, the SSD controller 2210 may load data from the cache and provide the data to the host 2100.

[0168] Fig.12 is a diagram showing a data center 3000 to which a storage device according to an embodiment is applied.

[0169] refer to Fig.12 , the data center 3000 is a facility that collects various types of data and provides services, and may also be referred to as a data storage center. The data center 3000 may be a system for running a search engine and a database, or may be a computing system for a company or government agency such as a bank. The data center 3000 may include application servers 3100 to 3100n and storage servers 3200 to 3200m. The number of application servers 3100 to 3100n and the number of storage servers 3200 to 3200m may be selected differently according to the embodiment, and the number of application servers 3100 to 3100n and the number of storage servers 3200 to 3200m may be different from each other.

[0170] The application server 3100 or the storage server 3200 may include at least one processor 3110 or 3210 and one memory 3120 or 3220. For example, in the case of the storage server 3200, the processor 3210 may control the overall operation of the storage server 3200 and may access the memory 3220 to run instructions and / or data loaded into the memory 3220. The memory 3220 may include a double data rate synchronous DRAM (DDR SDRAM), a high bandwidth memory (HBM), a hybrid memory cube (HMC), a dual in-line memory module (DIMM), an Optane DIMM, and / or a non-volatile DIMM (NVMDIMM). In some embodiments, the number of processors 3210 and memories 3220 included in the storage server 3200 may be selected differently. In an embodiment, the processor 3210 and the memory 3220 may provide a processor-memory pair. In an embodiment, the number of processors 3210 and the number of memories 3220 may be different from each other. The processor 3210 may include a single-core processor or a multi-core processor. The above description of the storage server 3200 may be similarly applied to the application server 3100. In some embodiments, the application server 3100 may not include the storage device 3150. The storage server 3200 may include at least one storage device 3250. The number of storage devices 3250 included in the storage server 3200 may be variously selected according to embodiments.

[0171] Application servers 3100 to 3100n and storage servers 3200 to 3200m can communicate with each other via network 3300. Network 3300 can be implemented by using Fibre Channel (FC) or Ethernet. In this case, FC is a medium for relatively high-speed data transmission, and an optical switch providing high performance and high availability can be used. According to the access method of network 3300, storage servers 3200 to 3200m can be provided as file storage devices, block storage devices, or object storage devices.

[0172] In an embodiment, the network 3300 may be a storage-only network, such as a storage area network (SAN). For example, the SAN may be a Fibre Channel (FC)-SAN implemented using a FC network and according to a FC protocol (FCP). As another example, the SAN may be an Internet Protocol (IP)-SAN implemented using a Transmission Control Protocol (TCP) / IP network and according to a Small Computer Small Interface (SCSI) or Internet SCSI (iSCSI) protocol based on TCP / IP. In another embodiment, the network 3300 may be a general-purpose network, such as a TCP / IP network. For example, the network 3300 may be implemented according to protocols such as FC over ethernet (FCoE), network attached storage (NAS), and NVMe over fabrics (NVMe-oF) based on fiber.

[0173] The following description focuses on the application server 3100 and the storage server 3200. The description of the application server 3100 may also be applied to another application server 3100n, and the description of the storage server 3200 may also be applied to another storage server 3200m.

[0174] The application server 3100 may store data requested by a user or client to be stored in one of the storage servers 3200 to 3200m via the network 3300. In addition, the application server 3100 may obtain data requested to be read by a user or client from one of the storage servers 3200 to 3200m via the network 3300. For example, the application server 3100 may be implemented as a network server or a database management system (DBMS).

[0175] The application server 3100 may access a memory 3120n or a storage device 3150n included in another application server 3100n via the network 3300, and / or may access a memory 3220 to 3220m or a storage device 3250 to 3250m included in the storage servers 3200 to 3200m via the network 3300. Therefore, the application server 3100 may perform various operations on the data stored in the application servers 3100 to 3100n and / or the storage servers 3200 to 3200m. For example, the application server 3100 may execute a command for moving or copying data between the application servers 3100 to 3100n and / or the storage servers 3200 to 3200m. In this case, the data may be moved from the storage devices 3250 to 3250m of the storage servers 3200 to 3200m to the application servers 3100 to 3100n through the memories 3220 to 3220m of the storage servers 3200 to 3200m, or may be moved directly from the storage devices 3250 to 3250m of the storage servers 3200 to 3200m to the application servers 3100 to 3100n. For security or privacy considerations, the data moved via the network 3300 may be encrypted data.

[0176] The storage server 3200 is described as an example. The interface 3254 can provide a physical connection between the processor 3210 and the controller 3251 and a physical connection between the network interconnect (NIC) 3240 and the controller 3251. For example, the interface 3254 can be implemented in a direct attached storage (DAS) method of directly connecting the storage device 3250 to a dedicated cable. In addition, for example, the interface 3254 can be implemented in various interface methods, such as advanced technology attachment (ATA), serial ATA (SATA), external SATA (e-SATA), SCSI, serial attached SCSI (SAS), peripheral component interconnect (PCI), PCI Express (PCIe), NVM Express (NVMexpress, NVMe), IEEE 1394, Universal Serial Bus (USB), secure digital (SD) card, multimedia card (MMC), embedded multimedia card (eMMC), universal flash storage (UFS), embedded universal flash storage (eUFS), and / or compact flash (CF) card interface.

[0177] The storage server 3200 may further include a switch 3230 and a NIC 3240. The switch 3230 may selectively connect the processor 3210 to the storage device 3250 under the control of the processor 3210, or selectively connect the NIC 3240 to the storage device 3250.

[0178] In an embodiment, the NIC 3240 may include a network interface card, a network adapter, etc. The NIC 3240 may be connected to the network 3300 through a wired interface, a wireless interface, a Bluetooth interface, an optical interface, etc. The NIC 3240 may include an internal memory, a digital signal processor (DSP), a host bus interface, etc., and may be connected to the processor 3210 and / or the switch 3230 through the host bus interface. The host bus interface may be implemented as one of the examples of the interface 3254 described above. In an embodiment, the NIC 3240 may be integrated with at least one of the processor 3210, the switch 3230, and the storage device 3250.

[0179] In the storage servers 3200 to 3200m or the application servers 3100 to 3100n, the processor may program or read data by transmitting commands to the storage devices 3150 to 3150n and 3250 to 3250m or the memories 3120 to 3120n and 3220 to 3220m. In this case, the data may be data whose errors are corrected by the ECC engine. The data is data that has been processed by data bus inversion (DBI) or data mask (DM), and may include cyclic redundancy code (CRC) information. For security or privacy, the data may be encrypted.

[0180] The storage devices 3150 to 3150n and 3250 to 3250m can transmit control signals and command / address signals to the NAND flash memory devices 3252 to 3252m in response to the read commands received from the processors 3110 to 3110n and 3210 to 3210m. Therefore, when reading data from the NAND flash memory devices 3252 to 3252m, a read enable (RE) signal can be input as a data output control signal and used to output data to the DQ bus. Data strobe (DQS) can be generated by using the RE signal. According to the rising edge or falling edge of the write enable (WE) signal, the command and address signals can be latched in the page buffer.

[0181] The controller 3251 may control the overall operation of the storage device 3250. In an embodiment, the controller 3251 may include an SRAM. The controller 3251 may write data to the NAND flash memory device 3252 in response to a write command, or may read data from the NAND flash memory device 3252 in response to a read command. For example, a write command and / or a read command may be provided from the processor 3210 of the storage server 3200, the processor 3210m of the storage server 3200m, or the processors 3110 and 3110n of the application servers 3100 and 3100n. The DRAM 3253 may temporarily store (buffer) data to be written to the NAND flash memory device 3252 or data read from the NAND flash memory device 3252. In addition, the DRAM 3253 may store metadata. The metadata is generated by the controller 3251 in order to manage user data or data of the NAND flash memory device 3252. The storage device 3250 may include a security element (SE) for security or privacy.

[0182] In an embodiment, the storage devices 3150 to 3150n and 3250 to 3250m may include reference Figures 1 to 11 The storage devices 3150 to 3150n and 3250 to 3250m may perform the first DMA operation to the third DMA operation, as described in reference Figures 1 to 11 described.

[0183] In an embodiment, the storage devices 3150 to 3150n and 3250 to 3250m may directly transfer read data read from the NVM device to the outside (i.e., a device outside the application servers 3100 to 3100n and the storage servers 3200 to 3200m) without writing the data to the buffer memory. The storage devices 3150 to 3150n and 3250 to 3250m may transfer the read data to the address manager using a virtual address without writing the data to the buffer memory. The storage devices 3150 to 3150n and 3250 to 3250m may perform an address conversion operation to convert the virtual address to a host address.

[0184] Although the embodiments have been described based on the read operation of the storage device, the scope of the inventive concept is not limited thereto. For example, during the write operation of the storage device, the write data may be directly transmitted to the NVM device without being stored in the buffer memory. The storage controller may use a virtual address to transmit the write data directly to the NVM device without writing the data to the buffer memory.

[0185] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the scope of the appended claims.

Claims

1. An operating method of a storage controller, wherein the storage controller includes a buffer memory, an address manager and a DMA engine and controls a non-volatile memory device, wherein the DMA engine is a direct memory access engine, and the operating method comprises: receiving a read request including a host address from an external host device; storing, by the address manager in response to the read request, mapping information about the host address and a command identifier corresponding to the read request in a conversion table; setting, by the DMA engine, a destination address of read data corresponding to the read request to a virtual address corresponding to the command identifier, and transferring the read data to the virtual address; as well as The destination address of the read data is converted from the virtual address to the host address by the address manager based on the conversion table. 2 . The operating method according to claim 1 , further comprising transmitting the read data to the host address of the external host device.

3. The operating method according to claim 1, further comprising transmitting, by the address manager, mode information indicating the first mode to the DMA engine, in, The first mode is a mode in which the read data is transferred to the virtual address without writing the read data to the buffer memory.

4. The operating method according to claim 3, wherein: Setting, by the DMA engine, the destination address of the read data corresponding to the read request to the virtual address corresponding to the command identifier and transferring the read data to the virtual address comprises: determining the virtual address by referencing a lookup table that maps the command identifier to the virtual address; determining whether the mode information indicates the first mode, the second mode, or the third mode; In response to determining that the mode information indicates the first mode, setting the destination address of the read data to the virtual address corresponding to the command identifier and transferring the read data to the virtual address; and in response to determining that the mode information indicates the second mode, setting the destination address of the read data to an address of the buffer memory and transferring the read data to the address of the buffer memory, The second mode is a mode for writing the read data into the buffer memory.

5. The operating method according to claim 1, further comprising transmitting, by the address manager, mode information indicating a third mode to the DMA engine, in, The third mode is a mode of transferring the read data to the virtual address and writing the read data to the buffer memory.

6. The operating method according to claim 5, wherein: Setting, by the DMA engine, the destination address of the read data corresponding to the read request to the virtual address corresponding to the command identifier and transferring the read data to the virtual address comprises: determining whether the mode information indicates the third mode; and In response to determining that the mode information indicates the third mode, the read data is transferred to the virtual address and the read data is transferred to the address of the buffer memory.

7. The operating method according to claim 1, further comprising: transmitting a read command to the nonvolatile memory device; as well as In response to transmitting the read command, the read data is received from the nonvolatile memory device.

8. The operating method according to claim 1, further comprising: Determine whether a cache hit has occurred; In response to determining that the cache hit has occurred, loading the read data from a cache memory; as well as In response to determining that a cache miss has occurred, the read data is read from a memory cell array of the nonvolatile memory device.

9. The operating method according to claim 8, wherein: In response to determining that the cache hit has occurred, loading the read data from the cache memory includes: determining whether the read data is cached in a sub-buffer; and In response to determining that the read data is cached in the sub-buffer, loading the read data from the sub-buffer, The sub-buffer is a memory used by an error correction code engine.

10. The operating method according to claim 9, wherein: In response to determining that the cache hit has occurred, loading the read data from the cache memory further comprises: determining whether the read data is cached in a latch of the nonvolatile memory device; and In response to determining that the read data is cached in the latch of the nonvolatile memory device, the read data is loaded from the latch of the nonvolatile memory device.

11. The operating method according to claim 10, wherein: Loading the read data from the latch of the non-volatile memory device comprises: transmitting a random data output command to the non-volatile memory device; and The read data is received from the non-volatile memory device.

12. A method for operating a storage device, the storage device comprising a non-volatile memory device and a storage controller, the storage controller comprising a host interface circuit, an address manager, a DMA engine and a non-volatile memory interface circuit and controlling the non-volatile memory device, the DMA engine being a direct memory access engine, the method comprising: receiving, by the host interface circuit, a read request including a host address from an external host device; storing, by the address manager, mapping information about the host address and a command identifier corresponding to the read request received from the host interface circuit in a translation table; The address manager generates mode information and transmits the mode information to the DMA engine; Setting, by the DMA engine, a destination address of read data as a virtual address based on the mode information and transferring the read data to the virtual address; converting, by the address manager, the destination address of the read data from the virtual address to the host address; as well as The read data is transmitted by the host interface circuit to the host address.

13. The operating method according to claim 12, further comprising: transmitting a read command from the nonvolatile memory interface circuit to the nonvolatile memory device; as well as The read data is output by the nonvolatile memory device to the nonvolatile memory interface circuit in response to the read command.

14. The operating method according to claim 12, further comprising: When the mode information indicates the first mode, the DMA engine transfers the read data to the virtual address; When the mode information indicates the second mode, the DMA engine writes the read data to the buffer memory of the storage controller; as well as When the mode information indicates a third mode, the DMA engine transfers the read data to the virtual address and writes the read data to the buffer memory.

15. The operating method according to claim 14, in, The DMA engine is a first DMA engine, and The operation method further includes: When the mode information indicates the second mode, loading the read data from the buffer memory by a second DMA engine included in the storage controller; and The read data loaded from the buffer memory is transferred to the host address by the second DMA engine.

16. The operating method according to claim 12, further comprising: determining, by a cache manager included in the storage controller, whether a cache hit has occurred; In response to determining that the cache hit has occurred, loading, by the cache manager, the read data from a cache; as well as In response to determining that a cache miss has occurred, the read data is read from a memory cell array of the nonvolatile memory device by the nonvolatile memory interface circuit.

17. A storage controller, the storage controller comprising: a host interface circuit configured to receive a read request from an external host device and transmit read data corresponding to the read request to the external host device; an address manager configured to receive a command identifier and a host address from the host interface circuit, store mapping information about the command identifier and the host address in a conversion table, and perform an address conversion operation to convert a destination address of the read data from a virtual address to the host address; as well as A DMA engine, namely a direct memory access engine, is configured to set the destination address of the read data to the virtual address based on the mode information received from the address manager, and transfer the read data to the virtual address.

18. The storage controller according to claim 17, wherein: The DMA engine is also configured to: transfer the read data to the virtual address when the mode information indicates a first mode, write the read data to a buffer memory when the mode information indicates a second mode, and transfer the read data to the virtual address and write the read data to the buffer memory when the mode information indicates a third mode.

19. The storage controller according to claim 18, in, The DMA engine is a first DMA engine, and The storage controller further includes a second DMA engine, wherein the second DMA engine is configured to read the read data stored in the buffer memory and transfer the read data to the host address.

20. The storage controller of claim 17, further comprising a cache manager configured to determine whether a cache hit has occurred, and in response to determining that the cache hit has occurred, load the read data from a cache, in, The cache includes latches of a non-volatile memory device and a memory of an error correction code engine.

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