High-speed serial computer expansion bus standard terminal equipment and clock distribution circuit thereof

Abstract

The invention discloses a high-speed serial computer expansion bus standard terminal device and a clock distribution circuit thereof, and belongs to the field of integrated circuit design. When a level switching circuit receives a dual-port enable signal sent by a host, a multi-channel clock selector can be controlled to work in a dual-port mode; therefore, two paths of reference clocks of the host are correspondingly led to the first physical medium sub-layer and the second physical medium sub-layer, and when a dual-port enable signal is not received, the multi-path clock selector can be controlled to work in a single-port mode, and the reference clocks provided by the host through the first output end can be correspondingly led to the first physical medium sub-layer and the second physical medium sub-layer. The two reference clocks are synchronously output through the two output ends of the multi-channel clock selector, so that the two reference clocks are kept synchronous, the cooperative work of the two physical medium sub-layers is not influenced, and the forwarding processing performed by the multi-channel clock selector does not influence the quality of the reference clocks; the host can accurately control the working mode of the PCIe terminal device through the dual-port enable signal.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and in particular to a high-speed serial computer expansion bus standard terminal device and a clock distribution circuit thereof. Background Art

[0002] The PCIe controller of a dual-port PCIe (Peripheral Component Interconnect express) device has two independent PAMs (Physical Medium Attachment), so that the dual port can work in dual-port mode and single-port mode. In dual-port mode, a single PAM can be regarded as an independent PCIe terminal device, which can independently receive PCIe signals provided by the host to work; in single-port mode, the host provides a reference clock to a PAM inside the PCIe controller, and the processing unit in the PCIe controller converts the reference clock and distributes it to another PAM inside the PCIe controller. However, the "conversion and distribution" of the reference clock by the processing unit will not only cause delays and affect the collaborative work of the two PAMs, but may also reduce the quality of the reference clock.

[0003] Therefore, how to provide a solution to the above technical problems is a problem that those skilled in the art need to solve at present. Summary of the invention

[0004] The purpose of the present invention is to provide a high-speed serial computer expansion bus standard terminal device and its clock distribution circuit. In the single-port mode of the PCIe terminal device, a multi-way clock selector can synchronously output the reference clock provided by the host through the first output terminal through the two output terminals of the multi-way clock selector, so that the two reference clocks remain synchronized, and will not affect the coordinated work of the two physical medium sublayers, and the forwarding processing performed by the multi-way clock selector will not affect the quality of the reference clock. In addition, the host can accurately control the working mode of the PCIe terminal device through a dual-port enable signal.

[0005] In order to solve the above technical problems, the present invention provides a clock distribution circuit, including a multi-channel clock selector and a level conversion circuit;

[0006] The first output end of the multi-way clock selector is connected to the clock input end of the first physical medium sublayer, the second output end of the multi-way clock selector is connected to the clock input end of the second physical medium sublayer, the first input end of the multi-way clock selector is connected to the first output end of the host, the second input end of the multi-way clock selector is connected to the second output end of the host, the control end of the multi-way clock selector is connected to the output end of the level conversion circuit, and the input end of the level conversion circuit is connected to the third output end of the host;

[0007] The first physical medium sublayer and the second physical medium sublayer belong to the same high-speed serial computer expansion bus standard controller, and the first output terminal and the second output terminal of the host are both used to output a reference clock;

[0008] A multi-way clock selector, for connecting its first input terminal to the first output terminal and its second input terminal to the second output terminal when receiving a first level, and for synchronously outputting a reference clock received by its first input terminal through the first output terminal and the second output terminal when receiving a second level;

[0009] The level conversion circuit is used for outputting a first level when receiving a dual-port enable signal, and outputting a second level when not receiving a dual-port enable signal.

[0010] On the other hand, the multi-channel clock selector and the level conversion circuit are both arranged on the mainboard of a high-speed serial computer expansion bus standard terminal device;

[0011] The clock distribution circuit also includes first to twelfth connection terminals and four electrical connection devices arranged on the mainboard of the high-speed serial computer expansion bus standard terminal device;

[0012] The first connection terminal is connected to the first output end of the host, the second connection terminal is connected to the fifth connection terminal, the third connection terminal is connected to the first input end of the multi-way clock selector, the fourth connection terminal is connected to the clock input end of the first physical medium sublayer, the sixth connection terminal is connected to the first output end of the multi-way clock selector, the seventh connection terminal is connected to the second output end of the host, the eighth connection terminal is connected to the eleventh connection terminal, the ninth connection terminal is connected to the second input end of the multi-way clock selector, the tenth connection terminal is connected to the clock input end of the second physical medium sublayer, and the twelfth connection terminal is connected to the second output end of the multi-way clock selector;

[0013] Any one of the first connection terminal, the fourth connection terminal, the seventh connection terminal and the tenth connection terminal is used to establish an electrical connection with an adjacent connection terminal through a corresponding one of the electrical connection components.

[0014] On the other hand, the electrical connection device includes a zero-ohm resistor or a jumper cap.

[0015] In another aspect, the level conversion circuit includes a processor;

[0016] The clock distribution circuit also includes a prompter;

[0017] The processor is used to output a first level when receiving a dual-port enable signal, and output a second level when not receiving the dual-port enable signal; and control the prompter to prompt whether the dual-port enable signal is currently received.

[0018] On the other hand, the clock distribution circuit further includes a first voltage monitoring module;

[0019] A first voltage monitoring module, used for detecting a first voltage value of a second input terminal of the multi-channel clock selector;

[0020] The processor is also used to, when no dual-port enable signal is received, determine whether a reference clock exists at the second input end of the multi-channel clock selector according to the first voltage value, and if so, control the prompter to prompt that the reference clock is wrong.

[0021] On the other hand, the clock distribution circuit further includes a second voltage monitoring module:

[0022] A second voltage monitoring module, used for detecting a second voltage value of a first input terminal of the multi-channel clock selector;

[0023] The processor is also used to, when receiving a dual-port enable signal, determine whether there is a reference clock at the second input end of the multi-way clock selector through the first voltage value, determine whether there is a reference clock at the first input end of the multi-way clock selector through the second voltage value, and when there is no reference clock at any input end of the multi-way clock selector, control the prompter to prompt a reference clock error.

[0024] On the other hand, the level conversion circuit includes a controllable switch, a power supply, a first resistor and a second resistor;

[0025] The control end of the controllable switch is connected to the third output end of the host, the second end of the controllable switch is grounded, the common end formed by the first end of the controllable switch, the first end of the first resistor and the first end of the second resistor serves as the output end of the level conversion circuit, the second end of the first resistor is connected to the power supply, and the second end of the second resistor is grounded;

[0026] The controllable switch is used to disconnect the first end and the second end of the controllable switch when the control end receives the dual-port enable signal, and connect the first end and the second end of the controllable switch otherwise.

[0027] On the other hand, the level conversion circuit further includes a filtering module;

[0028] The first end of the filter module is connected to a common end formed by the first end of the controllable switch, the first end of the first resistor and the first end of the second resistor, and the second end of the filter module is grounded;

[0029] The filtering module is used to filter the voltage between the first resistor and the second resistor.

[0030] On the other hand, the dual-port enable signal is at a low level;

[0031] The controllable switch includes an N-channel metal oxide semi-conductor field effect transistor.

[0032] In order to solve the above technical problems, the present invention also provides a high-speed serial computer expansion bus standard terminal device, comprising a circuit substrate and a dual-port high-speed serial computer expansion bus standard controller, and also comprising the clock distribution circuit as described above connected to the dual-port high-speed serial computer expansion bus standard controller;

[0033] Wherein, the dual-port high-speed serial computer expansion bus standard controller and the clock distribution circuit are arranged on the circuit substrate.

[0034] Beneficial effect: The present invention provides a clock distribution circuit. Considering that in single-port mode, the method of "leading a single reference clock to the same device and then synchronously outputting it through two ports" can output two synchronous reference clocks, the clock distribution circuit of the present application includes a multi-channel clock selector and a level conversion circuit. When the level conversion circuit receives the "dual-port enable signal sent by the host", the multi-channel clock selector can be controlled to work in the dual-port mode, so that the two reference clocks of the host are correspondingly led to the first physical medium sublayer and the second physical medium sublayer, and when the dual-port enable signal is not received, the multi-channel clock selector can be controlled to work in the single-port mode, and the reference clock provided by the host through the first output end can be synchronously output through the two output ends of the multi-channel clock selector, so that the two reference clocks remain synchronized, which will not affect the coordinated work of the two physical medium sublayers, and the forwarding processing performed by the multi-channel clock selector will not affect the quality of the reference clock. In addition, the host can accurately control the working mode of the PCIe terminal device through the dual-port enable signal.

[0035] The present invention also provides a high-speed serial computer expansion bus standard terminal device, which has the same beneficial effects as the above clock distribution circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the relevant technologies and the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0037] Figure 1 A schematic diagram of the structure of a clock distribution circuit provided by the present invention;

[0038] Figure 2 A schematic diagram of signal connection in a dual-port mode in the related art;

[0039] Figure 3 A schematic diagram of signal connection in a single-port mode in the related art;

[0040] Figure 4 A schematic diagram of the structure of another clock distribution circuit provided by the present invention;

[0041] Figure 5 A schematic diagram of the structure of a level conversion circuit provided by the present invention. DETAILED DESCRIPTION

[0042] The core of the present invention is to provide a high-speed serial computer expansion bus standard terminal device and its clock distribution circuit. In the single-port mode of the PCIe terminal device, the multi-way clock selector can synchronously output the reference clock provided by the host through the first output end through the two output ends of the multi-way clock selector, so that the two reference clocks remain synchronized, which will not affect the coordinated work of the two physical medium sublayers, and the forwarding processing performed by the multi-way clock selector will not affect the quality of the reference clock. In addition, the host can accurately control the working mode of the PCIe terminal device through the dual-port enable signal.

[0043] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0044] Please refer to Figure 1 , Figure 1 A schematic diagram of the structure of a clock distribution circuit provided by the present invention, the clock distribution circuit comprises a multi-channel clock selector 1 and a level conversion circuit 2;

[0045] The first output end of the multi-channel clock selector 1 is connected to the clock input end of the first physical medium sublayer, the second output end of the multi-channel clock selector 1 is connected to the clock input end of the second physical medium sublayer, the first input end of the multi-channel clock selector 1 is connected to the first output end of the host, the second input end of the multi-channel clock selector 1 is connected to the second output end of the host, the control end of the multi-channel clock selector 1 is connected to the output end of the level conversion circuit 2, and the input end of the level conversion circuit 2 is connected to the third output end of the host;

[0046] The first physical medium sublayer and the second physical medium sublayer belong to the same high-speed serial computer expansion bus standard controller, and the first output terminal and the second output terminal of the host are both used to output a reference clock;

[0047] A multi-channel clock selector 1, for connecting its first input terminal to the first output terminal and its second input terminal to the second output terminal when receiving a first level, and for synchronously outputting a reference clock received by its first input terminal through the first output terminal and the second output terminal when receiving a second level;

[0048] The level conversion circuit 2 is used to output a first level when receiving a dual-port enable signal, and output a second level when not receiving a dual-port enable signal.

[0049] To better illustrate the embodiments of the present invention, please refer to Figure 2 and Figure 3 , Figure 2 It is a schematic diagram of signal connection in dual-port mode in the related art. Figure 3 is a schematic diagram of signal connection in a single-port mode in the related art. Figure 2 In the embodiment, the two PAMs work independently of each other, the reference clock of the first host is provided to the clock input terminal of the first PAM, the first host and the first PAM transmit signals through the first channel and the second channel, the reference clock of the second host is provided to the clock input terminal of the second PAM, the second host and the second PAM transmit signals through the third channel and the fourth channel, Figure 3 In the example, the two PAMs work as a whole. At this time, the first host provides a reference clock to the clock input of the first PAM, and the processing unit in the PCIe controller converts the reference clock and distributes it to the second PAM. The first host and the "first PAM and the second PAM as a whole" transmit signals through the first to fourth channels.

[0050] Specifically, taking into account the technical problems in the above background technology, and considering that in single-port mode, the method of "leading a single reference clock to the same device and then outputting it synchronously through two ports" can output two synchronous reference clocks, therefore, in an embodiment of the present invention, the two output ends of the host are intended to be connected to the two input ends of the multi-channel clock selector 1, and the two output ends of the multi-channel clock selector 1 are connected to the clock input ends of the two physical medium sublayers (that is, the PCIe module) in the PCIe controller, so as to realize the forwarding of the two reference clocks by the multi-channel clock selector 1.

[0051] Specifically, based on the above structure, the dual-port enable signal sent by the host can be processed by the level conversion circuit 2 to control the multi-way clock selector 1 to cooperate with the "PCIe controller of the PCIe terminal device" to work in the dual-port mode. When the host does not send a dual-port enable signal, the level conversion circuit 2 can control the multi-way clock selector 1 to cooperate with the "PCIe controller of the PCIe terminal device" to work in the single-port mode through the output second level.

[0052] Among them, in the dual-port mode, the multi-channel clock selector 1 can send the two received reference clocks to the clock input end of the physical medium sublayer one by one. In the single-port mode, the multi-channel clock selector 1 can receive the reference clock provided by the host through the first output end through the first input end, and synchronize the output of the reference clock through its own two output ends, so that the two physical medium sublayers can receive the reference clock synchronously, that is, in the single-port mode, the two PAMs of the PCIe controller can synchronously receive one reference clock, and there is no delay in the reference clocks received by the two PAMs, thereby improving the working reliability of the single-port mode. Moreover, the "copying and synchronous output" action of the multi-channel selector for the single reference clock in the single-port mode will not affect the signal quality of the reference clock, and also ensure the quality of the reference clock.

[0053] In addition, it is worth mentioning that the PCIe standard stipulates that in single-port mode, the PCIe host provides a single reference clock through the output end with the smallest sequence number. Therefore, in an embodiment of the present invention, the PCIe host can output the reference clock through the first output end in single-port mode.

[0054] The first level and the second level may be two levels with opposite high and low states, which is not limited in the embodiment of the present invention.

[0055] Specifically, the multi-channel clock selector 1 may be of various types, for example, it may be a MUX (multiplexer), and specifically, a MUX of model RC19202AGNT may be selected, and the embodiment of the present invention is not limited here.

[0056] The clock distribution circuit of the present application includes a multi-channel clock selector and a level conversion circuit. When the level conversion circuit receives a "dual-port enable signal sent by the host", the multi-channel clock selector can be controlled to operate in a dual-port mode, thereby correspondingly leading the two reference clocks of the host to the first physical medium sublayer and the second physical medium sublayer. When the dual-port enable signal is not received, the multi-channel clock selector can be controlled to operate in a single-port mode. The reference clock provided by the host through the first output end can be synchronously output through the two output ends of the multi-channel clock selector, thereby keeping the two reference clocks synchronized, without affecting the coordinated work of the two physical medium sublayers, and the forwarding processing performed by the multi-channel clock selector will not affect the quality of the reference clock. In addition, the host can accurately control the working mode of the PCIe terminal device through the dual-port enable signal.

[0057] Based on the above embodiments:

[0058] As an optional embodiment, the multi-channel clock selector 1 and the level conversion circuit 2 are both arranged on the mainboard of a high-speed serial computer expansion bus standard terminal device;

[0059] The clock distribution circuit also includes first to twelfth connection terminals and four electrical connection devices arranged on a mainboard of a high-speed serial computer expansion bus standard terminal device;

[0060] The first connection terminal is used to connect to the first output end of the host, the second connection terminal is connected to the fifth connection terminal, the third connection terminal is connected to the first input end of the multi-way clock selector 1, the fourth connection terminal is connected to the clock input end of the first physical medium sublayer, the sixth connection terminal is connected to the first output end of the multi-way clock selector 1, the seventh connection terminal is used to connect to the second output end of the host, the eighth connection terminal is connected to the eleventh connection terminal, the ninth connection terminal is connected to the second input end of the multi-way clock selector 1, the tenth connection terminal is connected to the clock input end of the second physical medium sublayer, and the twelfth connection terminal is connected to the second output end of the multi-way clock selector 1;

[0061] Any one of the first connection terminal, the fourth connection terminal, the seventh connection terminal and the tenth connection terminal is used to establish an electrical connection with an adjacent connection terminal through a corresponding electrical connection device.

[0062] Specifically, to better illustrate the embodiments of the present invention, please refer to Figure 4 , Figure 4 A schematic diagram of the structure of another clock distribution circuit provided by the present invention, Figure 4The 12 circular symbols containing 1 to 12 around the multi-way clock selector 1 in the figure represent the first to twelfth connection terminals respectively. The serial numbers of the connection terminals (first to twelfth) are consistent with the numbers in the circular symbols. The signal transmission scheme can be selected through the twelve connection terminals.

[0063] Specifically, in order to improve the simplicity of connection between the PCIe terminal device and the PCIe host, the multi-channel clock selector 1 and the level conversion circuit 2 in the embodiment of the present invention are both arranged on the mainboard of the PCIe terminal device.

[0064] Specifically, considering that for some PCIe controllers, the design quality of the conversion and distribution of the reference clock inside is good, and thus the signal delay will not be increased or the signal quality will not be reduced, that is, for such PCIe controllers, in theory, the reference clock can be forwarded without going through the multi-way clock selector 1. Therefore, in order to meet this demand, the first to twelfth connection terminals are also designed on the motherboard of the PCIe device in the embodiment of the present invention. Through the connection of the connection terminals, two signal processing schemes can be selected. The first is the aforementioned scheme of processing through the multi-way clock selector 1, and the second is the traditional scheme of "directly connecting the first output end of the PCIe host to the clock input end of the first PAM, and directly connecting the second output end of the PCIe host to the clock input end of the second PAM, and the internal processing unit of the PCIe control performs the conversion and distribution of the reference clock in the single-port mode".

[0065] Among them, if you want to select the solution of "including multi-way clock selector 1", you can connect the first connection terminal to the third connection terminal, the fourth connection terminal to the sixth connection terminal, the seventh connection terminal to the ninth connection terminal, and the tenth connection terminal to the twelfth connection terminal; if you want to select the solution of "not including multi-way clock selector 1", you can connect the first connection terminal to the second connection terminal, the fourth connection terminal to the fifth connection terminal, the seventh connection terminal to the eighth connection terminal, and the tenth connection terminal to the eleventh connection terminal.

[0066] As an optional embodiment, the electrical connection device includes a zero-ohm resistor or a jumper cap.

[0067] Specifically, the electrical connection of the connection terminals can be performed through a zero-ohm resistor or a jumper cap without affecting the transmission of the reference clock, and both have the advantages of small size and low cost.

[0068] Of course, in addition to the zero-ohm resistor and the jumper cap, the electrical connection device may also be of other types, which is not limited in the embodiment of the present invention.

[0069] As an optional embodiment, the level conversion circuit 2 includes a processor;

[0070] The clock distribution circuit also includes a prompter;

[0071] The processor is used to output a first level when receiving a dual-port enable signal, and output a second level when not receiving the dual-port enable signal; and control the prompter to prompt whether the dual-port enable signal is currently received.

[0072] Specifically, considering that the processor has level processing capabilities and is small and simple, the level conversion circuit 2 in the embodiment of the present invention includes a processor; and considering that in some cases the staff needs to know in real time whether the level conversion circuit 2 can normally receive the dual-port enable signal, the processor in the embodiment of the present invention can also control the prompter to prompt whether the dual-port enable signal is currently received, so that the staff can judge "whether the processor can normally receive the dual-port enable signal and analyze the signal transmission path or whether the processor has a fault" through the information prompted by the prompter.

[0073] The prompter may be of various types, such as a display or a voice announcer, or the PCIe host may be used directly as the prompter, which is not limited in the embodiment of the present invention.

[0074] As an optional embodiment, the clock distribution circuit further includes a first voltage monitoring module;

[0075] A first voltage monitoring module, used for detecting a first voltage value of a second input terminal of the multi-channel clock selector 1;

[0076] The processor is also used to, when not receiving the dual-port enable signal, determine whether there is a reference clock at the second input end of the multi-channel clock selector 1 through the first voltage value, and if so, control the prompter to prompt a reference clock error.

[0077] Specifically, considering that the PCIe host may mistakenly send a reference clock to the second input terminal of the clock selector in single-port mode, in order to promptly discover this situation, in the embodiment of the present invention, in single-port mode (that is, the processor has not received the dual-port enable signal), the first voltage value of the second input terminal of the multi-way clock selector 1 is used to determine whether there is a reference clock at the second input terminal of the multi-way clock selector 1. Under normal circumstances, it should not exist. If it exists, it means that the PCIe host erroneously outputs the reference clock, so the indicator can be controlled to prompt the reference clock error.

[0078] The first voltage monitoring module may be of various types, for example, a voltage divider circuit, etc., which is not limited in the embodiment of the present invention.

[0079] As an optional embodiment, the clock distribution circuit further includes a second voltage monitoring module:

[0080] A second voltage monitoring module, used for detecting a second voltage value of a first input terminal of the multi-channel clock selector 1;

[0081] The processor is also used to, when receiving a dual-port enable signal, determine whether there is a reference clock at the second input end of the multi-way clock selector 1 through a first voltage value, determine whether there is a reference clock at the first input end of the multi-way clock selector 1 through a second voltage value, and when there is no reference clock at any input end of the multi-way clock selector 1, control the prompter to prompt a reference clock error.

[0082] Specifically, considering that if an abnormality occurs in the PCIe host in the dual-port mode, it may not be able to output the reference clock through any of its own output ends, in order to promptly detect the abnormality, the processor in the embodiment of the present invention can, when receiving the dual-port enable signal, determine whether there is a reference clock at the second input end of the multi-way clock selector 1 by the first voltage value of the second input end of the multi-way clock selector 1, determine whether there is a reference clock at the first input end of the multi-way clock selector 1 by the second voltage value of the first input end of the multi-way clock selector 1, and when there is no reference clock at any input end of the multi-way clock selector 1, control the prompter to prompt a reference clock error, so that the staff can promptly detect the reference clock output error of the PCIe host.

[0083] Among them, there can be many specific ways to determine whether there is a reference clock at the second input end of the multi-way clock selector 1 by the first voltage value, and to determine whether there is a reference clock at the first input end of the multi-way clock selector 1 by the second voltage value. For example, they can all be "when the voltage value has periodic fluctuations, it can be determined that there is a reference clock, otherwise it can be determined that there is no reference clock", etc. The embodiments of the present invention are not limited here.

[0084] In addition, considering that the transmission of the reference clock may be abnormal and the multi-way clock selector 1 may also fail, the embodiment of the present invention may also include a third voltage monitoring module and a fourth voltage monitoring module to analyze the failure of the multi-way clock selector 1. The third voltage monitoring module can detect the third voltage value of the first output end of the multi-way clock selector 1, and the fourth voltage monitoring module can detect the fourth voltage value of the second output end of the multi-way clock selector 1. In this case, the processor can control the prompter to prompt in real time "the signal waveform from the first voltage value to the fourth voltage value" and "whether the dual-port enable signal is currently received". Based on the prompt information, the staff can analyze whether the two inputs and two outputs of the reference clock of the multi-way clock selector 1 match the signal received by the control end of the multi-way clock selector 1. If they match, it means "there is no problem with the multi-way clock selector 1", thereby efficiently realizing the fault analysis of the multi-way clock selector 1.

[0085] As an optional embodiment, the level conversion circuit 2 includes a controllable switch, a power supply, a first resistor and a second resistor;

[0086] The control end of the controllable switch is connected to the third output end of the host, the second end of the controllable switch is grounded, the common end formed by the first end of the controllable switch, the first end of the first resistor and the first end of the second resistor serves as the output end of the level conversion circuit 2, the second end of the first resistor is connected to the power supply, and the second end of the second resistor is grounded;

[0087] The controllable switch is used to disconnect the first end and the second end of the switch when the control end receives a dual-port enable signal, and connect the first end and the second end of the switch otherwise.

[0088] Specifically, in order to better illustrate the embodiments of the present invention, please refer to Figure 5 , Figure 5 A schematic diagram of the structure of a level conversion circuit 2 provided by the present invention, Figure 5 Q1 in the figure represents a controllable switch (which can be NMOS), and the control end of the controllable switch can also be connected to a current limiting resistor R3, R1 is also a first resistor, R2 is a second resistor, and the filtering circuit is implemented by a capacitor C1. When the PCIe host outputs a low level (that is, a dual-port enable signal) through the third output end, Q1 is not turned on, and the voltage signal between R1 and R2 (for example, 1.65V) is used as the output of the level conversion circuit 2, and when the PCIe host outputs a high level through the third output end, Q1 is turned on, and the level conversion circuit 2 outputs a low level.

[0089] Wherein, please refer to the following Table 1, which is a comparison relationship table between the output of the level conversion circuit 2 and the output of the multi-channel clock selector 1. It can be seen from the table that when the output signal CLKSEL_MUX of the level conversion circuit 2 is 0 (low level), corresponding to the single-port mode of the PCIe terminal device, the first output end of MUX and the second output end of MUX both output the reference clock received by the first input end of MUX, and when the output signal CLKSEL_MUX of the level conversion circuit 2 is 1 (high level), corresponding to the dual-port mode of the PCIe terminal device, the first output end of MUX outputs the reference clock received by the first input end of MUX, and the second output end of MUX outputs the reference clock received by the second input end of MUX.

[0090] Table 1

[0091]

[0092] Specifically, considering that the level conversion circuit 2 can also be constructed by circuit elements and has the advantages of small size and low cost, the level conversion circuit 2 can be constructed by a controllable switch, a power supply, a first resistor and a second resistor in the embodiment of the present invention. The controllable switch can turn off its first end and the second end when the control end receives a dual-port enable signal, otherwise connect its first end and the second end. After turning off its first end and the second end, the level output by the level conversion circuit 2 is the voltage between the first resistor and the second resistor (the first level), and when connecting its first end and the second end, since the output end is grounded, the level output by the level conversion circuit 2 is a low level (the second level).

[0093] Of course, in addition to this specific structure, the level conversion circuit 2 constructed by circuit elements can also be in many other forms, which is not limited in the embodiment of the present invention.

[0094] As an optional embodiment, the level conversion circuit 2 further includes a filtering module;

[0095] The first end of the filter module is connected to a common end formed by the first end of the controllable switch, the first end of the first resistor and the first end of the second resistor, and the second end of the filter module is grounded;

[0096] The filtering module is used to filter the voltage between the first resistor and the second resistor.

[0097] Specifically, considering that the output signal of the level conversion circuit 2 may be mixed with noise, and the stability of the output signal of the level conversion circuit 2 is related to the stability of the multi-channel clock selector 1, the level conversion circuit 2 in the embodiment of the present invention also includes a filtering module, which can filter the voltage between the first resistor and the second resistor, thereby improving the stability of the output signal of the level conversion circuit 2.

[0098] The filter module may be of various types, such as a capacitor, etc., which is not limited in the embodiment of the present invention.

[0099] As an optional embodiment, the dual-port enable signal is at a low level;

[0100] The controllable switch includes an N-channel metal oxide semi-conductor field effect transistor.

[0101] Specifically, the dual-port enable signal may be a low level, and when the dual-port enable signal is not sent, the PCIe host may output a high level through the third output terminal, thereby causing the level conversion circuit 2 to output the second level.

[0102] Among them, NMOS (N-Metal-Oxide-Semiconductor Field Effect Transistor) has the advantages of small size, fast response and low cost.

[0103] Of course, in addition to NMOS, the controllable switch may also be of other types, which is not limited in the embodiment of the present invention.

[0104] The present invention also provides a high-speed serial computer expansion bus standard terminal device, comprising a circuit substrate and a dual-port high-speed serial computer expansion bus standard controller, and also comprising the above clock distribution circuit connected to the dual-port high-speed serial computer expansion bus standard controller;

[0105] Among them, a dual-port high-speed serial computer expansion bus standard controller and a clock distribution circuit are set up with a circuit substrate.

[0106] For an introduction to the embodiment of the present invention, please refer to the aforementioned embodiment of the clock distribution circuit, and the embodiment of the present invention will not be described in detail here.

[0107] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same and similar parts between the embodiments can be referred to each other. It should also be noted that in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also other elements that are not explicitly listed, or also include elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the element.

[0108] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A clock distribution circuit, characterized in that: Including a multi-channel clock selector and a level conversion circuit; The first output end of the multi-way clock selector is connected to the clock input end of the first physical medium sublayer, the second output end of the multi-way clock selector is connected to the clock input end of the second physical medium sublayer, the first input end of the multi-way clock selector is connected to the first output end of the host, the second input end of the multi-way clock selector is connected to the second output end of the host, the control end of the multi-way clock selector is connected to the output end of the level conversion circuit, and the input end of the level conversion circuit is connected to the third output end of the host; The first physical medium sublayer and the second physical medium sublayer belong to the same high-speed serial computer expansion bus standard controller, and the first output terminal and the second output terminal of the host are both used to output a reference clock; A multi-way clock selector, for connecting its first input terminal to the first output terminal and its second input terminal to the second output terminal when receiving a first level, and for synchronously outputting a reference clock received by its first input terminal through the first output terminal and the second output terminal when receiving a second level; The level conversion circuit is used for outputting a first level when receiving a dual-port enable signal, and outputting a second level when not receiving a dual-port enable signal.

2. The clock distribution circuit according to claim 1, characterized in that: The multi-channel clock selector and the level conversion circuit are both arranged on the mainboard of a high-speed serial computer expansion bus standard terminal device; The clock distribution circuit also includes first to twelfth connection terminals and four electrical connection devices arranged on the mainboard of the high-speed serial computer expansion bus standard terminal device; The first connection terminal is connected to the first output end of the host, the second connection terminal is connected to the fifth connection terminal, the third connection terminal is connected to the first input end of the multi-way clock selector, the fourth connection terminal is connected to the clock input end of the first physical medium sublayer, the sixth connection terminal is connected to the first output end of the multi-way clock selector, the seventh connection terminal is connected to the second output end of the host, the eighth connection terminal is connected to the eleventh connection terminal, the ninth connection terminal is connected to the second input end of the multi-way clock selector, the tenth connection terminal is connected to the clock input end of the second physical medium sublayer, and the twelfth connection terminal is connected to the second output end of the multi-way clock selector; Any one of the first connection terminal, the fourth connection terminal, the seventh connection terminal and the tenth connection terminal is used to establish an electrical connection with an adjacent connection terminal through a corresponding one of the electrical connection components.

3. The clock distribution circuit according to claim 2, characterized in that: The electrical connection device includes a zero-ohm resistor or a jumper cap.

4. The clock distribution circuit according to claim 1, characterized in that: The level conversion circuit includes a processor; The clock distribution circuit also includes a prompter; The processor is used to output a first level when receiving a dual-port enable signal, and output a second level when not receiving the dual-port enable signal; and control the prompter to prompt whether the dual-port enable signal is currently received.

5. The clock distribution circuit according to claim 4, characterized in that: The clock distribution circuit also includes a first voltage monitoring module; A first voltage monitoring module, used for detecting a first voltage value of a second input terminal of the multi-channel clock selector; The processor is also used to, when no dual-port enable signal is received, determine whether a reference clock exists at the second input end of the multi-channel clock selector according to the first voltage value, and if so, control the prompter to prompt that the reference clock is wrong.

6. The clock distribution circuit according to claim 5, characterized in that: The clock distribution circuit also includes a second voltage monitoring module: A second voltage monitoring module, used for detecting a second voltage value of a first input terminal of the multi-channel clock selector; The processor is also used to, when receiving a dual-port enable signal, determine whether there is a reference clock at the second input end of the multi-way clock selector through the first voltage value, determine whether there is a reference clock at the first input end of the multi-way clock selector through the second voltage value, and when there is no reference clock at any input end of the multi-way clock selector, control the prompter to prompt a reference clock error.

7. The clock distribution circuit according to any one of claims 1 to 6, characterized in that: The level conversion circuit includes a controllable switch, a power supply, a first resistor and a second resistor; The control end of the controllable switch is connected to the third output end of the host, the second end of the controllable switch is grounded, the common end formed by the first end of the controllable switch, the first end of the first resistor and the first end of the second resistor serves as the output end of the level conversion circuit, the second end of the first resistor is connected to the power supply, and the second end of the second resistor is grounded; The controllable switch is used to disconnect the first end and the second end of the controllable switch when the control end receives the dual-port enable signal, and connect the first end and the second end of the controllable switch otherwise.

8. The clock distribution circuit according to claim 7, characterized in that: The level conversion circuit also includes a filtering module; The first end of the filter module is connected to a common end formed by the first end of the controllable switch, the first end of the first resistor and the first end of the second resistor, and the second end of the filter module is grounded; The filtering module is used to filter the voltage between the first resistor and the second resistor.

9. The clock distribution circuit according to claim 7, characterized in that: The dual-port enable signal is at a low level; The controllable switch includes an N-channel metal oxide semi-conductor field effect transistor.

10. A high-speed serial computer expansion bus standard terminal device, characterized in that: It comprises a circuit substrate and a dual-port high-speed serial computer expansion bus standard controller, and also comprises a clock distribution circuit as claimed in any one of claims 1 to 9 connected to the dual-port high-speed serial computer expansion bus standard controller; Wherein, the dual-port high-speed serial computer expansion bus standard controller and the clock distribution circuit are arranged on the circuit substrate.

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