Clock tree comprehensive optimization method and system based on layered region division and buffer insertion

Abstract

The invention discloses a clock tree comprehensive optimization method and system based on layered region division and buffer insertion, and the method carries out the clock tree comprehensive optimization through a layered buffer insertion mode, and comprises the steps: firstly, taking all registers as basic units, carrying out the rectangular region cutting of a circuit, and inserting a bottom buffer at a geometric center point; then taking the upper layer buffer as a basic unit, dividing a circuit area by using a rhombus grid division method, inserting a middle layer buffer at a geometric center point, and finally inserting a top layer buffer according to an H-tree structure; after the buffers are inserted, the positions of the buffers are dynamically adjusted, so that delay minimization and deflection control of the global clock tree are achieved, meanwhile, the number of the buffers is effectively reduced, power consumption is reduced, and design efficiency is improved.

Description

Technical Field

[0001] The invention relates to digital circuit simulation and optimization technology, in particular to a clock tree comprehensive optimization method and system based on hierarchical region division and buffer insertion. Background Art

[0002] In digital integrated circuit design, the clock signal is the benchmark for data transmission, and its stability and reliability are crucial to the function and performance of the entire system. The clock signal is usually the signal with the largest fan-out, the longest transmission distance, and the fastest running speed in the entire chip. Therefore, the generation and distribution process of the clock signal has a decisive influence on the design quality of the chip. If the clock signal cannot meet the critical timing requirements under the worst conditions, data errors may be incorrectly latched into the register, resulting in failure and instability of system functions.

[0003] In modern chip design, Clock Tree Synthesis (CTS) is a key step in the physical design phase, especially in the ASIC (Application Specific Integrated Circuit) process based on standard cell libraries. The design goal of the clock tree is to ensure that the clock signal meets the timing constraints when it reaches all clock receiving ends (such as registers, memories, etc.) from the clock source, and avoid problems such as clock offset and delay. The design process of the clock tree usually includes the selection of the root node, the distribution of the clock signal, and the insertion of the clock driver.

[0004] The clock signal starts from the source point (root node), passes through multiple distribution nodes and finally reaches the register or other clock terminal to form a complete clock tree. The root node of the clock tree is usually located at the clock source of the chip, and the distribution nodes and leaf nodes are respectively associated with the transmission process of the clock signal. In order to ensure that the clock signal can be transmitted effectively, it is often necessary to insert a buffer between the distribution node and the leaf node in the design to reduce the attenuation and delay of the clock signal during transmission.

[0005] Existing clock tree synthesis optimization technologies include hierarchical clock tree synthesis methods, which divide the clock tree design into multiple levels and distribute clock signals in a hierarchical manner. Although it can effectively reduce the computational complexity, the hierarchical method may lead to poor global clock synchronization and large local clock skew when optimizing clock skew and clock delay. Especially when the chip design complexity is high, insufficient optimization at the low level may cause uneven distribution of clock signals, resulting in large clock skew. In addition, the traditional buffer insertion method is based on local optimal strategies, such as greedy algorithms. Under certain conditions, it may insert too many buffers to optimize clock skew or delay, but fails to consider the needs of global optimization, resulting in unnecessary buffer insertion. The insertion of too many buffers not only increases the power consumption of the chip, but also occupies more layout space, which may lead to area waste. Especially in resource-limited designs, excessive insertion of buffers will reduce design efficiency. Summary of the invention

[0006] Purpose of the invention: The purpose of the present invention is to provide a clock tree synthesis optimization method and system based on hierarchical region division and buffer insertion, to identify and optimize the timing problems and failure and instability of system functions that may be caused by clock signal distribution in the circuit, thereby achieving stable design of the circuit and solving the technical problems that traditional clock tree synthesis methods cannot efficiently handle clock skew, clock delay, buffer insertion redundancy and low optimization efficiency in complex circuits.

[0007] Technical solution: The clock tree comprehensive optimization method based on hierarchical region division and buffer insertion of the present invention comprises the following steps: Step 1, extracting circuit information, including register connection information and signal topology; Step 2, taking all registers as basic units, dividing the circuit area by using a rectangular cutting method, and inserting a bottom buffer at the geometric center point of each first area obtained after the division; Step 3, using the upper layer buffer as the basic unit, dividing the circuit area using the diamond grid division method, inserting the middle layer buffer at the geometric center point of each second area obtained after the division; repeating step 3 until n layers of middle layer buffers are inserted; n is the number of layers of the middle layer buffer; The upper buffer of the nth layer middle buffer is the n-1th layer middle buffer, and the upper buffer of the 1st layer middle buffer is the bottom buffer; Step 4, insert m layers of top buffers according to the H-tree structure; m is the number of layers of the top buffers; Step 5, output the circuit information after the buffer is inserted, including the location information of the bottom buffer, the middle buffer and the top buffer, the signal topology after the buffer is inserted, and the connection relationship between the register and the buffer.

[0008] Furthermore, in step 2, a hierarchical clustering algorithm is used to divide each first region into a plurality of point sets according to the maximum fan-out number limit, wherein the points in the point set are registers; and the geometric center of each point set is calculated and inserted into the bottom buffer.

[0009] Furthermore, in step 2 and step 3, overlap detection is performed on each bottom layer buffer and middle layer buffer, and if there is overlap, the positions of the geometric centers are adjusted and then the bottom layer buffer and the middle layer buffer are inserted, including the following steps: Check whether the edges of the bottom buffer and the middle buffer intersect with other buffers and / or registers. If so, move the position of the geometric center in the opposite direction of the intersecting edges, and then re-perform overlap detection until any edge of the bottom buffer and the middle buffer does not intersect with other buffers and / or registers.

[0010] Furthermore, in step 3, the upper layer buffer is used as a basic unit, the circuit area is divided by a diamond grid division method, and the middle layer buffer is inserted at the geometric center point of each second area obtained after the division, including: Calculate the ratio of the number of buffers in the previous layer to the maximum fan-out number, round up the ratio to get the middle-layer division number, perform diamond division according to the middle-layer division number to get several second areas, calculate whether the number of basic units in each second area meets the maximum fan-out number limit, if not, re-divide the basic unit farthest from the geometric center of the second area until each second area meets the maximum fan-out number limit; calculate the sum of the net_rc values ​​between the basic unit and the geometric center in each second area ,like If the maximum net_rc value limit in the second region is exceeded, the basic unit farthest from the geometric center of the second region is re-divided until each second region meets the maximum net_rc value limit; a middle buffer is inserted at the geometric center point of each second region; The net_rc value is , where D is the Manhattan distance between the basic unit and the geometric center, r and c are the resistance and capacitance values ​​of the line between the basic unit and the geometric center, respectively.

[0011] Furthermore, in step 3, the number of layer buffers in the nth layer ranges from [30, 40].

[0012] Further, in step 4, for any two k-1th layer top buffers q1 and q2 connected to any k-th layer top buffer p, the net_rc values ​​from p to q1 and q2 are calculated respectively, denoted as net_rc1 and net_rc2, and the maximum net_rc values ​​from q1 and q2 to the k-2th layer top buffer connected thereto are calculated, denoted as c1 and c2; where k=3,4,5,…,m; If net_rc1+c1>net_rc2+c2, adjust the position of p toward q1; if net_rc1+c1<net_rc2+c2, adjust the position of p toward q2; if net_rc1+c1=net_rc2+c2, do not adjust the position of p; The net_rc value is , where D is the Manhattan distance between buffers, r and c are the resistance and capacitance of the wires between buffers, respectively.

[0013] Furthermore, in step 4, for any k-th layer top buffer p, any k-1-th layer top buffer q1 connected to p, and any k-2-th layer top buffer q3 connected to q1, where k=3, 4, 5,…, m; if the horizontal coordinate of q3 is between the horizontal coordinates of p and q1, the position of q1 is adjusted along the horizontal coordinate in the direction of p; if the vertical coordinate of q3 is between the vertical coordinates of p and q1, the position of q1 is adjusted along the vertical coordinate in the direction of p.

[0014] The clock tree comprehensive optimization system based on hierarchical region division and buffer insertion of the present invention comprises: A circuit information extraction unit, used to extract circuit information, including register connection information and signal topology structure; A bottom buffer insertion unit is used to divide the circuit area by using a rectangular cutting method using all registers as basic units, and insert a bottom buffer at the geometric center point of each first area obtained after the division; The middle-layer buffer insertion unit is used to divide the circuit area by using the upper-layer buffer as the basic unit using the diamond grid division method, and insert the middle-layer buffer at the geometric center point of each second area obtained after the division; repeat step 3 until n layers of middle-layer buffers are inserted; n is the number of layers of the middle-layer buffers; The upper buffer of the nth layer middle buffer is the n-1th layer middle buffer, and the upper buffer of the 1st layer middle buffer is the bottom buffer; A top buffer insertion unit, used for inserting m layers of top buffers according to an H-tree structure; m is the number of layers of the top buffers; The clock tree synthesis optimization result output unit is used to output the circuit information after the buffer is inserted, including the location information of the bottom buffer, the middle buffer and the top buffer, the signal topology structure after the buffer is inserted, and the connection relationship between the register and the buffer.

[0015] The electronic device described in the present invention includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the computer program is loaded into the processor, the clock tree synthesis optimization method based on hierarchical region division and buffer insertion is implemented.

[0016] The computer-readable storage medium of the present invention stores a computer program, and when the computer program is executed by a processor, the clock tree synthesis optimization method based on hierarchical region division and buffer insertion is implemented.

[0017] Beneficial effects: Compared with the prior art, the advantages of the present invention are: (1) The present invention can quickly identify and eliminate clock delays and clock offsets, especially in complex circuits to ensure the stability of clock signals and meet strict timing requirements. When inserting at the bottom and middle layers, clustering algorithms and rectangular cutting and diamond grid division strategies are used to accurately adjust the structure of each layer of the clock tree, effectively reduce the number of buffers, optimize the allocation of clock signals, ensure that the design power consumption is reduced and the quality of the clock signal is improved; when inserting at the top layer, a dynamic clock optimization strategy is used in combination with the improved H-tree structure, so that the present invention can adapt to design requirements of different scales, flexibly adjust the buffer position, optimize the clock tree at each level, and improve the flexibility and versatility of the design. (2) The optimization results provided by the present invention, including relevant parameters such as buffer insertion position, connection relationship, and clock tree allocation structure, can provide an accurate basis for subsequent design verification and simulation, significantly improve the efficiency of circuit simulation and verification, and ensure design stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a flow chart of the clock tree synthesis optimization method of the present invention.

[0019] Figure 2 Schematic diagram of a rectangular cutting algorithm in an embodiment of the present invention.

[0020] Figure 3 It is a schematic diagram of the insertion result of the bottom layer buffer according to an embodiment of the present invention.

[0021] Figure 4 Schematic diagram of the position adjustment function principle in an embodiment of the present invention.

[0022] Figure 5 Schematic diagram of the diamond grid division structure in an embodiment of the present invention.

[0023] Figure 6Schematic diagram of structural analysis of the superiority of diamond mesh division in an embodiment of the present invention.

[0024] Figure 7 Schematic diagram of clock skew optimization principle analysis in an embodiment of the present invention.

[0025] Figure 8 Schematic diagram of clock delay optimization principle analysis in an embodiment of the present invention. DETAILED DESCRIPTION

[0026] The technical solution of the present invention is further described below in conjunction with the accompanying drawings.

[0027] like Figure 1 As shown, the clock tree synthesis optimization method based on hierarchical area division and buffer insertion includes the following steps.

[0028] S1: Read circuit information through C++ language program.

[0029] The input file is read through a C++ language program to extract the register connection information and signal topology of the circuit. The information read from the input file includes the unit length unit, the circuit area size range floorplan, the clock source coordinate clock root, the size of the register FF and buffer buffer, and the coordinates of all register instances FF instance. In addition to the circuit information, the information read also includes the resistance value r and capacitance value c of the unit length chip internal connection net, the maximum net_rc value limit, the maximum fan-out number limit Max_fanout, and the delay data of a single buffer. The net_rc value is: , in this formula Refers to the net_rc value between unit 1 and unit 2. A unit can be a buffer or a register. Here, units 1 and 2 are just examples. It refers to the Manhattan distance between two units, and the unit of resistance value r is Ω / um, and the unit of capacitance value c is pF / um. After reading the input information, the extracted information is visualized to verify whether the circuit information is accurately extracted.

[0030] S2: Divide the circuit area into rectangles and insert them into the bottom buffer.

[0031] According to the circuit information extracted in step S1, all registers are taken as basic units, and the entire circuit area is divided using a rectangular cutting algorithm, such as Figure 2As shown in the figure, the division will terminate when the set index is reached. The index can be adjusted according to the size of the circuit, such as six equal divisions or eight equal divisions. After the division is completed, a preliminary model of the circuit is formed. The improved hierarchical clustering algorithm is used to group the points in each region according to the maximum fan-out limit to form several point sets. Each point set is traversed, and the sum of the x-coordinate and y-coordinate of each point in the point set is calculated. Then, the geometric center point is obtained by dividing by the size of the point set, and the point in the point set is the basic unit. The generated geometric center point may overlap with other points or exceed the boundary of the region. Therefore, after the geometric center is inserted into the underlying buffer, the overlap rate detection is performed. If the overlap rate is 0, the underlying buffer is inserted. Otherwise, the position is adjusted by the position adjustment function to ensure that the final generated point is valid. Finally, the buffer is inserted into each corrected geometric center point. These operations provide strong support for minimizing the number of inserted buffers and optimizing clock offsets.

[0032] like Figure 3 As shown in the figure, this circuit structure diagram shows the layout of the entire circuit area after the bottom buffer is inserted. The red dots in the figure represent registers (FF), the blue dots represent inserted buffers (BUF), and the green five-pointed star represents the clock source (CLK). This step does not connect the clock source, but only shows the location information of the clock source. The entire area is continuously divided using the rectangular area cutting algorithm, and then grouped using the hierarchical clustering algorithm. Finally, the buffer is inserted at the geometric center and the overlap rate is detected, as shown in Figure 4 For example, the green rectangle represents the buffer and the blue rectangle represents the register. When detecting the overlap rate, the four upper, lower, left and right sides of the size rectangle of the buffer and the register are intersected to detect whether all the registers and buffers in each point set overlap in area. If an intersection is found on the upper side of the buffer, it will be adjusted downward by the preset step size through the position adjustment function; if the upper side is still intersected after detection, it will move downward by twice the step size, and the adjustment strategy for the intersection of the remaining sides is consistent with the intersection of the upper side, until the four upper, lower, left and right sides are adjusted to have no intersection, then the final position for inserting the buffer will be determined.

[0033] S3: Divide the circuit into diamond-shaped areas and insert middle-level buffers.

[0034] In this step, since the middle-level division requires multi-level division, the first-level middle-level division is named , the last middle layer is named In the middle layer During the buffer insertion process, the underlying inserted buffer needs to be The basic unit is then divided into diamond shapes to Figure 5For example, the entire area is divided into several rhombuses and triangles at the edges, where the red point represents the geometric center position where the middle buffer will be inserted. The reason for using rhombus mesh division is as follows: Figure 6 As shown, Figure 6 The rectangle shown in (a) and Figure 6 The diamonds shown in (b) have equal areas, the blue dot represents the geometric center, and the black triangle represents the basic unit in the area; since the calculation of the entire circuit delay is based on the Manhattan distance, as shown by the red line in the figure, compared with rectangular division, the use of diamond division can make the maximum Manhattan distance from the point in the area to the geometric center smaller, thereby achieving lower clock delay and clock skew.

[0035] When using the improved diamond mesh partitioning algorithm to partition the circuit area with the bottom buffer as the basic unit, the ratio of the number of bottom buffers to the maximum fan-out number is calculated, and then rounded up. The middle layer is initially divided according to the value to determine whether the number of basic units in a single area meets the maximum fan-out limit. If not, the basic unit farthest from the geometric center will be found and redistributed until the number of basic units in each area meets the maximum fan-out limit. Then the net_rc value between the geometric center and each basic unit is summed and compared with the maximum net_rc value. If it exceeds the limit, the basic unit farthest from the geometric center is redistributed. Finally, the buffer is inserted at the geometric center for overlap detection. If the overlap rate is 0, the middle buffer is inserted. Otherwise, the position is adjusted through the position adjustment function. Because the basic unit is changed from a register to a bottom buffer, the position adjustment function will modify the size parameters until all restrictions are met before insertion.

[0036] exist After the layer buffer is inserted, The layer will be The buffer inserted in is divided into basic units, and this step will be iterated until The layer buffer is inserted, that is, divided into The number of buffers is between [30,40]. When the number reaches this range, an H-tree structure with good clock skew and clock delay can be generated to prepare for the insertion of the top-level buffer. These operations can ensure the optimization of the overall clock delay and clock skew.

[0037] S4: Insert into the top-level buffer based on the H-tree structure.

[0038] In this step, since the top-level partitioning also requires multi-level partitioning, the first-level top-level partitioning is named , the last top-level partition is named The H tree structure is a symmetrical and recursive fractal clock distribution structure. This step inserts the top-level buffer through the H tree structure. After the H tree structure is generated, the buffer in the H tree structure is dynamically adjusted. When the kth layer (k ≥3), the dynamic adjustment function will be called to fine-tune the position of each buffer in the current layer. Since the buffer of layer k is generated at the geometric center of the buffer of layer k-1, the clock skew is small, so the net_rc value from the buffer of layer k to the buffer of layer k-2 needs to be considered. For example, there is a buffer p in layer k, and there are two buffers of layer k-1 connected to p, namely q1 and q2. The maximum net_rc value from q1 and q2 of layer k-1 to the buffer of layer k-2 is calculated, recorded as c1 and c2, and the net_rc value from p to q1 and q2 is added, recorded as net_rc1 and net_rc2, and the values ​​of net_rc1+c1 and net_rc2+c2 are compared. If net_rc1+c1 is larger, it is adjusted to the direction of q1. If net_rc1+c2 is larger, it is adjusted to the direction of q2. If the two are equal, the position of p is not adjusted. Figure 7 For example, after generating the basic H-tree structure, Figure 7 As shown in (a), the points represent the buffers of the top layer, and different colors represent the buffers of different layers in the top layer. It can be seen that the distance from buf_1 to the orange points, i.e., buf_2 and buf_3, is consistent, and the distance to buf_4, buf_5, buf_6, and buf_7 is also consistent. However, the distance from buf_1 to buf_8 and buf_9 is relatively large, which will cause a large clock skew. Therefore, the position of the buffer of buf_2 needs to be dynamically adjusted to balance the clock skew. The adjusted schematic diagram is shown in the figure below. Figure 7 As shown in (b), inserting the top-level buffer using this structure can ensure that the clock skew of the top level is 0.

[0039] After the top-level buffer is inserted, a dynamic clock optimization strategy needs to be used to continue to dynamically adjust the position of the top-level buffer to optimize the global clock skew and clock delay. This method determines whether the buffer position needs to be adjusted by determining the coordinate information. For example, there is a k-layer buffer b1, and the k-1-layer buffer connected to this buffer is b2, and the k-2-layer buffer connected to b2 is b3. If the x-coordinate of b3 is between the horizontal coordinates of b1 and b2, then b2 needs to be adjusted toward b1 along the x-coordinate. If the y-coordinate of b3 is between the y-coordinates of b1 and b2, then b2 needs to be adjusted toward b1 along the y-coordinate. Figure 8 Taking the schematic diagram (a) as an example, buf_11 is A buffer inserted in the layer, buf_12 and buf_13 are The buffer inserted in the layer, buf_10 is The buffer inserted in the layer, because The buf_11 of the layer is inserted at the center of the distance between buf_12 and buf_13. Therefore, directly inserting buf_1 may cause the transmission route to be repeated, resulting in an increase in the overall delay, and may also cause an increase in the overall clock skew. Therefore, the position of buf_11 should be dynamically adjusted according to the positions of buf_12 and buf_13, such as Figure 8 As shown in (b), the problem of increased clock delay and aggravated clock skew caused by detours is avoided. This step still requires overlap detection before determining the final insertion position of the top-level buffer, and connects the clock source after the buffer is inserted.

[0040] S5: Output optimized circuit design information.

[0041] After the optimization is completed, the optimized circuit clock tree synthesis information is output to the file, including register location information, buffer insertion location information, optimized signal topology structure, and network connection relationship between registers and buffers and between different buffers. The output information facilitates subsequent circuit verification and iterative design.

[0042] The method of the present invention is verified by specific experiments below.

[0043] This embodiment selects a traditional heuristic algorithm: Greedy Heuristic (greedy algorithm) to perform a comparative test with the method of the present invention. In the test, three different circuits (case 1, case 2, case 3) are selected. The three circuits are all circuit files containing FFs with uneven distribution of 100K~200K, and all FFs are of the same type and size. The test results are compared by means of scientific demonstration to verify the real effect of the method of the present invention.

[0044] Table 1: Results of the method of the present invention

[0045]

[0046] Table 2: Running results of the clock tree synthesis optimization method based on the greedy algorithm

[0047]

[0048] The results show that the traditional method can achieve the expected clock tree synthesis and optimization effect in smaller-scale circuits, but its running time is prolonged and the optimization accuracy is significantly reduced in medium-scale and larger-scale circuits. The clock tree synthesis optimization method based on hierarchical region partitioning and buffer insertion effectively optimizes clock delay and clock skew within a reasonable algorithm running time, and significantly reduces the number of buffer insertions. For example, in case 3, the number of register insertions is reduced to 3293, which is 276 less than the heuristic algorithm. At the same time, the method performs well in optimizing skew and latency, with the skew reduced by about 7 picoseconds and the latency reduced by about 10 picoseconds in case 3, and the skew reduced by about 2 picoseconds in case 2, which comprehensively improves the comprehensive performance and design reliability of the clock tree.

[0049] The clock tree comprehensive optimization system based on hierarchical region division and buffer insertion of the present invention comprises: A circuit information extraction unit, used to extract circuit information, including register connection information and signal topology structure; A bottom buffer insertion unit is used to divide the circuit area by using a rectangular cutting method using all registers as basic units, and insert a bottom buffer at the geometric center point of each first area obtained after the division; The middle-layer buffer insertion unit is used to divide the circuit area by using the upper-layer buffer as the basic unit and using the diamond grid division method, and insert the middle-layer buffer at the geometric center point of each second area obtained after the division; until n layers of middle-layer buffers are inserted; n is the number of layers of the middle-layer buffers; The upper buffer of the nth layer middle buffer is the n-1th layer middle buffer, and the upper buffer of the 1st layer middle buffer is the bottom buffer; A top buffer insertion unit, used for inserting m layers of top buffers according to an H-tree structure; m is the number of layers of the top buffers; The clock tree synthesis optimization result output unit is used to output the circuit information after the buffer is inserted, including the location information of the bottom buffer, the middle buffer and the top buffer, the signal topology structure after the buffer is inserted, and the connection relationship between the register and the buffer.

[0050] The electronic device described in the present invention includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the computer program is loaded into the processor, the clock tree synthesis optimization method based on hierarchical region division and buffer insertion is implemented.

[0051] The computer-readable storage medium of the present invention stores a computer program, and when the computer program is executed by a processor, the clock tree synthesis optimization method based on hierarchical region division and buffer insertion is implemented.

[0052] The computer-readable storage media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, flash memory, or any other medium that can be used to store program code in the form of instructions or data structures and that can be accessed by a computer.

[0053] The processor is used to execute the computer program stored in the memory to implement each step of the method involved in the above embodiment.

Claims

1. A clock tree synthesis optimization method based on hierarchical region partitioning and buffer insertion, characterized in that: The steps include: Step 1, extracting circuit information, including register connection information and signal topology; Step 2, taking all registers as basic units, dividing the circuit area by using a rectangular cutting method, and inserting a bottom buffer at the geometric center point of each first area obtained after the division; Step 3, using the upper layer buffer as the basic unit, dividing the circuit area using the diamond grid division method, inserting the middle layer buffer at the geometric center point of each second area obtained after the division; repeating step 3 until n layers of middle layer buffers are inserted; n is the number of layers of the middle layer buffer; The upper buffer of the nth layer middle buffer is the n-1th layer middle buffer, and the upper buffer of the 1st layer middle buffer is the bottom buffer; Step 4, insert the m-layer top buffer according to the H-tree structure; m is the number of layers of the top buffer; Step 5, output the circuit information after the buffer is inserted, including the location information of the bottom buffer, the middle buffer and the top buffer, the signal topology after the buffer is inserted, and the connection relationship between the register and the buffer.

2. The clock tree comprehensive optimization method based on hierarchical region partitioning and buffer insertion according to claim 1, characterized in that: In step 2, a hierarchical clustering algorithm is used to divide each first region into a number of point sets according to the maximum fan-out number limit, where the points in the point set are registers; the geometric center of each point set is calculated and inserted into the bottom buffer.

3. The clock tree comprehensive optimization method based on hierarchical region partitioning and buffer insertion according to claim 1, characterized in that: In step 2 and step 3, overlap detection is performed on each bottom layer buffer and middle layer buffer. If there is overlap, the position of the geometric center is adjusted and then the bottom layer buffer and the middle layer buffer are inserted, including the following steps: Check whether the edges of the bottom buffer and the middle buffer intersect with other buffers and / or registers. If so, move the position of the geometric center in the opposite direction of the intersecting edges, and then re-perform overlap detection until any edge of the bottom buffer and the middle buffer does not intersect with other buffers and / or registers.

4. The clock tree comprehensive optimization method based on hierarchical region partitioning and buffer insertion according to claim 1, characterized in that: In step 3, the above-layer buffer is used as a basic unit, the circuit area is divided by using a diamond grid division method, and the middle-layer buffer is inserted at the geometric center point of each second area obtained after the division, including: Calculate the ratio of the number of buffers in the previous layer to the maximum fan-out number, round up the ratio to get the middle-layer division number, perform diamond division according to the middle-layer division number to get several second areas, calculate whether the number of basic units in each second area meets the maximum fan-out number limit, if not, re-divide the basic unit farthest from the geometric center of the second area until each second area meets the maximum fan-out number limit; calculate the sum of the net_rc values ​​between the basic unit and the geometric center in each second area ,like If the maximum net_rc value limit in the second region is exceeded, the basic unit farthest from the geometric center of the second region is re-divided until each second region meets the maximum net_rc value limit; a middle buffer is inserted at the geometric center point of each second region; The net_rc value is , where D is the Manhattan distance between the basic unit and the geometric center, r and c are the resistance and capacitance values ​​of the line between the basic unit and the geometric center, respectively.

5. The clock tree comprehensive optimization method based on hierarchical region partitioning and buffer insertion according to claim 1, characterized in that: In step 3, the number of buffers in layer n is in the range of [30,40].

6. The clock tree comprehensive optimization method based on hierarchical region partitioning and buffer insertion according to claim 1, characterized in that: In step 4, for any two k-1th layer top buffers q1 and q2 connected to any k-th layer top buffer p, the net_rc values ​​from p to q1 and q2 are calculated, denoted as net_rc1 and net_rc2, respectively, and the maximum net_rc values ​​from q1 and q2 to the k-2th layer top buffer connected to them are calculated, denoted as c1 and c2; where k=3,4,5,…,m; If net_rc1+c1>net_rc2+c2, adjust the position of p toward q1; if net_rc1+c1<net_rc2+c2, adjust the position of p toward q2; if net_rc1+c1=net_rc2+c2, do not adjust the position of p; The net_rc value is , where D is the Manhattan distance between buffers, r and c are the resistance and capacitance of the wires between buffers, respectively.

7. The clock tree comprehensive optimization method based on hierarchical region partitioning and buffer insertion according to claim 1, characterized in that: In step 4, for any k-th layer top buffer p, any k-1-th layer top buffer q1 connected to p, and any k-2-th layer top buffer q3 connected to q1, where k=3, 4, 5, …, m; if the horizontal coordinate of q3 is between the horizontal coordinates of p and q1, the position of q1 is adjusted along the horizontal coordinate in the direction of p; if the vertical coordinate of q3 is between the vertical coordinates of p and q1, the position of q1 is adjusted along the vertical coordinate in the direction of p.

8. A clock tree synthesis optimization system based on hierarchical region partitioning and buffer insertion, characterized in that: include: A circuit information extraction unit, used to extract circuit information, including register connection information and signal topology; A bottom buffer insertion unit is used to divide the circuit area by using a rectangular cutting method using all registers as basic units, and insert a bottom buffer at the geometric center point of each first area obtained after the division; The middle-layer buffer insertion unit is used to divide the circuit area by using the upper-layer buffer as the basic unit using the diamond grid division method, and insert the middle-layer buffer at the geometric center point of each second area obtained after the division; repeat step 3 until n layers of middle-layer buffers are inserted; n is the number of layers of the middle-layer buffers; The upper buffer of the nth layer middle buffer is the n-1th layer middle buffer, and the upper buffer of the 1st layer middle buffer is the bottom buffer; A top-level buffer insertion unit, used for inserting m-level top-level buffers according to the H-tree structure; m is the number of layers of the top buffer; The clock tree synthesis optimization result output unit is used to output the circuit information after the buffer is inserted, including the location information of the bottom buffer, the middle buffer and the top buffer, the signal topology structure after the buffer is inserted, and the connection relationship between the register and the buffer.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the computer program is loaded into a processor, the clock tree synthesis optimization method based on hierarchical region partitioning and buffer insertion according to any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the clock tree synthesis optimization method based on hierarchical region partitioning and buffer insertion according to any one of claims 1 to 7 is implemented.

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