Acceleration device and method for calculating Gamma correction algorithm

Abstract

The invention discloses an acceleration device and method for calculating a Gamma correction algorithm, which can remarkably improve the execution speed of the Gamma correction algorithm and effectively solve the bottleneck problem of a traditional general processor in the aspect of processing efficiency. The device comprises a value taking unit, a decoding unit, an execution unit, a memory access unit and a write-back unit, the valuing unit comprises an instruction memory, a program counter, an instruction prefetching unit, a branch prediction unit and a pre-decoding unit; the execution unit comprises a branch instruction module, an ALU module, an MUL module, a DIV module, an FPU module and a GAMMA unit which shares partial logic resources with the ALU module and the FPU module; the memory access unit comprises a data memory; the write-back unit comprises an integer register file GPR and a floating point register file FPR.

Description

Technical Field

[0001] The present invention relates to the technical field of computer image preprocessing, and in particular to an acceleration device for calculating a gamma correction algorithm, and an acceleration method for calculating a gamma correction algorithm. Background Art

[0002] Gamma correction is an important image preprocessing technology that plays a critical role in improving image display quality. In the image acquisition, processing and display chain, due to the nonlinear electro-optical conversion characteristics of the display device, if the image is not gamma corrected, the brightness and color reproduction of the image will be seriously distorted and cannot meet the requirements of high-quality visual experience. When the traditional gamma correction algorithm is implemented on a general-purpose processor, due to the high complexity of the algorithm, it often faces the dilemma of low processing efficiency and is difficult to meet application scenarios with strict speed requirements such as high-definition video processing and real-time image rendering.

[0003] As an emerging open source instruction set architecture, RISC-V architecture has significant advantages such as simplicity, strong customizability and modular design, and has emerged in many fields such as embedded systems, the Internet of Things and high-performance computing. How to fully utilize the advantages of RISC-V architecture to deeply optimize and accelerate the gamma correction algorithm is an urgent problem to be solved in the current field of image preprocessing technology. Summary of the invention

[0004] In order to overcome the defects of the prior art, the technical problem to be solved by the present invention is to provide an acceleration device for calculating the Gamma correction algorithm, which can significantly improve the execution speed of the Gamma correction algorithm and effectively solve the bottleneck problem of traditional general-purpose processors in processing efficiency.

[0005] The technical scheme of the present invention is: the acceleration device for calculating the Gamma correction algorithm comprises: a value acquisition unit, a decoding unit, an execution unit, a memory access unit and a write-back unit; the value acquisition unit comprises an instruction memory, a program counter, an instruction pre-fetch unit, a branch prediction unit and a pre-decoding unit; the execution unit comprises a branch instruction module, an ALU module, a MUL module, a DIV module, an FPU module, and a GAMMA unit which shares some logic resources with the ALU module and the FPU module; the memory access unit comprises a data memory; the write-back unit comprises an integer register stack GPR and a floating point register stack FPR; The opcode field of the GAMMA unit in the pre-decoding unit is constructed by a custom encoding form, using 7'b0001011 as the opcode. The circuit of the opcode recognition part includes a three-input NAND gate, two three-input AND gates and a NOT gate; The instruction memory stores the machine code converted by the RISC-V program through the assembler and compiler; the program counter stores and updates the current instruction address; the branch prediction unit predicts the direction and target address of the branch instruction; the instruction prefetch unit judges and decodes the compressed instruction set, translating the 16-bit compressed instructions into 32-bit basic instructions; the data memory stores the data when the program is running and is accessed by load / store instructions; the register stack is located inside the processor and stores operands and intermediate results.

[0006] The beneficial technical effects of the present invention are as follows: (1) Taking advantage of the flexibility and customizability of the RISC-V instruction set, a special customized instruction set was designed to reduce the number of instructions required for image preprocessing tasks, giving full play to the hardware acceleration features of RISC-V and meeting the needs of image processing applications with high real-time requirements.

[0007] (2) A customized instruction set is used to optimize the gamma correction algorithm, and some resources are shared with the existing integer instruction set and floating-point instruction set, which reduces the large amount of general computing resources required when running on a general-purpose processor. At the same time, the implementation of the customized instruction set is more efficient in resource utilization than pure hardware implementation, reducing the hardware resource requirements of the entire system.

[0008] (3) Through a detailed analysis of the Gamma algorithm, an optimal circuit structure that conforms to the algorithm was developed, and instruction design was performed rationally, which reduced additional resource consumption and the burden of value retrieval and decoding after adding custom instructions.

[0009] A method for accelerating the calculation of a gamma correction algorithm is also provided, comprising the following steps: (1) The instruction memory stores the machine code converted by the RISC-V program through the assembler and compiler. The program counter stores and updates the current instruction address. The branch prediction unit predicts the direction and target address of the branch instruction. The instruction prefetch unit judges and decodes the compressed instructions and translates the 16-bit compressed instructions into 32-bit basic instructions. The data memory stores the data during program execution and is accessed by load / store instructions. The register stack is located inside the processor and stores operands and intermediate results. (2) The instruction is loaded into the instruction memory. The value fetching unit fetches the required instruction from the instruction memory according to the program counter and determines whether it is a compressed instruction. If it is a compressed instruction, it enters the instruction prefetching unit and translates the 16-bit compressed instruction into a 32-bit instruction. At the same time, the value fetching unit is paused to determine whether the next 16-bit instruction is a compressed instruction. If not, it is concatenated with the lower 16 bits of the 32-bit instruction. If it is, it enters the compressed instruction translation process again. (3) The translated 32-bit instruction or normal 32-bit instruction is first transmitted to the instruction pre-decoding unit, which inputs the 32-bit instruction and outputs the source operand and destination operand registers of the instruction and the control signal for loading non-operation type instructions; (4) The 32-bit instruction and pre-decoding unit are sent to the decoding unit. The decoding unit decodes the opcode, funct3, and funct7 in detail to obtain the detailed operation code of the general instruction, obtain all the detailed information of a single instruction, and obtain the control signal. The control signal and source operand are then transmitted to the execution unit. The execution unit determines which operation unit the instruction flows to based on the control signal, enters the operation unit to obtain the result, and sends it to the memory access stage. (5) If it is a load-store instruction, it enters the load-store unit and interacts with the data memory; if it is an instruction other than load-store, it directly enters the write-back unit and interacts with the integer register file or floating-point register file for data. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a schematic diagram of the structure of an acceleration device for calculating a gamma correction algorithm according to the present invention.

[0011] Figure 2 A flowchart of a processor front end including a compression-to-zero set decoding unit is shown.

[0012] Figure 3 It is a schematic diagram of the specific structure from the pre-decoding module to the decoding unit.

[0013] Figure 4 Schematic diagram of the GAMMA identification circuit in the pre-decoding unit.

[0014] Figure 5 It is a schematic diagram of the funct7 decoding circuit in the decoding unit.

[0015] Figure 6 Schematic diagram of the GAMMA unit in the execution unit.

[0016] Figure 7 Schematic diagram of the structure of the data normalization unit.

[0017] Figure 8 Schematic diagram of the structure of the power function operation unit.

[0018] Fig. 9 Schematic diagram of the structure of the data denormalization unit. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0020] In order to make the description of the present disclosure more detailed and complete, the following provides an illustrative description of the implementation and specific embodiments of the present invention; however, this is not the only form of implementing or using the specific embodiments of the present invention. The implementation covers the features of multiple specific embodiments and the method steps and sequences used to construct and operate these specific embodiments. However, other specific embodiments can also be used to achieve the same or equivalent functions and step sequences.

[0021] like Figure 1 As shown, the acceleration device for calculating the Gamma correction algorithm includes: a value acquisition unit, a decoding unit, an execution unit, a memory access unit and a write-back unit; the value acquisition unit includes an instruction memory, a program counter, an instruction pre-fetch unit, a branch prediction unit and a pre-decoding unit; the execution unit includes a branch instruction module, an ALU (Arithmetic Logic Unit) module, a MUL (Multiple) module, a DIV (Division) module, an FPU (Floating-Point Unit) module, and a GAMMA unit that shares some logic resources with the ALU module and the FPU module; the memory access unit includes a data memory; the write-back unit includes an integer register stack GPR (General Purpose Register) and a floating-point register stack FPR (Floating-Point Register); The opcode field of the GAMMA unit in the pre-decoding unit is constructed by a custom encoding form, using 7'b0001011 as the opcode. The circuit of the opcode recognition part includes a three-input NAND gate, two three-input AND gates and a NOT gate; The instruction memory stores the machine code converted by the RISC-V program through the assembler and compiler; the program counter stores and updates the current instruction address; the branch prediction unit predicts the direction and target address of the branch instruction; the instruction prefetch unit judges and decodes the compressed instruction set, translating the 16-bit compressed instructions into 32-bit basic instructions; the data memory stores the data when the program is running and is accessed by load / store instructions; the register stack is located inside the processor and stores operands and intermediate results.

[0022] The beneficial technical effects of the present invention are as follows: (1) Taking advantage of the flexibility and customizability of the RISC-V instruction set, a special customized instruction set was designed to reduce the number of instructions required for image preprocessing tasks, giving full play to the hardware acceleration features of RISC-V and meeting the needs of image processing applications with high real-time requirements.

[0023] (2) A customized instruction set is used to optimize the gamma correction algorithm, and some resources are shared with the existing integer instruction set and floating-point instruction set, which reduces the large amount of general computing resources required when running on a general-purpose processor. At the same time, the implementation of the customized instruction set is more efficient in resource utilization than pure hardware implementation, reducing the hardware resource requirements of the entire system.

[0024] (3) Through a detailed analysis of the Gamma algorithm, an optimal circuit structure that conforms to the algorithm was developed, and instruction design was performed rationally, which reduced additional resource consumption and the burden of value retrieval and decoding after adding custom instructions.

[0025] Preferably, the Gamma correction formula in the GAMMA unit is: , In the actual operation process, the specific steps are: , , , , in: is the input pixel value, the value range is 0≤ ≤255; γ is the γ correction value, and its value range is 0<γ<2.5; is the output pixel value, the value range is 0≤ ≤255; is the normalized pixel value, ranging from 0≤ ≤1; The value range is -∞< ≤0; The value range is -∞< ≤0; The value range is 0< ≤1.

[0026] Preferably, the instruction set of the GAMMA unit is defined as R-type instructions in the floating-point type, with a total of 5 instructions; opcode uses custom-0 unit, and identifies the custom instruction in GAMMA unit according to the opcode code; funct7 is used to distinguish the specific instructions in GAMMA unit; funct3 is all set to 000; rs2 is all set to 00000; funct7 is encoded by one-hot code; The funct7 decoding circuit in the decoding unit decodes the required instructions through a one-to-one correspondence according to the encoding format of the one-hot code.

[0027] Preferably, the instruction set of the GAMMA unit is defined as CA-type instructions in the compression instruction type, with a total of 5 items; A compressed instruction set using a custom Gamma correction algorithm is used in the value-taking unit. The length of the instructions in the compressed instruction set is 16 bits. The compressed instruction format of the custom Gamma correction algorithm is distinguished from the existing instructions by adjusting the encoding of op and funct2. The funct6 field of the compressed instruction set is encoded using a sequential shift sequence and a one-hot code, and each instruction only verifies and detects one bit of data.

[0028] Preferably, the GAMMA unit performs Gamma correction processing on the input image, including a data normalization unit, a lookup table unit, a power operation unit, and a data denormalization unit.

[0029] Preferably, the data normalization unit comprises a serial floating point adder and a floating point shifter, which maps the input pixel value in the integer range of 0-255 to a real number range of 0-1.

[0030] Preferably, the lookup table unit stores the γ correction values ​​corresponding to different gray value regions, and outputs the corresponding γ correction value according to the input pixel value I.

[0031] Preferably, the power operation unit includes a floating-point reciprocal operator, a logarithm operator, a floating-point multiplier and an exponential operator, and pre-compensates the normalized pixel value to convert the data from the linear space to a non-linear space suitable for the display device.

[0032] Preferably, the data denormalization unit includes a serial floating-point shifter and a floating-point subtractor, which maps the result of the power function operation after the gamma correction back to an integer range between 0 and 255.

[0033] A method for accelerating the calculation of a gamma correction algorithm is also provided, comprising the following steps: (1) The instruction memory stores the machine code converted by the RISC-V program through the assembler and compiler. The program counter stores and updates the current instruction address. The branch prediction unit predicts the direction and target address of the branch instruction. The instruction prefetch unit judges and decodes the compressed instructions and translates the 16-bit compressed instructions into 32-bit basic instructions. The data memory stores the data during program execution and is accessed by load / store instructions. The register stack is located inside the processor and stores operands and intermediate results. (2) The instruction is loaded into the instruction memory. The value fetching unit fetches the required instruction from the instruction memory according to the program counter and determines whether it is a compressed instruction. If it is a compressed instruction, it enters the instruction prefetching unit and translates the 16-bit compressed instruction into a 32-bit instruction. At the same time, the value fetching unit is paused to determine whether the next 16-bit instruction is a compressed instruction. If not, it is concatenated with the lower 16 bits of the 32-bit instruction. If it is, it enters the compressed instruction translation process again. (3) The translated 32-bit instruction or normal 32-bit instruction is first transmitted to the instruction pre-decoding unit, which inputs the 32-bit instruction and outputs the source operand and destination operand registers of the instruction and the control signal for loading non-operation type instructions; (4) The 32-bit instruction and pre-decoding unit are sent to the decoding unit. The decoding unit decodes the opcode, funct3, and funct7 in detail to obtain the detailed operation code of the general instruction, obtain all the detailed information of a single instruction, and obtain the control signal. The control signal and source operand are then transmitted to the execution unit. The execution unit determines which operation unit the instruction flows to based on the control signal, enters the operation unit to obtain the result, and sends it to the memory access stage. (5) If it is a load-store instruction, it enters the load-store unit and interacts with the data memory; if it is an instruction other than load-store, it directly enters the write-back unit and interacts with the integer register file or floating-point register file for data.

[0034] The specific embodiments of the present invention are described in more detail below.

[0035] like Figure 1 The figure shows the overall circuit structure of the GAMMA correction algorithm acceleration device. The processor architecture based on RISC-V includes a value acquisition unit, a decoding unit, an execution unit, a memory access unit and a write-back unit. The value acquisition unit includes an instruction memory, a program counter, an instruction pre-fetch unit, a branch prediction unit and a pre-decoding unit. The memory access unit includes a branch instruction module, an ALU, a MUL, a DIV and an FPU module, and a GAMMA unit that shares some logic resources with the ALU and the FPU. The memory access unit includes a data memory, and the write-back unit includes an integer register file and a floating-point register file.

[0036] The instruction memory is responsible for storing the machine code converted by the RISC-V program through the assembler and compiler; the program counter is responsible for storing and updating the current instruction address to ensure that instructions are executed in sequence or by jump; the branch prediction unit predicts the direction and target address of branch instructions, reduces pipeline pauses, and improves processor performance; the instruction prefetch unit is responsible for judging and decoding compressed instructions, translating 16-bit compressed instructions into 32-bit basic instructions; the data memory is used to store data during program execution and is accessed by load / store instructions; the register stack is located inside the processor and is used to store operands and intermediate results.

[0037] The instruction is loaded into the instruction memory, and the value fetching unit fetches the required instruction from the instruction memory according to the program counter to determine whether it is a compressed instruction. If it is a compressed instruction, it enters the instruction prefetching unit to translate the 16-bit compressed instruction into a 32-bit instruction. At the same time, the value fetching unit is paused to determine whether the next 16-bit instruction is a compressed instruction. If not, it is spliced ​​with the lower 16 bits of the 32-bit instruction. If it is, it enters the translation process of the compressed instruction again; the translated 32-bit instruction or normal 32-bit instruction is first transmitted to the instruction pre-decoding unit, which inputs the 32-bit instruction and outputs the source operand and destination operand registers of the instruction as well as the control information of non-operation type instructions such as load and store instructions. number, thereby reducing the pressure of the decoding stage; the 32-bit instruction and the pre-decoding unit are transmitted to the decoding unit, the decoding unit decodes the opcode, funct3 and funct7 in detail, obtains the detailed operation code of the large category of instructions, obtains all the detailed information of a single instruction, and obtains the control signal; the control signal and the source operand are then transmitted to the execution unit, the execution unit determines which operation unit the instruction flows to according to the control signal, enters the operation unit to obtain the result, and transmits it to the memory access stage; if it is a load-store instruction, it enters the load-store unit and interacts with the data memory; if it is an instruction other than load-store, it directly enters the write-back unit to interact with the integer register stack or the floating-point register stack.

[0038] The gamma correction formula is: , in: : Input pixel value, the value range is 0≤ ≤255; γ: γ correction value, the value range is 0<γ<2.5; : Output pixel value, the value range is 0≤ ≤255.

[0039] Gamma correction specific steps: Normalization: , Power operation: , Denormalization: , in: The power module is converted to: , : is the normalized pixel value, the value range is 0≤ ≤1; : The value range is -∞< ≤0; : The value range is -∞< ≤0; : The value range is 0< ≤1.

[0040] According to the analysis and decomposition of the algorithm, this type of instruction belongs to the floating-point operation type, and involves reciprocal operation, logarithmic operation, and exponential operation. Therefore, a total of 5 instructions are customized, and the customized instructions are encoded using the R-type instruction encoding format in the floating-point type. The customized encoding part includes opcode, funct7, and funct3. Here, opcode uses custom-0 units to distinguish it from existing instructions. The customized instructions in the GAMMA unit can be directly identified according to the opcode encoding. Funct7 is used to distinguish specific instructions in the GAMMA unit. It is written in one-hot code, and the characteristic of one-hot code that only contains one valid value at a time is used to reduce the decoding burden. Funct3 is all set to 000. Since each instruction is a single operand, rs2 is also all set to 00000. Table 1 shows the specific encoding format.

[0041] Table 1

[0042] The processor has a configurable compressed instruction set module, which is implemented in the value-taking unit using the compressed instruction set. The length of the instructions in the compressed instruction set is 16 bits, which greatly reduces the resource consumption of the instruction memory compared to the normal 32-bit instructions, so as to reduce the burden on the value-taking unit. The 16-bit compressed instruction is composed of the CA format segment of the RISC-V compressed instruction set, which consists of funct6 (6 bits), rd / rs1 (3 bits), funct2 (2 bits), rs2 (3 bits) and op (2 bits). Table 2 shows the specific 16-bit encoding format.

[0043] Table 2

[0044] The function of the fnorm instruction is to normalize the input pixels, perform floating-point addition and then shift; the function of the frenorm instruction is to perform anti-normalization, perform floating-point shift and then subtract; the function of the frec instruction is to perform floating-point reciprocal; the function of the fln instruction is to perform floating-point logarithm; and the function of the fexp instruction is to perform floating-point exponentiation.

[0045] Using shift registers in the normalization and denormalization units to multiply or divide by 256 can directly add / subtract 8 to the exponent, but there may be insufficient exponent bits, and overflow or underflow may occur. At this time, the floating-point overflow needs to be adjusted. This can be avoided by checking the range of the input value.

[0046] like Figure 2 As shown, it is a flowchart of the decoding unit of the processor front end including the compressed instruction set: The 16-bit compressed instruction first passes through the instruction prefetch unit, where it is decoded according to the compressed instruction set specification in the RISC-V official manual. By identifying op, funct6, and funct2, a 32-bit custom Gamma instruction is generated. For example, when op and funct2 are 2'b01 and 2'b10 respectively, the current instruction is the instruction in the GAMMA unit. At this time, the 16-bit data is expanded to 32 bits: funct6 is mapped to funct7, op (2'b01) is replaced with opcode (7'b0001011), funct2 (2'b10) is replaced with funct3 (3'b000), and other source operands and destination operands are mapped to 5-bit rd or rs1 / rs2, and the high bits are filled with 0.

[0047] like Figure 3 As shown, it is a schematic diagram of the specific structure from the pre-decoding module to the decoding unit: In the instruction fetch stage, through the opcode characteristics of the custom instruction set, the pre-decoding module can directly identify the instructions belonging to the GAMMA unit, generate the Gamma-en enable signal, and decode the source register (Rs), the destination register number (Rd), the load / store instruction (Load / Store) signal, and the register enable signal. The above signals pass through the decoding stage. In the decoding module, the 32-bit instruction recognizes the 5 instructions in the Gamma unit according to funct7, and other RISC-V standard instruction sets are identified through funct7 and funct3, generating ALU-Ctrl, Ld-Ctrl, St-Ctrl, Bru-Ctrl, Gamma-Ctrl and Imm signals, of which the suffix Ctrl is the control signal of the instruction, and Imm is the immediate value.

[0048] like Figure 4As shown, the GAMMA unit opcode recognition circuit in the pre-decoding unit: The Gamma identification circuit consists of a three-input NAND gate (numbered 1), two three-input AND gates (numbered 2 and 3), and a NOT gate. opcode[6:4] is input to device 1 to get the result out1; opcode[1:0] and opcode[3] are input to device 2 to get the result out2; opcode[2] is input to the NOT gate to get the result out3; out1, out2, and out3 are input to device 3 to get the result Gamma-en enable signal. If the signal is 1, the instruction is a custom instruction in the Gamma unit. If it is 0, the signal is not a custom instruction in the Gamma unit.

[0049] like Figure 5 As shown, the funct7 decoding circuit in the decoding unit: When the result of the opcode recognition circuit in the pre-decoding stage is 1, the decoding stage starts to decode funct7 and recognizes the specific custom instruction. Funct7 takes the [31:25] bits of the 32-bit instruction. The funct7 of the 5 instructions of the GAMMA unit is designed as a one-hot code format so that each encoding has only one valid value. Figure 3 , funct7 is 7'b0000001 corresponding to the fnorm instruction, funct7 is 7'b0000010 corresponding to the frenorm instruction, funct7 is 7'b0000100 corresponding to the frec instruction, funct7 is 7'b0001000 corresponding to the fln instruction, and funct7 is 7'b0010000 corresponding to the fexp instruction. Through this one-to-one correspondence, the required instructions are decoded.

[0050] like Figure 6 As shown in the figure, when the signal of the control unit enters the GAMMA unit in the execution unit, the Gamma correction first needs to perform data normalization on the input pixel value, and output the corresponding γ correction value according to the input pixel value, and then perform power operation, that is, pre-compensation processing on the normalized data, and finally perform data denormalization processing. The entire GAMMA unit includes a data normalization unit, a search unit, a power operation unit, and a data normalization unit.

[0051] According to the formula for data normalization, such as Figure 7 As shown, it includes a floating-point adder and a floating-point shifter, and is executed serially. It is used to map the pixel value in the input integer range of 0-255 to the real number range of 0-1, ensuring that the pixel value can be processed smoothly when performing the power function operation of Gamma correction.

[0052] According to the core's power unit, such as Figure 8 As shown in the figure, it includes a logarithm calculator, a floating-point reciprocal calculator, a floating-point multiplier, and an exponential calculator. The logarithm calculator is used to calculate The floating-point reciprocal unit is used to calculate the result of The floating-point multiplier multiplies the result of the logarithmic operation by the result of the reciprocal operation, and the output result is As input to the exponential operator, the exponential operator is used to calculate The result is the pixel value after Gamma correction. (0< ≤1).

[0053] Finally, the pixel values ​​need to be remapped back to the integer range of 0-255 so that the corrected brightness values ​​can be converted back to a format that the display device can recognize. Fig. 9 As shown, the data denormalization unit includes a floating-point shifter and a floating-point subtractor that are executed in series.

[0054] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Any simple modification, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention are still within the protection scope of the technical solution of the present invention.

Claims

1. An acceleration device for calculating a gamma correction algorithm, characterized in that: It includes: Value fetch unit, decoding unit, execution unit, memory access unit and write-back unit; The value fetching unit includes an instruction memory, a program counter, an instruction prefetching unit, a branch prediction unit, and a predecoding unit; the execution unit includes a branch instruction module, an ALU module, a MUL module, a DIV module, an FPU module, and a GAMMA unit that shares some logic resources with the ALU module and the FPU module; the memory access unit includes a data memory; the write-back unit includes an integer register file GPR and a floating point register file FPR; The opcode field of the GAMMA unit in the pre-decoding unit is constructed by a custom encoding form, using 7'b0001011 as the opcode. The circuit of the opcode recognition part includes a three-input NAND gate, two three-input AND gates and a NOT gate; The instruction memory stores the machine code converted by the RISC-V program through the assembler and compiler; the program counter stores and updates the current instruction address; the branch prediction unit predicts the direction and target address of the branch instruction; the instruction prefetch unit judges and decodes the compressed instruction set, translating the 16-bit compressed instructions into 32-bit basic instructions; the data memory stores the data when the program is running and is accessed by load / store instructions; the register stack is located inside the processor and stores operands and intermediate results.

2. The acceleration device for calculating the gamma correction algorithm according to claim 1, characterized in that: The gamma correction formula in the GAMMA unit is: ， ， ， ， ， in: is the input pixel value, the value range is 0≤ ≤255; γ is the γ correction value, and its value range is 0<γ<2.5; is the output pixel value, the value range is 0≤ ≤255; is the normalized pixel value, ranging from 0≤ ≤1; The value range is -∞< ≤0; The value range is -∞< ≤0; The value range is 0< ≤1.

3. The acceleration device for calculating the gamma correction algorithm according to claim 2, characterized in that: Define the instruction set of the GAMMA unit as R-type instructions in the floating-point type, a total of 5; opcode uses custom-0 unit, and identifies the custom instruction in GAMMA unit according to the opcode code; funct7 is used to distinguish the specific instructions in GAMMA unit; funct3 is all set to 000; rs2 is all set to 00000; funct7 is encoded by one-hot code; The funct7 decoding circuit in the decoding unit decodes the required instructions through a one-to-one correspondence according to the encoding format of the one-hot code.

4. The acceleration device for calculating the gamma correction algorithm according to claim 3, characterized in that: The instruction set of the GAMMA unit is defined as the CA-type instructions in the compressed instruction type, with a total of 5 items; A compressed instruction set of a custom Gamma correction algorithm is used in the value-taking unit. The length of the instructions in the compressed instruction set is 16 bits. The compressed instruction format of the custom Gamma correction algorithm is distinguished from the existing instructions by adjusting the encoding of op and funct2. The funct6 field of the compressed instruction set is encoded using sequential shift sequence and one-hot code, and each instruction only verifies and detects one bit of data.

5. The acceleration device for calculating the gamma correction algorithm according to claim 4, characterized in that: The GAMMA unit performs Gamma correction processing on the input image, including a data normalization unit, a lookup table unit, a power operation unit, and a data denormalization unit.

6. The acceleration device for calculating the gamma correction algorithm according to claim 5, characterized in that: The data normalization unit includes a serial floating-point adder and a floating-point shifter, which maps the input pixel value in the integer range of 0-255 to the real number range of 0-1.

7. The acceleration device for calculating the gamma correction algorithm according to claim 6, characterized in that: The lookup table unit stores the gamma correction values ​​corresponding to different grayscale value regions, and outputs the corresponding gamma correction value according to the input pixel value I.

8. The acceleration device for calculating the gamma correction algorithm according to claim 7, characterized in that: The power operation unit includes a floating-point reciprocal operator, a logarithm operator, a floating-point multiplier and an exponent operator, which pre-compensate the normalized pixel value to convert the data from a linear space to a non-linear space suitable for a display device.

9. The acceleration device for calculating the gamma correction algorithm according to claim 8, characterized in that: The data denormalization unit includes a serial floating-point shifter and a floating-point subtractor, which maps the result of the power function operation after the gamma correction back to an integer range between 0 and 255.

10. An acceleration method for calculating a gamma correction algorithm, using the acceleration device for calculating a gamma correction algorithm according to claim 1, characterized in that: It includes the following steps: (1) The instruction memory stores the machine code converted by the RISC-V program through the assembler and compiler. The program counter stores and updates the current instruction address. The branch prediction unit predicts the direction and target address of the branch instruction. The instruction prefetch unit judges and decodes the compressed instructions and translates the 16-bit compressed instructions into 32-bit basic instructions. The data memory stores the data during program execution and is accessed by load / store instructions. The register stack is located inside the processor and stores operands and intermediate results. (2) The instruction is loaded into the instruction memory. The value fetching unit fetches the required instruction from the instruction memory according to the program counter and determines whether it is a compressed instruction. If it is a compressed instruction, it enters the instruction prefetching unit and translates the 16-bit compressed instruction into a 32-bit instruction. At the same time, the value fetching unit is paused to determine whether the next 16-bit instruction is a compressed instruction. If not, it is concatenated with the lower 16 bits of the 32-bit instruction. If it is, it enters the compressed instruction translation process again. (3) The translated 32-bit instruction or normal 32-bit instruction is first transmitted to the instruction pre-decoding unit, which inputs the 32-bit instruction and outputs the source operand and destination operand registers of the instruction and the control signal for loading non-operation type instructions; (4) The 32-bit instruction and pre-decoding unit are sent to the decoding unit. The decoding unit decodes the opcode, funct3, and funct7 in detail to obtain the detailed operation code of the general instruction, obtain all the detailed information of a single instruction, and obtain the control signal. The control signal and source operand are then transmitted to the execution unit. The execution unit determines which operation unit the instruction flows to based on the control signal, enters the operation unit to obtain the result, and sends it to the memory access stage. (5) If it is a load-store instruction, it enters the load-store unit and interacts with the data memory; if it is an instruction other than load-store, it directly enters the write-back unit and interacts with the integer register file or floating-point register file for data.

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