Driver and display device

Abstract

The invention discloses a driver and a display device. The driver includes a plurality of stages, at least one of the plurality of stages including: an input circuit configured to transmit an input signal to a first node in response to a clock signal; a first transistor connected between the first node and the second node; a carry circuit configured to output a carry signal having a first high gate voltage when the second node has the first high gate voltage; and a level shift output circuit configured to output an output signal having a second high gate voltage higher than the first high gate voltage by level shifting the first high gate voltage of the second node.

Description

Technical Field

[0001] The present disclosure relates to a driver and a display device, and more particularly, to embodiments of a driver that provides signals to pixels of a display device and a display device including the driver. Background Art

[0002] The driver (e.g., gate driver and / or emission driver) of the display device can sequentially provide signals (e.g., gate signals and / or emission signals) to the pixels of the display panel row by row. In order to sequentially provide signals row by row, the driver can be implemented in the form of a shift register including multiple stages.

[0003] Generally speaking, the driver can operate based on a clock signal that switches between a high gate voltage and a low gate voltage. In addition, the high gate voltage of the clock signal can have a voltage level substantially the same as the voltage level of the high gate voltage of the output signal of the driver. Summary of the invention

[0004] Some embodiments of the present disclosure provide a driver capable of reducing power consumption.

[0005] Some embodiments of the present disclosure provide a display device including a driver capable of reducing power consumption.

[0006] According to an embodiment, the driver may include a plurality of stages. At least one of the plurality of stages includes: an input circuit configured to transmit an input signal to a first node in response to a clock signal; a first transistor connected between the first node and a second node; a carry circuit configured to output a carry signal having the first high gate voltage when the second node has a first high gate voltage; and a level shift output circuit configured to output an output signal having a second high gate voltage higher than the first high gate voltage by level shifting the first high gate voltage of the second node.

[0007] In an embodiment, the clock signal may switch between a low gate voltage and the first high gate voltage.

[0008] In an embodiment, the level shift output circuit may include at least one P-type metal oxide semiconductor (PMOS) transistor and at least one N-type metal oxide semiconductor (NMOS) transistor, and the first active region of the PMOS transistor may include a material different from a material of the second active region of the NMOS transistor.

[0009] In an embodiment, the level shift output circuit may further include at least one capacitor connected between the gate of the PMOS transistor and the gate of the NMOS transistor.

[0010] In an embodiment, the first transistor may include a gate receiving a low gate voltage, a first terminal connected to the first node, and a second terminal connected to the second node.

[0011] In an embodiment, the input circuit may include: a second transistor including a gate receiving the clock signal, a first terminal receiving the input signal, and a second terminal connected to the first node.

[0012] In an embodiment, the input circuit may further include: a third transistor including a gate receiving an inverted clock signal, a first terminal receiving the input signal, and a second terminal connected to the first node.

[0013] In an embodiment, the second transistor is a PMOS transistor and the third transistor is an NMOS transistor.

[0014] In an embodiment, the carry circuit may include: a fourth transistor including a gate connected to a third node, a first terminal receiving the first high gate voltage, and a second terminal connected to a carry node, outputting the carry signal at the carry node; and a fifth transistor including a gate connected to the second node, a first terminal connected to the carry node, and a second terminal receiving a low gate voltage.

[0015] In an embodiment, the carry circuit may further include: a first capacitor including a first electrode connected to the carry node and a second electrode connected to the second node.

[0016] In an embodiment, the level shift output circuit may include: a sixth transistor, including a gate connected to a fourth node, a first terminal receiving the second high gate voltage, and a second terminal connected to a third node; a seventh transistor, including a gate connected to the second node, a first terminal connected to the third node, and a second terminal receiving a low gate voltage; an eighth transistor, including a gate connected to the third node, a first terminal receiving the second high gate voltage, and a second terminal connected to the fourth node; a ninth transistor, including a gate connected to the second node, a first terminal connected to the fourth node, and a second terminal receiving the low gate voltage; and a second capacitor, including a first electrode connected to the fourth node and a second electrode connected to the second node.

[0017] In an embodiment, the sixth transistor, the eighth transistor, and the ninth transistor may be PMOS transistors, and the seventh transistor may be an NMOS transistor.

[0018] In an embodiment, the seventh transistor may further include a bottom gate, and the bottom gate may receive a bias voltage.

[0019] In an embodiment, the fourth node may be an output node at which the output signal is output.

[0020] In an embodiment, the level shift output circuit may further include: a tenth transistor, including a gate connected to the third node, a first terminal receiving the second high gate voltage, and a second terminal connected to an output node, at which the output signal is output; an eleventh transistor, including a gate connected to the second node, a first terminal connected to the output node, and a second terminal receiving the low gate voltage; and a third capacitor, including a first electrode connected to the output node and a second electrode connected to the second node.

[0021] In an embodiment, the level shift output circuit may include: a sixth transistor, including a gate connected to a fourth node, a first terminal receiving the second high gate voltage, and a second terminal connected to a third node; a seventh transistor, including a gate connected to the second node, a first terminal connected to the third node, and a second terminal receiving a low gate voltage; an eighth transistor, including a gate connected to the third node, a first terminal receiving the second high gate voltage, and a second terminal connected to the fourth node; a ninth transistor, including a gate connected to the third node, a first terminal connected to the fourth node, and a second terminal receiving the low gate voltage; and a second capacitor, including a first electrode connected to the fourth node and a second electrode connected to the second node.

[0022] In an embodiment, the level shift output circuit may further include: a tenth transistor, including a gate connected to the third node, a first terminal receiving the second high gate voltage, and a second terminal connected to an output node, at which the output signal is output; an eleventh transistor, including a gate connected to the third node, a first terminal connected to the output node, and a second terminal receiving the low gate voltage; and a third capacitor, including a first electrode connected to the output node and a second electrode connected to the second node.

[0023] In an embodiment, the sixth transistor, the eighth transistor, and the tenth transistor may be PMOS transistors, and the seventh transistor, the ninth transistor, and the eleventh transistor may be NMOS transistors.

[0024] In an embodiment, each of the ninth transistor and the eleventh transistor further includes a bottom gate, and the bottom gate may receive the low gate voltage.

[0025] In an embodiment, the at least one stage may further include: a second transistor connected in series with the first transistor between the first node and the second node, and the first transistor and the second transistor may be different types of transistors.

[0026] In an embodiment, the second low gate voltage of the output signal may be lower than first low gate voltages of the input signal, the clock signal, and the carry signal.

[0027] According to an embodiment, the driver may include a plurality of stages. At least one of the plurality of stages includes: an input circuit configured to transmit an input signal to a first node in response to a clock signal; a first transistor connected between the first node and a second node; a carry circuit configured to output a carry signal having the first high gate voltage when the second node has a first high gate voltage; a level shifter circuit configured to level-shift the first high gate voltage of the second node so that the third node has a second high gate voltage higher than the first high gate voltage; a second transistor connected between the third node and a fourth node and configured to transmit the second high gate voltage of the third node to the fourth node; and a level shift output circuit configured to output an output signal having a third high gate voltage higher than the second high gate voltage by level-shifting the second high gate voltage of the fourth node.

[0028] In an embodiment, the at least one stage may further include: a third transistor connected in series with the first transistor between the first node and the second node; and a fourth transistor connected in series with the second transistor between the third node and the fourth node. The first transistor and the third transistor are transistors of different types, and the second transistor and the fourth transistor are transistors of different types.

[0029] In an embodiment, the second low gate voltage of the third node may be lower than the first low gate voltages of the input signal, the clock signal, and the carry signal, and the third low gate voltage of the output signal may be lower than the second low gate voltage of the third node.

[0030] According to an embodiment, a display device may include: a display panel including a plurality of pixels; a data driver configured to provide a data signal to the plurality of pixels; a gate driver configured to provide a gate signal to the plurality of pixels; an emission driver configured to provide an emission signal to the plurality of pixels; and a controller configured to control the data driver, the gate driver, and the emission driver. At least one of the gate driver and the emission driver may include a plurality of stages. At least one of the plurality of stages may include: an input circuit configured to transmit an input signal to a first node in response to a clock signal; a first transistor connected between the first node and a second node; a carry circuit configured to output a carry signal having the first high gate voltage when the second node has a first high gate voltage; and a level shift output circuit configured to output an output signal having a second high gate voltage higher than the first high gate voltage by level shifting the first high gate voltage of the second node.

[0031] As described above, in the driver and the display device, at least one stage may include a level shift output circuit, and the level shift output circuit may output an output signal having a second high gate voltage higher than the first high gate voltage by level shifting the first high gate voltage of the internal node of the stage. Therefore, the first high gate voltage of the signal applied to the stage and the first high gate voltage of the internal node of the stage may be lower than the second high gate voltage of the output signal, and thus the power consumption of the driver and the display device may be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0033] Figure 1 is a block diagram illustrating an embodiment of a driver.

[0034] Figure 2 Is used to describe Figure 1 A timing diagram of an example of the operation of the driver.

[0035] Figure 3 is a block diagram illustrating stages of a driver according to an embodiment of the present disclosure.

[0036] Figure 4 is a graph showing an example of power consumption of a driver according to a voltage level of a first high gate voltage.

[0037] Figure 5 It is shown that the Figure 3 0 is a cross-sectional view of an example of a PMOS transistor and an NMOS transistor in a stage.

[0038] Figure 6is a circuit diagram showing an embodiment of a stage of a driver.

[0039] Figure 7 Is used to describe Figure 6 A timing diagram of an example of the operation of the stage.

[0040] Figure 8 It is shown that during the first time period Figure 6 A circuit diagram of an example of the operation of the stage.

[0041] Fig. 9 is shown during the initial part of the first time period Figure 6 A diagram of an example of signal voltages at nodes in a stage.

[0042] Fig.10 It is shown that during the second time period Figure 6 A circuit diagram of an example of the operation of the stage.

[0043] Fig.11 is a circuit diagram showing a stage of a driver according to an embodiment.

[0044] Fig.12 is a circuit diagram showing a stage of a driver according to an embodiment.

[0045] Fig.13 is a circuit diagram showing a stage of a driver according to an embodiment.

[0046] Fig.14 is a circuit diagram showing a stage of a driver according to an embodiment.

[0047] Fig.15 is a circuit diagram showing a stage of a driver according to an embodiment.

[0048] Fig.16 is a circuit diagram showing a stage of a driver according to an embodiment.

[0049] Fig.17 is a circuit diagram showing a stage of a driver according to an embodiment.

[0050] Fig.18 is a circuit diagram showing a stage of a driver according to an embodiment.

[0051] Fig.19 is a block diagram illustrating stages of a driver according to an embodiment.

[0052] Fig. 20 is a circuit diagram showing a stage of a driver according to an embodiment.

[0053] Fig.21 is a block diagram illustrating stages of a driver according to an embodiment.

[0054] Fig. 22is a circuit diagram showing a stage of a driver according to an embodiment.

[0055] Fig.23 is a block diagram illustrating stages of a driver according to an embodiment.

[0056] Fig.24 is a circuit diagram showing a stage of a driver according to an embodiment.

[0057] Fig.25 is a block diagram showing a display device according to an embodiment.

[0058] Fig.26 is a block diagram illustrating an electronic device including a display device according to an embodiment. DETAILED DESCRIPTION

[0059] Example embodiments are described more fully hereinafter with reference to the accompanying drawings.The same or similar reference numerals refer to the same or similar elements throughout.

[0060] Figure 1 is a block diagram illustrating an embodiment of a driver, and Figure 2 Is used to describe Figure 1 A timing diagram of an example of the operation of the driver.

[0061] Reference Figure 1 , the driver 100 according to the illustrated embodiment may include a plurality of stages STG1, STG2, STG3, STG4, .... The driver 100 may be implemented in the form of a shift register, wherein the plurality of stages STG1, STG2, STG3, STG4, ... sequentially output output signals OUT1, OUT2, OUT3, OUT4, ... of the driver 100. In some embodiments, the driver 100 may be included in a display device and may be formed in a display panel of the display device. For example, the driver 100 may be integrated or formed on a substrate of a display panel.

[0062] Based on the initial signal FLM, the first clock signal CLK1 and the second clock signal CLK2 input to the driver 100, a plurality of stages STG1, STG2, STG3, STG4, ... can sequentially generate carry signals CR1, CR2, CR3, CR4, ..., and, for example, output signals OUT1, OUT2, OUT3, OUT4, ... can be sequentially output to a plurality of pixels of the display panel. In some embodiments, the first clock signal CLK1 and the second clock signal CLK2 can have the same frequency but different phases. For example, the first clock signal CLK1 and the second clock signal CLK2 can have opposite phases (e.g., 180° inverted). In addition, the first stage STG1 can receive the initial signal FLM as an input signal, and each of the subsequent stages STG2, STG3, STG4, ... can receive the carry signal CR1, CR2, CR3, ... from the previous stage as an input signal. For example, the second stage STG2 may receive the first carry signal CR1 from the first stage STG1 as an input signal, the third stage STG3 may receive the second carry signal CR2 from the second stage STG2 as an input signal, and the fourth stage STG4 may receive the third carry signal CR3 of the third stage STG3 as an input signal.

[0063] In some embodiments, the odd-numbered stages STG1, STG3, ... may respectively output odd-numbered output signals OUT1, OUT3, ... in response to the first clock signal CLK1, and the even-numbered stages STG2, STG4, ... may respectively output even-numbered output signals OUT2, OUT4, ... in response to the second clock signal CLK2. Figure 1 and Figure 2As shown in , when the first clock signal CLK1 is changed to a low level after the initial signal FLM is changed to a high level, the first stage STG1 can generate a first carry signal CR1 and a first output signal OUT1 having a high level. In addition, when the first clock signal CLK1 is changed to a low level after the initial signal FLM is changed to a low level, the first stage STG1 can change the first carry signal CR1 and the first output signal OUT1 to a low level. When the second clock signal CLK2 is changed to a low level after the first carry signal CR1 is changed to a high level, the second stage STG2 can generate a second carry signal CR2 and a second output signal OUT2 having a high level. In addition, when the second clock signal CLK2 is changed to a low level after the first carry signal CR1 is changed to a low level, the second stage STG2 can change the second carry signal CR2 and the second output signal OUT2 to a low level. When the first clock signal CLK1 is changed to a low level after the second carry signal CR2 is changed to a high level, the third stage STG3 can generate a third carry signal CR3 and a third output signal OUT3 having a high level. In addition, when the first clock signal CLK1 is changed to a low level after the second carry signal CR2 is changed to a low level, the third stage STG3 can change the third carry signal CR3 and the third output signal OUT3 to a low level. When the second clock signal CLK2 is changed to a low level after the third carry signal CR3 is changed to a high level, the fourth stage STG4 can generate a fourth carry signal CR4 and a fourth output signal OUT4 with a high level. In addition, when the second clock signal CLK2 is changed to a low level after the third carry signal CR3 is changed to a low level, the fourth stage STG4 can change the fourth carry signal CR4 and the fourth output signal OUT4 to a low level. In this way, a plurality of stages STG1, STG2, STG3, STG4, ... can sequentially output output signals OUT1, OUT2, OUT3, OUT4, ... by delaying or shifting the output signals OUT1, OUT2, OUT3, OUT4, ... by half a cycle of each clock signal CLK1 and CLK2.

[0064] In the driver 100 according to the embodiment, the plurality of stages STG1, STG2, STG3, STG4, ... may output output signals OUT1, OUT2, OUT3, OUT4, ... having a second high gate voltage VGH2 higher than the first high gate voltage VGH1 by level-shifting the first high gate voltage VGH1. Therefore, although the output signals OUT1, OUT2, OUT3, OUT4, ... output from the plurality of stages STG1, STG2, STG3, STG4, ... to the plurality of pixels have the second high gate voltage VGH2 as a high voltage, the signals applied to the plurality of stages STG1, STG2, STG3, STG4, ... (e.g., the first clock signal CLK1, the second clock signal CLK2, the initial signal FLM of the high voltage, and the carry signals CR1, CR2, CR3, CR4, ...) may be the first high gate voltage VGH1 which may be lower than the second high gate voltage VGH2. Therefore, since the driver 100 operates based on the first high gate voltage VGH1 which is lower than the second high gate voltage VGH2 , power consumption of the driver 100 according to the embodiment may be reduced.

[0065] Figure 3 is a block diagram showing the stages of a driver according to an embodiment of the present disclosure, Figure 4 is a diagram showing an example of power consumption of a driver according to a voltage level of a first high gate voltage, and Figure 5 It is shown that the Figure 3 0 is a cross-sectional view of an example of a PMOS transistor and an NMOS transistor in a stage.

[0066] Reference Figure 3 , each stage 200 (e.g., Figure 1 Each of the stages STG1 , STG2 , STG3 , . . . shown in ) may include an input circuit 210 , a first transistor T1 , a carry circuit 230 , and a level shift output circuit 250 .

[0067] The input circuit 210 may transmit the input signal SIN to the first node Q1 in response to the clock signal CLK. In some embodiments, the input circuit 210 of the first stage among the plurality of stages of the driver may receive the initial signal FLM as the input signal SIN, and each of the subsequent stages may receive the carry signal PCR of the previous stage as the input signal SIN. In some embodiments, the clock signal CLK may periodically switch between the low gate voltage VGL and the first high gate voltage VGH1. In addition, in some embodiments, the input circuits 210 of the odd-numbered stages may receive the carry signal PCR of the previous stage. Figure 1 and Figure 2 The first clock signal CLK1 shown in FIG. 2 is used as the clock signal CLK, and the input circuit 210 of the even-numbered stage can receive Figure 1 and Figure 2 The second clock signal CLK2 shown in FIG. 1 is used as the clock signal CLK.

[0068] The first transistor T1 may be connected between the first node Q1 and the second node Q2. The first transistor T1 may be a PMOS transistor having a gate of the first transistor T1 connected to a line for transmitting the low gate voltage VGL, and the first transistor T1 may be referred to as an always-on transistor (AOT). In some embodiments, the first transistor T1 may include a gate for receiving the low gate voltage VGL, a first terminal connected to the first node Q1, and a second terminal connected to the second node Q2.

[0069] The carry circuit 230 may be connected to the second node Q2. When the second node Q2 has the first high gate voltage VGH1, the carry circuit 230 may output a carry signal CR having the first high gate voltage VGH1. The carry signal CR of the carry circuit 230 may be provided to the next stage as an input signal SIN of the next stage.

[0070] The level shift output circuit 250 can output an output signal OUT having a second high gate voltage VGH2 higher than the first high gate voltage VGH1 by level shifting the first high gate voltage VGH1 of the second node Q2. Figure 3 As shown in , the input signal SIN and the clock signal CLK applied to the input circuit 210 and the first node Q1 connected to the input circuit 210 may have a first high gate voltage VGH1 as a high voltage. In addition, the carry signal CR output from the carry circuit 230 and the second node Q2 connected to the carry circuit 230 may have a first high gate voltage VGH1 as a high voltage. However, the output signal OUT output from the level shift output circuit 250 may have a second high gate voltage VGH2 higher than the first high gate voltage VGH1 as a high voltage. Therefore, the high voltage (i.e., the first high gate voltage VGH1) of the signal (e.g., the input signal SIN and the clock signal CLK) applied to the stage 200 and the internal nodes (e.g., the first node Q1 and the second node Q2) of the stage 200 may be lower than the high voltage (i.e., the second high gate voltage VGH2) required for the pixel to which the output signal OUT is applied. Therefore, the power consumption of the driver including the stage 200 can be reduced.

[0071] Reference Figure 4 , also refer to Figure 3 , Figure 4 An example is shown in which the low gate voltage VGL is about -7V and the high voltage or second high gate voltage VGH2 required for the pixel is about 7V. Figure 4In different cases corresponding to different rows shown in , the high voltage VHi of the carry signal CR, the input signal SIN, the clock signal CLK, the first high gate voltage VGH1 of the first node Q1 and the second node Q2 may be about 7V, about 6V, about 5V, about 4V, about 3V or about 2V, but the high voltage VHo of the output signal OUT may be maintained at about 7V. For all cases, the low voltage VLi of the carry signal CR and the low voltage VLo of the output signal OUT may be about -7V. In addition, as Figure 4 As shown in , even if the first high gate voltage VGH1 decreases, the rise time TRi and the fall time TFi of the carry signal CR and the rise time TRo and the fall time TFo of the output signal OUT may not be substantially increased. If the first high gate voltage VGH1 is reduced from about 7V of the second high gate voltage VGH2 to about 6V, about 5V, about 4V, about 3V, and about 2V, the power consumption of the driver caused by the clock signal CLK can be reduced by about 86%, about 73%, about 62%, about 51%, and about 41%, respectively. That is, in the driver according to the embodiment, the signals CR, SIN, and CLK and the nodes Q1 and Q2 can have the first high gate voltage VGH1 as their high voltage VHi, and the first high gate voltage VGH1 is lower than the second high gate voltage VGH2 so that the power consumption of the driver is reduced, while the driver provides its conventional or desired voltage and timing characteristics to the output signal OUT.

[0072] In some embodiments, stage 200 or level shift output circuit 250 may include at least one P-type metal oxide semiconductor (PMOS) transistor and at least one N-type metal oxide semiconductor (NMOS) transistor. In addition, in some embodiments, the first active region of the PMOS transistor and the second active region of the NMOS transistor may be formed of different materials. That is, the first active region of the PMOS transistor may include a material different from the material of the second active region of the NMOS transistor. In addition, in some embodiments, the NMOS transistor may include a gate (e.g., a top gate) located above the second active region and a bottom gate located below the second active region.

[0073] For example, Figure 5As shown in , the first source / drain region SD1, the first active region ACT1, and the second source / drain region SD2 of the PMOS transistor PT may be formed on the substrate SUB of the display panel. In some embodiments, a buffer layer may be further formed between the substrate SUB and the first active region ACT1 to prevent impurities from penetrating into the first active region ACT1, but the embodiment is not limited thereto. The first active region ACT1 of the PMOS transistor PT may include polysilicon (e.g., low temperature polysilicon (LTPS)). In addition, the first source / drain region SD1 and the second source / drain region SD2 may be P+ doped regions and may be used as the source and drain of the PMOS transistor PT, respectively. The first gate insulating layer GI1 may be formed on the first source / drain region SD1, the first active region ACT1, and the second source / drain region SD2. For example, the first gate insulating layer GI1 may include silicon oxide, but is not limited thereto. In addition, the gate GAT1 of the PMOS transistor PT may be formed on the first gate insulating layer (or film) GI1. For example, the gate GAT1 of the PMOS transistor PT may include a metal material such as molybdenum, but is not limited thereto. The second gate insulating layer GI2 may be formed on the gate GAT1 of the PMOS transistor PT. For example, the second gate insulating layer GI2 may include silicon nitride, but is not limited thereto.

[0074] In addition, the bottom gate BML of the NMOS transistor NT may be formed on the second gate insulating layer (or film) GI2. For example, the bottom gate BML may include a metal material such as molybdenum, but is not limited thereto. In some embodiments, the bottom gate BML may be formed as shown in FIG. Fig.15 and Fig.17 The low gate voltage VGL is applied to the bottom gate BML of the NMOS transistor NT as shown in FIG. 1 , or it can be applied as shown in FIG. Fig.12 and Fig.13 As shown in the figure, a bias voltage VBIAS is applied to the bottom gate BML of the NMOS transistor NT. The bias voltage VBIAS applied to the bottom gate BML can be used as a body bias voltage of the NMOS transistor NT, and the threshold voltage of the NMOS transistor NT can be adjusted by adjusting the bias voltage VBIAS. In some embodiments, the bias voltage VBIAS applied to the bottom gate BML can be lower than the low gate voltage VGL, and thus the threshold voltage of the NMOS transistor NT can be increased. In this case, the leakage current flowing through the NMOS transistor NT can be reduced. The first interlayer insulating layer (or film) ILD1 can be formed on the bottom gate BML. For example, the first interlayer insulating layer ILD1 may include silicon oxide or silicon nitride, but is not limited thereto.

[0075] The third source / drain region SD3, the second active region ACT2, and the fourth source / drain region SD4 of the NMOS transistor NT may be formed on the first interlayer insulating layer ILD1. The second active region ACT2 of the NMOS transistor NT may include a material different from that of the first active region ACT1 of the PMOS transistor PT. For example, the second active region ACT2 of the NMOS transistor NT may include an oxide semiconductor, an organic semiconductor, amorphous silicon, or the like. That is, in some embodiments, the first active region ACT1 of the PMOS transistor PT may include polycrystalline silicon, and the second active region ACT2 of the NMOS transistor NT may include an oxide semiconductor (e.g., indium gallium zinc oxide (IGZO) semiconductor). In other embodiments, the first active region ACT1 of the PMOS transistor PT may include polycrystalline silicon, and the second active region ACT2 of the NMOS transistor NT may include an organic semiconductor. In another embodiment, the first active region ACT1 of the PMOS transistor PT may include polycrystalline silicon, and the second active region ACT2 of the NMOS transistor NT may include amorphous silicon. In addition, in some embodiments, as Figure 5 As shown in , the first active region ACT1 of the PMOS transistor PT and the second active region ACT2 of the NMOS transistor NT can be formed in different layers located at different heights from the substrate SUB of the display panel. The third source / drain region SD3 and the fourth source / drain region SD4 can be N+ doped regions and can be used as the source and drain of the NMOS transistor NT, respectively. The third gate insulating layer (or film) GI3 can be formed on the third source / drain region SD3, the second active region ACT2, and the fourth source / drain region SD4. For example, the third gate insulating layer GI3 may include silicon nitride, but is not limited thereto. In addition, the gate GAT2 (for example, the top gate) of the NMOS transistor NT can be formed on the third gate insulating layer GI3. For example, the gate GAT2 of the NMOS transistor NT may include a metal material such as molybdenum or titanium, but is not limited thereto. The second interlayer insulating layer (or film) ILD2 can be formed on the gate GAT2 of the NMOS transistor NT. For example, the second interlayer insulating layer ILD2 may include silicon oxide or silicon nitride, but is not limited thereto.

[0076] The level shift output circuit 250 in each stage 200 may also include a PMOS transistor PT (eg, Figure 6 The gate of the sixth transistor T6 shown in FIG. 1 is connected to the gate of the NMOS transistor NT (eg, Figure 6 At least one capacitor (eg, Figure 6Even if competition is caused by the PMOS transistor PT and the NMOS transistor NT having different mobilities, the capacitor can also connect the node between the PMOS transistor PT and the NMOS transistor NT (for example, Figure 6 The voltage of the third node Q3) shown in FIG. 1 is maintained at a desired voltage.

[0077] Figure 6 is a circuit diagram showing an embodiment of a stage of a driver.

[0078] Reference Figure 6 , each stage 200 of the driver according to the embodiment may include an input circuit 210 , a first transistor T1 , a carry circuit 230 , and a level shift output circuit 250 .

[0079] The input circuit 210 may include a second transistor T2 that transmits the input signal SIN to the first node Q1 in response to the clock signal CLK. Figure 6 In the embodiment of FIG. 5 , the second transistor T2 may include a gate for receiving the clock signal CLK, a first end for receiving the input signal SIN, and a second end connected to the first node Q1.

[0080] The carry circuit 230 may include: a fourth transistor T4, which outputs a first high gate voltage VGH1 as a carry signal CR at a carry node NCR in response to a voltage of a third node Q3; and a fifth transistor T5, which outputs a low gate voltage VGL as a carry signal CR at a carry node NCR in response to a voltage of a second node Q2. In some embodiments, the fourth transistor T4 may include a gate connected to the third node Q3, a first terminal for receiving the first high gate voltage VGH1, and a second terminal connected to the carry node NCR, and the fifth transistor T5 may include a gate connected to the second node Q2, a first terminal connected to the carry node NCR, and a second terminal for receiving the low gate voltage VGL.

[0081] The level shift output circuit 250 may include: a sixth transistor T6, which provides a second high gate voltage VGH2 to the third node Q3 in response to the voltage of the fourth node Q4; a seventh transistor T7, which provides a low gate voltage VGL to the third node Q3 in response to the voltage of the second node Q2; an eighth transistor T8, which provides a second high gate voltage VGH2 to the fourth node Q4 in response to the voltage of the third node Q3; a ninth transistor T9, which provides a low gate voltage VGL to the fourth node Q4 in response to the voltage of the second node Q2; and a second capacitor C2, which is connected between the fourth node Q4 and the second node Q2. In some embodiments, the sixth transistor T6 may include a gate connected to the fourth node Q4, a first terminal for receiving the second high gate voltage VGH2, and a second terminal connected to the third node Q3; the seventh transistor T7 may include a gate connected to the second node Q2, a first terminal connected to the third node Q3, and a second terminal for receiving the low gate voltage VGL; the eighth transistor T8 may include a gate connected to the third node Q3, a first terminal for receiving the second high gate voltage VGH2, and a second terminal connected to the fourth node Q4; the ninth transistor T9 may include a gate connected to the second node Q2, a first terminal connected to the fourth node Q4, and a second terminal for receiving the low gate voltage VGL; and the second capacitor C2 may include a first electrode connected to the fourth node Q4 and a second electrode connected to the second node Q2.

[0082] In some embodiments, the level shift output circuit 250 may further include: a tenth transistor T10, which outputs a second high gate voltage VGH2 as an output signal OUT at an output node NOUT in response to a voltage of the third node Q3; an eleventh transistor T11, which outputs a low gate voltage VGL as an output signal OUT at an output node NOUT in response to a voltage of the second node Q2; and a third capacitor C3 connected between the output node NOUT and the second node Q2. In some embodiments, the tenth transistor T10 may include a gate connected to the third node Q3, a first terminal for receiving the second high gate voltage VGH2, and a second terminal connected to the output node NOUT; the eleventh transistor T11 may include a gate connected to the second node Q2, a first terminal connected to the output node NOUT, and a second terminal for receiving the low gate voltage VGL; and the third capacitor C3 may include a first electrode connected to the output node NOUT and a second electrode connected to the second node Q2.

[0083] In some embodiments, Figure 6As shown in , the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10 and the eleventh transistor T11 may be PMOS transistors, and the seventh transistor T7 may be an NMOS transistor, but the embodiment is not limited thereto.

[0084] Figure 7 Is used to describe Figure 6 A timing diagram of an example of the operation of the stage, Figure 8 It is shown that during the first time period Figure 6 A circuit diagram of an example of the operation of the stage, Fig. 9 is shown during the initial part of the first time period Figure 6 A diagram of an example of a signal voltage at a node in a stage, and Fig.10 It is shown that during the second time period Figure 6 A circuit diagram of an example of the operation of the stage.

[0085] Reference Figure 6 and Figure 7 , based on the clock signal CLK and the input signal SIN, the stage 200 may provide a carry signal CR having a first high gate voltage VGH1 to the next stage, and may provide an output signal OUT having a second high gate voltage VGH2 higher than the first high gate voltage VGH1 to the pixel. In some embodiments, the clock signal CLK may periodically switch between the first high gate voltage VGH1 and the low gate voltage VGL.

[0086] exist Figure 7 In the first time period TP1, after the input signal SIN becomes the first high gate voltage VGH1, the clock signal CLK has the low gate voltage VGL, and as shown in FIG. Figure 8 As shown in , the second transistor T2 may be turned on in response to the clock signal CLK having the low gate voltage VGL, and may transmit the input signal SIN having the first high gate voltage VGH1 to the first node Q1. The first transistor T1 may be turned on in response to the low gate voltage VGL, and may transmit the first high gate voltage VGH1 of the first node Q1 to the second node Q2. The fifth transistor T5, the ninth transistor T9, and the eleventh transistor T11 may be turned off in response to the first high gate voltage VGH1 of the second node Q2.

[0087] The seventh transistor T7 may be turned on in response to the first high gate voltage VGH1 of the second node Q2, and may transmit the low gate voltage VGL to the third node Q3. However, since the fourth node Q4 has the low gate voltage VGL immediately before the first period TP1, if the voltage of the fourth node Q4 is not increased, the sixth transistor T6 may prevent the seventh transistor T7 from reducing the voltage of the third node Q3 to the low gate voltage VGL. In particular, the seventh transistor T7 implemented as an oxide thin film transistor may have a driving capability lower than that of the sixth transistor T6 implemented as an LTPS thin film transistor, and thus the seventh transistor T7 may not be able to reduce the voltage of the third node Q3 to the low gate voltage VGL. However, the level shift output circuit 250 of the stage 200 according to the illustrated embodiment may include a second capacitor C2 connected between the fourth node Q4 and the second node Q2. When the voltage of the second node Q2 increases to the first high gate voltage VGH1, the voltage of the fourth node Q4 may also increase due to the capacitive coupling of the second capacitor C2. Therefore, in the first period TP1, the sixth transistor T6 may be turned off and the voltage of the third node Q3 may be reduced to the low gate voltage VGL. In addition, the eighth transistor T8 may be turned on in response to the low gate voltage VGL of the third node Q3 and may transmit the second high gate voltage VGH2 to the fourth node Q4.

[0088] The fourth transistor T4 may be turned on in response to the low gate voltage VGL of the third node Q3, and may output a carry signal CR having a first high gate voltage VGH1 at the carry node NCR. In addition, the tenth transistor T10 may be turned on in response to the low gate voltage VGL of the third node Q3, and may output an output signal OUT having a second high gate voltage VGH2 at the output node NOUT.

[0089] Fig. 9 1 shows the voltages of the signals CLK, CR and OUT and the nodes Q2, Q3 and Q4 during the initial portion of the first time period TP1. Fig. 9 As shown in , when the clock signal CLK drops to the low gate voltage VGL, the voltage of the second node Q2 may increase to the first high gate voltage VGH1. In addition, when the voltage of the second node Q2 increases, the voltage of the fourth node Q4 may increase due to the capacitive coupling of the second capacitor C2. If the voltage of the second node Q2 and the voltage of the fourth node Q4 increase, the voltage of the third node Q3 may decrease to the low gate voltage VGL. If the voltage of the third node Q3 decreases, the carry signal CR may increase to the first high gate voltage VGH1, and the output signal OUT may increase to the second high gate voltage VGH2 (in the subsequent part of the first time period TP1). Fig. 9 not shown).

[0090] exist Figure 7 During the second time period TP2 shown in FIG. 1 , after the input signal SIN changes from the first high gate voltage VGH1 to the low gate voltage VGL, the clock signal CLK has the low gate voltage VGL. Fig.10 As shown in , the second transistor T2 can then be turned on in response to the clock signal CLK having the low gate voltage VGL, and the input signal SIN having the low gate voltage VGL can be transmitted to the first node Q1. The first transistor T1 can be turned on in response to the low gate voltage VGL, and the low gate voltage VGL of the first node Q1 can be transferred to the second node Q2. The ninth transistor T9 can be turned on in response to the low gate voltage VGL of the second node Q2, and the low gate voltage VGL can be transmitted to the fourth node Q4. Therefore, the voltage of the fourth node Q4 can be reduced from the second high gate voltage VGH2 to the low gate voltage VGL. If the voltage of the fourth node Q4 is reduced, the capacitive coupling of the second capacitor C2 can reduce the voltage of the second node Q2 from the low gate voltage VGL to the boosted low gate voltage BVGL lower than the low gate voltage VGL. For example, when the second high gate voltage VGH2 is about 7V and the low gate voltage VGL is about -7V, the boosted low gate voltage BVGL of the second node Q2 can be about -15V, but the embodiment is not limited thereto. The seventh transistor T7 may be turned off in response to the boosted low gate voltage BVGL of the second node Q2. Since the boosted low gate voltage BVGL of the second node Q2 is lower than the low gate voltage VGL applied to the gate of the first transistor T1, the boosted low gate voltage BVGL of the second node Q2 may not be transmitted to the first node Q1 through the first transistor T1. In addition, the sixth transistor T6 may be turned on in response to the low gate voltage VGL of the fourth node Q4, and may transfer the second high gate voltage VGH2 to the third node Q3. The fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 may be turned off in response to the second high gate voltage VGH2 of the third node Q3.

[0091] The fifth transistor T5 can be turned on in response to the boosted low gate voltage BVGL of the second node Q2, and can output a carry signal CR having a low gate voltage VGL at the carry node NCR. In addition, the eleventh transistor T11 can be turned on in response to the boosted low gate voltage BVGL of the second node Q2, and can output an output signal OUT having a low gate voltage VGL at the output node NOUT. Since the voltage of the output node NOUT is reduced from the second high gate voltage VGH2 to the low gate voltage VGL, the third capacitor C3 can also play an auxiliary role in reducing the voltage of the second node Q2 to the boosted low gate voltage BVGL lower than the low gate voltage VGL.

[0092] Fig.11 is a circuit diagram showing a stage of a driver according to an embodiment.

[0093] Reference Fig.11 In the embodiment of the present invention, each stage 200a of the driver may include an input circuit 210, a first transistor T1, a carry circuit 230a and a level shift output circuit 250. In addition to the carry circuit 230a also including a first capacitor C1, Fig.11 The stage 200a may have Figure 6 The stage 200 has substantially the same configuration and operates substantially the same.

[0094] The carry circuit 230a may include a first capacitor C1 connected between the carry node NCR and the second node Q2. In some embodiments, the first capacitor C1 may include a first electrode connected to the carry node NCR and a second electrode connected to the second node Q2.

[0095] Fig.12 is a circuit diagram showing a stage of a driver according to an embodiment.

[0096] Reference Fig.12 In the embodiment of the present invention, each stage 200b of the driver may include an input circuit 210, a first transistor T1, a carry circuit 230 and a level shift output circuit 250b. In addition to the seventh transistor T7' in the level shift output circuit 250b including a bottom gate BML, Fig.12 The stage 200b may have Figure 6 The stage 200 has substantially the same configuration and operates substantially the same.

[0097] The seventh transistor T7' may include a gate connected to the second node Q2, a first terminal connected to the third node Q3, a second terminal for receiving the low gate voltage VGL, and a bottom gate BML. The bottom gate BML may receive the low gate voltage VGL or a bias voltage VBIAS different from the low gate voltage VGL. The bias voltage VBIAS applied to the bottom gate BML may be used as a body bias voltage of the seventh transistor T7'. Fig.12 In the example of the seventh transistor T7' is an NMOS transistor. The threshold voltage of the seventh transistor T7' can be adjusted by adjusting the bias voltage VBIAS. For example, the bias voltage VBIAS applied to the bottom gate BML can be lower than the low gate voltage VGL, and thus the threshold voltage of the seventh transistor T7' can be increased. In this case, the leakage current through the seventh transistor T7' can be reduced, and the abnormal operation of the seventh transistor T7' can be prevented.

[0098] Fig.13 is a circuit diagram showing a stage of a driver according to an embodiment.

[0099] Reference Fig.13 In the embodiment of the present invention, each stage 200c of the driver may include an input circuit 210c, a first transistor T1, a carry circuit 230 and a level shift output circuit 250c. In addition to the input circuit 210c, the third transistor T3 may also be included. Fig.13 The level 200c can have Fig.12 Stage 200b has substantially the same configuration and substantially the same operation.

[0100] The input circuit 210c may include a second transistor T2 and a third transistor T3. The second transistor T2 transmits the input signal SIN to the first node Q1 in response to the clock signal CLK, and the third transistor T3 transmits the input signal SIN to the first node Q1 in response to the inverted clock signal CLKB. In some embodiments, when the clock signal CLK is Figure 1 and Figure 2 In the case of the first clock signal CLK1 shown in FIG, the inverted clock signal CLKB may be Figure 1 and Figure 2 In some embodiments, the third transistor T3 may include a gate for receiving the inverted clock signal CLKB, a first terminal for receiving the input signal SIN, and a second terminal connected to the first node Q1.

[0101] In addition, if Fig.13 As shown in , the second transistor T2 may be a PMOS transistor, and the third transistor T3 may be an NMOS transistor. That is, the input circuit 210c may be implemented as a CMOS transmission gate including a PMOS transistor and an NMOS transistor connected in parallel.

[0102] In some embodiments, each of the third transistor T3 and the seventh transistor T7 ′ as NMOS transistors may include a gate and a bottom gate. The bottom gate may receive a low gate voltage VGL or a bias voltage VBIAS different from the low gate voltage VGL.

[0103] Fig.14 is a circuit diagram showing a stage of a driver according to an embodiment.

[0104] Reference Fig.14 In the embodiment of the present invention, each stage 200d of the driver may include an input circuit 210, a first transistor T1, a carry circuit 230, and a level shift output circuit 250d. In addition to the level shift output circuit 250d including a ninth transistor T9', the ninth transistor T9' is implemented as an NMOS transistor and replaces the ninth transistor T9 described above. Fig.14 The level 200d can have Figure 6The stage 200 has substantially the same configuration and operates substantially the same.

[0105] The ninth transistor T9' may be an NMOS transistor and may operate in response to the voltage of the third node Q3. In some embodiments, the ninth transistor T9' may include a gate connected to the third node Q3, a first terminal connected to the fourth node Q4, and a second terminal for receiving the low gate voltage VGL.

[0106] Fig.15 is a circuit diagram showing a stage of a driver according to an embodiment.

[0107] Reference Fig.15 In the embodiment of the present invention, each stage 200e of the driver may include an input circuit 210, a first transistor T1, a carry circuit 230 and a level shift output circuit 250e. In addition, the eleventh transistor T11' is also implemented as an NMOS transistor and replaces the above-mentioned eleventh transistor T11. Fig.15 The Level 200e can have Fig.14 The stage 200d has substantially the same configuration and substantially the same operation.

[0108] The eleventh transistor T11' may be an NMOS transistor and may operate in response to the voltage of the third node Q3. In some embodiments, the eleventh transistor T11' may include a gate connected to the third node Q3, a first terminal connected to the output node NOUT, and a second terminal for receiving the low gate voltage VGL.

[0109] In some embodiments, Fig.15 As shown in FIG. 1 , each of the ninth transistor T9 ′ and the eleventh transistor T11 ′ may include a bottom gate. The bottom gate of each of the ninth transistor T9 ′ and the eleventh transistor T11 ′ may be as shown in FIG. Fig.15 Receives the low gate voltage VGL as shown in . Alternatively, the bottom gate of each of the ninth transistor T9 ′ and the eleventh transistor T11 ′ may receive a bias voltage different from the low gate voltage VGL.

[0110] Fig.16 is a circuit diagram showing a stage of a driver according to an embodiment.

[0111] Reference Fig.16 In the embodiment of the present invention, each stage 200f of the driver may include an input circuit 210, a first transistor T1, a carry circuit 230, and a level shift output circuit 250f. In addition, the level shift output circuit 250f does not include Figure 6 In addition to the tenth transistor T10, the eleventh transistor T11 and the third capacitor C3 shown in FIG. Fig.16 The level 200f can have Figure 6 The stage 200 has substantially the same configuration and operates substantially the same.

[0112] exist Fig.16 In the stage 200f, the fourth node Q4 may be an output node NOUT at which the output signal OUT is output, and the voltage of the fourth node Q4 may be provided to the pixel as the output signal OUT. Figure 7 As shown in , the voltage of the fourth node Q4 may have substantially the same waveform as that of the output signal OUT, and thus the voltage of the fourth node Q4 may serve as the output signal OUT.

[0113] Fig.17 is a circuit diagram showing a stage of a driver according to an embodiment.

[0114] Reference Fig.17 In the embodiment of the present invention, each stage 200g of the driver may include an input circuit 210, a first transistor T1, a carry circuit 230, and a level shift output circuit 250g. In addition to the ninth transistor T9' in the level shift output circuit 250g being implemented as an NMOS transistor, Fig.17 The level 200g can have Fig.16 The ninth transistor T9' may be an NMOS transistor and may operate in response to the voltage of the third node Q3. In some embodiments, the ninth transistor T9' may include a bottom gate that receives a low gate voltage VGL or a bias voltage.

[0115] Fig.18 is a circuit diagram showing a stage of a driver according to an embodiment.

[0116] Reference Fig.18 In the embodiment of the present invention, each stage 200h of the driver may include an input circuit 210, a first transistor T1, a carry circuit 230, a level shift output circuit 250, and a seventeenth transistor T17. In addition to the seventeenth transistor T17 connected in series with the first transistor T1 between the first node Q1 and the second node Q2, the stage 200h may also include a first transistor T17 connected in series with the first transistor T1. Fig.18 The level 200h can have Figure 6 The stage 200 has substantially the same configuration and operates substantially the same.

[0117] The first transistor T1 may be referred to as a first AOT transistor T1, the seventeenth transistor T17 may be referred to as a second AOT transistor T17, and the first AOT transistor T1 and the second AOT transistor T17 may be transistors of different types. Fig.18As shown in , the first AOT transistor T1 may be a PMOS transistor, and the second AOT transistor T17 may be an NMOS transistor. In addition, for example, the first AOT transistor T1 may include a gate for receiving a low gate voltage VGL, a first terminal connected to the second AOT transistor T17, and a second terminal connected to the second node Q2, and the second AOT transistor T17 may include a gate for receiving a first high gate voltage VGH1, a first terminal connected to the first node Q1, and a second terminal connected to the first AOT transistor T1.

[0118] Fig.19 is a block diagram illustrating stages of a driver according to an embodiment.

[0119] Reference Fig.19 In the embodiment of the present invention, each stage 1200 of the driver may include an input circuit 1210, a first transistor T1 (or a first AOT transistor T1), a carry circuit 1230, a level shifter circuit 1270, a twelfth transistor T12 (or a second AOT transistor T12), and a level shift output circuit 1250. In addition to the level shifter circuit 1270 and the second AOT transistor T12 between the second node Q2 and the level shift output circuit 1250, Fig.19 The level 1200 can have Figure 3 The stage 200 is similarly configured and operates similarly.

[0120] The input circuit 1210 may transmit an input signal SIN to a first node Q1 in response to a clock signal CLK. The first AOT transistor T1 may be connected between the first node Q1 and a second node Q2. When the second node Q2 has a first high gate voltage VGH1', the carry circuit 1230 may output a carry signal CR having the first high gate voltage VGH1'.

[0121] The level shifter circuit 1270 may level-shift the first high gate voltage VGH1 ′ of the second node Q2 so that the third node Q3 ′ may have a second high gate voltage VGH2 ′ higher than the first high gate voltage VGH1 ′.

[0122] The second AOT transistor T12 may be connected between the third node Q3' and the fourth node Q4'. The gate of the second AOT transistor T12 may be connected to a line for transmitting the low gate voltage VGL. The second AOT transistor T12 may transmit the second high gate voltage VGH2' of the third node Q3' to the fourth node Q4'. In some embodiments, the second AOT transistor T12 may include a gate for receiving the low gate voltage VGL, a first terminal connected to the third node Q3', and a second terminal connected to the fourth node Q4'.

[0123] The level shift output circuit 1250 may output an output signal OUT having a third high gate voltage VGH3 higher than the second high gate voltage VGH2 ′ by level-shifting the second high gate voltage VGH2 ′ of the fourth node Q4 ′.

[0124] exist Fig.19 In the embodiment of the present invention, the input signal SIN, the clock signal CLK, the carry signal CR, the first node Q1 and the second node Q2 may have the first high gate voltage VGH1' as a high voltage. The level shifter circuit 1270 may cause the third node Q3' and the fourth node Q4' to have the second high gate voltage VGH2', which is higher than the first high gate voltage VGH1', as a high voltage. In addition, the level shift output circuit 1250 may cause the output signal OUT to have the third high gate voltage VGH3, which is higher than the second high gate voltage VGH2', as a high voltage. That is, the second high gate voltage VGH2' may be lower than the third high gate voltage VGH3, and the first high gate voltage VGH1' may be lower than the second high gate voltage VGH2'. Therefore, the first high gate voltage VGH1' of the input signal SIN and the clock signal CLK applied to the stage 1200 may be lower than the third high gate voltage VGH3 required for the pixel to which the output signal OUT is applied, and thus the power consumption of the driver including the stage 1200 may be reduced. In addition, the use of the level shifter circuit 1270 may make Fig.19 The first high gate voltage VGH1' of stage 1200 is lower than Figure 3 The first high gate voltage VGH1 of the stage 200 is reduced, and thus the power consumption of the driver including the stage 1200 can be further reduced.

[0125] Fig. 20 is a circuit diagram showing a stage of a driver according to an embodiment.

[0126] Reference Fig. 20 In the embodiment of the present invention, each stage 1200 of the driver may include an input circuit 1210, a first AOT transistor T1, a carry circuit 1230, a level shifter circuit 1270, a second AOT transistor T12, and a level shift output circuit 1250. In addition to the level shifter circuit 1270 and the second AOT transistor T12 between the second node Q2 and the level shift output circuit 1250, the stage 1200 may also include the level shifter circuit 1270 and the second AOT transistor T12 between the second node Q2 and the level shift output circuit 1250. Fig. 20 The level 1200 can have Figure 6 The stage 200 is similarly configured and operates similarly.

[0127] The level shifter circuit 1270 may include a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, and a fourth capacitor C4. The thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, the sixteenth transistor T16, and the fourth capacitor C4 may respectively operate in the same manner as the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the second capacitor C2 operate to perform level shifting as described above. For example, the thirteenth transistor T13 and the fourteenth transistor T14 may be connected in series between a line for transmitting the second high gate voltage VGH2' and a line for transmitting the low gate voltage VGL, and the fifteenth transistor T15 and the sixteenth transistor T16 may be connected in series between a line for transmitting the second high gate voltage VGH2' and a line for transmitting the low gate voltage VGL, and the fourth capacitor C4 may be connected between the second node Q2 and the third node Q3'.

[0128] Fig.21 is a block diagram showing stages of a driver according to an embodiment, and Fig. 22 is a circuit diagram showing a stage of a driver according to an embodiment.

[0129] Reference Fig.21 and 22 In the embodiment of the present invention, each stage 1300 of the driver may include an input circuit 1310, a first transistor T1 (or a first AOT transistor T1), a seventeenth transistor T17 (or a second AOT transistor T17), a carry circuit 1330, and a level shift output circuit 1350. In addition to the stage 1300 further including a second AOT transistor T17 connected in series with the first AOT transistor T1 between the first node Q1' and the second node Q2', Fig.21 and Fig. 22 The level 1300 may have Figure 3 and Figure 6 The stage 200 is similarly configured and operates similarly.

[0130] The first AOT transistor T1 and the second AOT transistor T17 may be connected in series between the first node Q1' and the second node Q2' and may be transistors of different types. Fig.21 and Fig. 22As shown in , the first AOT transistor T1 can be a PMOS transistor, and the second AOT transistor T17 can be an NMOS transistor. In addition, the gate of the first AOT transistor T1 can receive the second low gate voltage VGL2, and the gate of the second AOT transistor T17 can receive the first high gate voltage VGH1. Even if the low voltage of the second node Q2' is boosted, the first AOT transistor T1 can prevent the boosted low voltage of the second node Q2' from being transmitted to the first node Q1'. In addition, even if the high voltage of the second node Q2' is boosted, the second AOT transistor T17 can prevent the boosted high voltage of the second node Q2' from being transmitted to the first node Q1'.

[0131] In each stage 1300 of the driver according to the embodiment, the input signal SIN, the clock signal CLK, and the carry signal CR may have a first high gate voltage VGH1 as a high voltage and a first low gate voltage VGL1 as a low voltage. In addition, the level shift output circuit 1350 may cause the output signal OUT to have a second high gate voltage VGH2 higher than the first high gate voltage VGH1 as a high voltage, and a second low gate voltage VGL2 lower than the first low gate voltage VGL1 as a low voltage. That is, the first high gate voltage VGH1 of the input signal SIN and the clock signal CLK applied to the stage 1300 may be lower than the second high gate voltage VGH2 required for the pixel to which the output signal OUT is applied, and the first low gate voltage VGL1 of the input signal SIN and the clock signal CLK applied to the stage 1300 may be higher than (or not negative than) the second low gate voltage VGL2 required for the pixel to which the output signal OUT is applied. Therefore, the power consumption of the driver including the stage 1300 may be further reduced.

[0132] Fig.23 is a block diagram showing stages of a driver according to an embodiment, and Fig.24 is a circuit diagram showing a stage of a driver according to an embodiment.

[0133] Reference Fig.23 and Fig.24In the embodiment of the present invention, each stage 1400 of the driver may include an input circuit 1410, a first transistor T1 (or a first AOT transistor T1), a seventeenth transistor T17 (or a third AOT transistor T17), a carry circuit 1430, a level shifter circuit 1470, a twelfth transistor T12 (or a second AOT transistor T12), an eighteenth transistor T18 (or a fourth AOT transistor T18), and a level shift output circuit 1450. In addition to the stage 1400 further including a third AOT transistor T17 connected in series with the first AOT transistor T1 between the first node Q1' and the second node Q2' and a fourth AOT transistor T18 connected in series with the second AOT transistor T12 between the third node Q3" and the fourth node Q4", Fig.23 and Fig.24 The level 1400 may have Fig.19 and Fig. 20 The stage 1200 is similarly configured and operates similarly.

[0134] The first AOT transistor T1 and the third AOT transistor T17 may be connected in series between the first node Q1' and the second node Q2', and may be transistors of different types. In addition, the second AOT transistor T12 and the fourth AOT transistor T18 may be connected in series between the third node Q3' and the fourth node Q4', and may be transistors of different types. For example, Fig.23 and Fig.24 As shown in , the first AOT transistor T1 may be a PMOS transistor, and the third AOT transistor T17 may be an NMOS transistor. The gate of the first AOT transistor T1 may receive the second low gate voltage VGL2', and the gate of the third AOT transistor T17 may receive the first high gate voltage VGH1'. In addition, the second AOT transistor T12 may be a PMOS transistor, and the fourth AOT transistor T18 may be an NMOS transistor. The gate of the second AOT transistor T12 may receive the third low gate voltage VGL3, and the gate of the fourth AOT transistor T18 may receive the second high gate voltage VGH2'.

[0135] In each stage 1400 of the driver according to another embodiment of the present invention, the input signal SIN, the clock signal CLK, and the carry signal CR may have a first high gate voltage VGH1' as a high voltage and have a first low gate voltage VGL1' as a low voltage. In addition, the level shifter circuit 1470 may cause the third node Q3" to have a second high gate voltage VGH2' higher than the first high gate voltage VGH1' as a high voltage and a second low gate voltage VGL2' lower than the first low gate voltage VGL1' as a low voltage. In addition, the level shift output circuit 1450 may cause the output signal OUT to have a third high gate voltage VGH3 higher than the second high gate voltage VGH2' as a high voltage and a third low gate voltage VGL3 lower than the second low gate voltage VGL2' as a low voltage. Therefore, the power consumption of the driver including the stage 1400 may be further reduced.

[0136] Although not in Fig.23 and Fig.24 As shown in the figure, each stage 1400 can output the voltage of the third node Q3" as an additional output signal having a voltage level different from the voltage level of the output signal OUT. In this case, each stage 1400 can also include a buffer that outputs the voltage of the third node Q3".

[0137] Fig.25 is a block diagram showing a display device according to an embodiment.

[0138] Reference Fig.25 The display device 2000 may include: a display panel 2010, including a plurality of pixels PX; a data driver 2030, providing a data signal DS to the plurality of pixels PX; a gate driver 2050, providing a gate signal GS to the plurality of pixels PX; an emission driver 2070, providing an emission signal EM to the plurality of pixels PX; and a controller 2090, controlling the data driver 2030, the gate driver 2050 and the emission driver 2070.

[0139] The display panel 2010 may include data lines, gate lines, emission lines, and a plurality of pixels PX connected to the data lines, gate lines, and emission lines. In some embodiments, each pixel PX may include a light-emitting element, and the display panel 2010 may be a light-emitting display panel. In some embodiments, the light-emitting element may be an organic light-emitting diode (OLED). In other embodiments, the light-emitting element may be a nano light-emitting diode (NED), a quantum dot (QD) light-emitting diode, a micro light-emitting diode, an inorganic light-emitting diode, or any other suitable light-emitting element. In other embodiments, the display panel 2010 may be a liquid crystal display (LCD) panel or any other suitable display panel.

[0140] The data driver 2030 may generate a data signal DS based on a data control signal DCTRL and output image data ODAT received from the controller 2090, and the data driver 2030 may provide the data signal DS to a plurality of pixels PX through a data line. In some embodiments, the data control signal DCTRL may include, but is not limited to, an output data enable signal, a horizontal initial signal, and a load signal. In some embodiments, the data driver 2030 and the controller 2090 may be implemented as a single integrated circuit, and the single integrated circuit may be referred to as a timing controller embedded data driver (TED) integrated circuit. In other embodiments, the data driver 2030 and the controller 2090 may be implemented as separate integrated circuits.

[0141] The gate driver 2050 may generate a gate signal GS based on a gate control signal GCTRL received from the controller 2090, and the gate driver 2050 may sequentially provide the gate signal GS to a plurality of pixels PX through the gate lines row by row. In some embodiments, the gate signal GS applied to each pixel PX may include, but is not limited to, a compensation signal, a write signal, and / or an initialization signal. In some embodiments, the gate control signal GCTRL may include, but is not limited to, a gate initialization signal and a gate clock signal. In some embodiments, the gate driver 2050 may include a plurality of stages, and each stage may be Figure 3 and Figure 6 Level 200, Fig.11 Level 200a, Fig.12 Level 200b, Fig.13 Level 200c, Fig.14 Level 200d, Fig.15 Level 200e, Fig.16 Level 200f, Fig.17 200g Fig.18 Level 200h, Fig.19 and Fig. 20 Level 1200, Fig.21 and Fig. 22 Level 1300 or Fig.23 and Fig.24 In addition, in some embodiments, as Fig.25 As shown in , the gate driver 2050 may be integrated or formed in the display panel 2010. In other embodiments, the gate driver 2050 may be implemented as one or more integrated circuits.

[0142] The emission driver 2070 may generate an emission signal EM based on an emission control signal ECTRL received from the controller 2090, and the emission driver 2070 may sequentially provide the emission signal EM to a plurality of pixels PX through the emission lines row by row. In some embodiments, the emission control signal ECTRL may include, but is not limited to, an emission start signal and an emission clock signal. In some embodiments, the emission driver 2070 may include a plurality of stages, and each stage may be Figure 3 and Figure 6 Level 200, Fig.11 Level 200a, Fig.12 Level 200b, Fig.13 Level 200c, Fig.14 Level 200d, Fig.15 Level 200e, Fig.16 Level 200f, Fig.17 200g Fig.18 Level 200h, Fig.19 and Fig. 20 Level 1200, Fig.21 and Fig. 22 Level 1300 or Fig.23 and Fig.24 In addition, in some embodiments, as Fig.25 As shown in , the emission driver 2070 may be integrated or formed in the display panel 2010. In other embodiments, the emission driver 2070 may be implemented as one or more integrated circuits.

[0143] The controller 2090 (e.g., a timing controller (TCON)) may receive input image data IDAT and a control signal CTRL from an external host processor (e.g., a graphics processing unit (GPU), an application processor (AP), or a graphics card). In some embodiments, the input image data IDAT may be RGB image data including red image data, green image data, and blue image data. In some embodiments, the control signal CTRL may include, but is not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a main clock signal, etc. The controller 2090 may generate output image data ODAT, a data control signal DCTRL, a gate control signal GCTRL, and an emission control signal ECTRL based on the input image data IDAT and the control signal CTRL. The controller 2090 may control the operation of the data driver 2030 by providing the output image data ODAT and the data control signal DCTRL to the data driver 2030, may control the operation of the gate driver 2050 by providing the gate control signal GCTRL to the gate driver 2050, and may control the operation of the emission driver 2070 by providing the emission control signal ECTRL to the emission driver 2070.

[0144] In the display device 2000 according to the illustrated embodiment, at least one of the gate driver 2050 and the emission driver 2070 may be implemented as Figure 1 The driver 100 of the present invention. At least one stage of the driver may include a level shift output circuit, and the level shift output circuit may output an output signal having a second high gate voltage higher than the first high gate voltage by level shifting the first high gate voltage of the internal node of the stage. Therefore, the first high gate voltage of the signal applied to the stage and the first high gate voltage of the internal node of the stage may be lower than the second high gate voltage of the output signal, and thus the power consumption of the driver and the display device 2000 may be reduced.

[0145] Fig.26 is a block diagram illustrating an electronic device including a display device according to an embodiment.

[0146] Reference Fig.26 , the electronic device 2100 may include a processor 2110, a memory device 2120, a storage device 2130, an input / output (I / O) device 2140, a power supply 2150, and a display device 2160. The electronic device 2100 may also include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, and the like.

[0147] The processor 2110 may perform various computing functions or tasks. The processor 2110 may be an application processor (AP), a microprocessor, a central processing unit (CPU), etc. The processor 2110 may be connected to other components via an address bus, a control bus, a data bus, etc. In addition, in some embodiments, the processor 2110 may be further connected to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0148] The memory device 2120 may store data used for the operation of the electronic device 2100. For example, the memory device 2120 may include at least one nonvolatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc. and / or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile dynamic random access memory (mobile DRAM) device, etc.

[0149] The storage device 2130 may be a solid state drive (SSD) device, a hard disk drive (HDD) device, a compact disk read only memory (CD-ROM) device, etc. The I / O device 2140 may be an input device such as a keyboard, a keypad, a mouse, a touch screen, etc. and an output device such as a printer, a speaker, etc. The power supply 2150 may be used to supply power for the operation of the electronic device 2100. The display device 2160 may be connected to other components via a bus or other communication links.

[0150] In the display device 2160, at least one stage of the driver may include a level shift output circuit, and the level shift output circuit may output an output signal having a second high gate voltage higher than the first high gate voltage by level shifting the first high gate voltage of the internal node of the stage. Therefore, the first high gate voltage of the signal applied to the stage and the first high gate voltage of the internal node of the stage may be lower than the second high gate voltage of the output signal, and thus the power consumption of the driver and the display device 2160 may be reduced.

[0151] The concepts disclosed herein may be applied to any display device 2160 and any electronic device 2100 including the display device 2160. For example, the concepts disclosed herein may be applied to smart phones, wearable electronic devices, mobile phones, televisions (TVs) such as digital TVs, three-dimensional (3D) TVs, personal computers (PCs) such as tablet computers, laptop computers, home appliances, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, music players, portable game consoles, navigation devices, and the like.

[0152] The foregoing is an illustration of some specific embodiments and should not be construed as limiting the embodiments. Although some embodiments have been described, it will be readily appreciated by those skilled in the art that many modifications may be made in the embodiments without substantially departing from the novel teachings and advantages of the present disclosure. Therefore, all of these modifications are intended to be included within the scope defined in the claims. Therefore, it will be understood that the foregoing is an illustration of various embodiments and should not be construed as being limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims.

Claims

1. A drive, wherein: The driver comprises a plurality of stages, at least one of the plurality of stages comprising: an input circuit configured to transmit an input signal to the first node in response to a clock signal; a first transistor connected between the first node and a second node; a carry circuit configured to output a carry signal having the first high gate voltage when the second node has the first high gate voltage; and A level shift output circuit is configured to output an output signal having a second high gate voltage higher than the first high gate voltage by level shifting the first high gate voltage of the second node.

2. The driver according to claim 1, wherein: The clock signal switches between a low gate voltage and the first high gate voltage.

3. The driver according to claim 1, wherein: The level shift output circuit includes at least one P-type metal oxide semiconductor transistor and at least one N-type metal oxide semiconductor transistor, and The first active region of the P-type metal oxide semiconductor transistor includes a material different from a material of the second active region of the N-type metal oxide semiconductor transistor.

4. The driver according to claim 3, wherein: The level shift output circuit further includes at least one capacitor connected between a gate of the P-type metal oxide semiconductor transistor and a gate of the N-type metal oxide semiconductor transistor.

5. The driver according to claim 1, wherein: The first transistor includes a gate receiving a low gate voltage, a first terminal connected to the first node, and a second terminal connected to the second node.

6. The driver according to claim 1, wherein: The input circuit comprises: The second transistor includes a gate receiving the clock signal, a first terminal receiving the input signal, and a second terminal connected to the first node.

7. The driver according to claim 6, wherein: The input circuit further comprises: a third transistor including a gate receiving an inverted clock signal, a first terminal receiving the input signal, and a second terminal connected to the first node, Wherein, the second transistor is a P-type metal oxide semiconductor transistor, and wherein, the third transistor is an N-type metal oxide semiconductor transistor.

8. The driver according to claim 1, wherein: The carry circuit comprises: a fourth transistor including a gate connected to a third node, a first terminal receiving the first high gate voltage, and a second terminal connected to a carry node at which the carry signal is output; and A fifth transistor includes a gate connected to the second node, a first terminal connected to the carry node, and a second terminal receiving a low gate voltage.

9. The driver according to claim 8, wherein: The carry circuit also includes: A first capacitor includes a first electrode connected to the carry node and a second electrode connected to the second node.

10. The driver according to claim 1, wherein: The level shift output circuit comprises: a sixth transistor including a gate connected to a fourth node, a first terminal receiving the second high gate voltage, and a second terminal connected to a third node; a seventh transistor including a gate connected to the second node, a first terminal connected to the third node, and a second terminal receiving a low gate voltage; an eighth transistor including a gate connected to the third node, a first terminal receiving the second high gate voltage, and a second terminal connected to the fourth node; a ninth transistor including a gate connected to the second node, a first terminal connected to the fourth node, and a second terminal receiving the low gate voltage; and The second capacitor includes a first electrode connected to the fourth node and a second electrode connected to the second node.

11. The driver according to claim 10, wherein: The sixth transistor, the eighth transistor and the ninth transistor are P-type metal oxide semiconductor transistors, Wherein, the seventh transistor is an N-type metal oxide semiconductor transistor, Wherein, the seventh transistor further includes a bottom gate, and Wherein, the bottom gate receives a bias voltage.

12. The driver according to claim 11, wherein: The fourth node is an output node at which the output signal is output.

13. The driver according to claim 11, wherein: The level shift output circuit further includes: a tenth transistor including a gate connected to the third node, a first terminal receiving the second high gate voltage, and a second terminal connected to an output node at which the output signal is output; an eleventh transistor including a gate connected to the second node, a first terminal connected to the output node, and a second terminal receiving the low gate voltage; and A third capacitor includes a first electrode connected to the output node and a second electrode connected to the second node.

14. The driver according to claim 1, wherein: The level shift output circuit comprises: a sixth transistor including a gate connected to a fourth node, a first terminal receiving the second high gate voltage, and a second terminal connected to a third node; a seventh transistor including a gate connected to the second node, a first terminal connected to the third node, and a second terminal receiving a low gate voltage; an eighth transistor including a gate connected to the third node, a first terminal receiving the second high gate voltage, and a second terminal connected to the fourth node; a ninth transistor including a gate connected to the third node, a first terminal connected to the fourth node, and a second terminal receiving the low gate voltage; and The second capacitor includes a first electrode connected to the fourth node and a second electrode connected to the second node.

15. The driver according to claim 14, wherein: The level shift output circuit further includes: a tenth transistor including a gate connected to the third node, a first terminal receiving the second high gate voltage, and a second terminal connected to an output node at which the output signal is output; an eleventh transistor including a gate connected to the third node, a first terminal connected to the output node, and a second terminal receiving the low gate voltage; and A third capacitor includes a first electrode connected to the output node and a second electrode connected to the second node.

16. The driver according to claim 15, wherein: The sixth transistor, the eighth transistor and the tenth transistor are P-type metal oxide semiconductor transistors, The seventh transistor, the ninth transistor and the eleventh transistor are N-type metal oxide semiconductor transistors. wherein each of the ninth transistor and the eleventh transistor further comprises a bottom gate, and The bottom gate receives the low gate voltage.

17. The driver according to claim 1, wherein: The at least one stage further comprises: a second transistor connected in series with the first transistor between the first node and the second node, wherein the first transistor and the second transistor are transistors of different types, and The second low gate voltage of the output signal is lower than the first low gate voltages of the input signal, the clock signal and the carry signal.

18. A drive, wherein: The driver comprises a plurality of stages, at least one of the plurality of stages comprising: an input circuit configured to transmit an input signal to the first node in response to a clock signal; a first transistor connected between the first node and a second node; a carry circuit configured to output a carry signal having the first high gate voltage when the second node has the first high gate voltage; a level shifter circuit configured to level-shift the first high gate voltage of the second node so that a third node has a second high gate voltage higher than the first high gate voltage; a second transistor connected between the third node and a fourth node and configured to transmit the second high gate voltage of the third node to the fourth node; and A level shift output circuit is configured to output an output signal having a third high gate voltage higher than the second high gate voltage by level shifting the second high gate voltage of the fourth node.

19. The driver according to claim 18, wherein: The at least one stage further comprises: a third transistor connected in series with the first transistor between the first node and the second node; and a fourth transistor connected in series with the second transistor between the third node and the fourth node, wherein the first transistor and the third transistor are transistors of different types, wherein the second transistor and the fourth transistor are transistors of different types, wherein the second low gate voltage of the third node is lower than the first low gate voltages of the input signal, the clock signal and the carry signal, and The third low gate voltage of the output signal is lower than the second low gate voltage of the third node.

20. A display device, wherein: The display device comprises: A display panel including a plurality of pixels; a data driver configured to provide data signals to the plurality of pixels; a gate driver configured to provide gate signals to the plurality of pixels; an emission driver configured to provide emission signals to the plurality of pixels; and a controller configured to control the data driver, the gate driver, and the emission driver, wherein at least one of the gate driver and the emission driver comprises a plurality of stages, and Wherein, at least one of the multiple levels comprises: an input circuit configured to transmit an input signal to the first node in response to a clock signal; a first transistor connected between the first node and a second node; a carry circuit configured to output a carry signal having the first high gate voltage when the second node has the first high gate voltage; and A level shift output circuit is configured to output an output signal having a second high gate voltage higher than the first high gate voltage by level shifting the first high gate voltage of the second node.

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