Semiconductor device preparation method and semiconductor device

Abstract

The invention provides a semiconductor device preparation method and a semiconductor device, and relates to the technical field of semiconductor device preparation, and the semiconductor device preparation method comprises the steps: S10, providing a GaAs substrate; s20, the first surface of the GaAs substrate is corroded through first treatment liquid, the first treatment liquid is H3PO4: H2O2: H2O = 1: 1: 138-2: 1: 50, and a concave-convex structure is formed on the first surface; and S30, forming a SiNx layer covering the concave-convex structure on the first surface.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor device preparation, and in particular to a semiconductor device preparation method and a semiconductor device. Background Art

[0002] The high-power edge-emitting chip includes a GaAs substrate, SiN x An insulating layer and an ohmic contact layer, wherein the ohmic contact layer is further divided into a first metal layer, a thick gold layer and a second metal layer, wherein the first metal layer and the second metal layer are both metal layers, and the thick gold layer is a thick gold layer.

[0003] In the prior art, when preparing high-power edge-emitting chips, after the thick gold layer and the second metal layer are peeled off, the gold layer at the edge is lost, that is, the ohmic contact gold layer and the insulating SiN layer below are x The layers fell off together, and after the post-cleavage, some bars also had gold falling problems during the adhesion test (the same SiN x fall off together). Summary of the invention

[0004] The object of the present invention is to provide a method for preparing a semiconductor device and a semiconductor device, which can alleviate the problem of SiN x The problem of layers falling off easily.

[0005] In a first aspect, the present invention provides a method for preparing a semiconductor device, comprising the steps of: S10. Providing a GaAs substrate; S20. Etching the first surface of the GaAs substrate using a first treatment liquid, wherein the first treatment liquid is H 3 PO 4 :H 2 O 2 :H 2 O=1:1:138-2:1:50, so that the first surface forms a concavo-convex structure; S30. Forming SiN covering the concave-convex structure on the first surface x layer.

[0006] Furthermore, the time t for corroding the first surface in step S20 ranges from 15s to 20s.

[0007] Furthermore, in the step S20, the maximum height difference of the concave-convex structure ranges from 8 nm to 10 nm.

[0008] Furthermore, the method further includes the following steps performed after step S30: S41. Forming a first metal layer of an ohmic contact layer on the first surface, wherein the first metal layer covers a portion of the SiN x layer; The following steps are also included after step S20: Step S21. Form a pit in the first region of the first surface, wherein the SiN x The SiN layer covers the first region, wherein the SiN x The area formed by the projection of the area in the layer not covered by the first metal layer onto the first surface of the GaAs substrate is the first area; Along the depth direction of the pit, there is at least one position in the pit where the cross-sectional area is larger than the opening area of ​​the pit.

[0009] Furthermore, the step S21 specifically includes the steps of: S211. Forming a mask having an opening at a first region of a first surface of a GaAs substrate; S212. Etching the first region through the opening using the first processing liquid to form a pit.

[0010] Furthermore, the ratio of the width L of the opening of the pit to the depth H of the pit is L:H>5:1, and L:H<12:1.

[0011] Furthermore, the method further includes the following steps performed after step S30: S41. Forming a first metal layer of an ohmic contact layer on the first surface, wherein the first metal layer covers a portion of the SiN x layer; S42. Forming a photoresist layer on the first metal layer, wherein windows are formed on the photoresist layer extending through the upper and lower surfaces thereof; S43. Forming a thick gold layer, a portion of the thick gold layer covers the photoresist layer, and another portion is located within the window; S43. Forming a second metal layer on the thick gold layer; S44. Remove the photoresist layer so that part of the thick gold layer and part of the second metal layer above the photoresist layer are uniformly stripped, and the projections of the thick gold layer and the second metal layer toward the GaAs substrate are both located on the SiN x Outside the layer.

[0012] Furthermore, the step S30 includes the steps of: S31. Obtaining a warping direction of the first surface of the GaAs substrate; S32. When the first surface of the GaAs substrate faces the SiN x When one side of the layer is warped, a low-frequency SiN xSingle layer; When the first surface of the GaAs substrate faces away from the SiN x When one side of the layer is warped, the layer in contact with the first surface of the GaAs substrate is a high-frequency SiN x Single layer; The low frequency SiN x The single layer is subjected to compressive stress, the high frequency SiN x The single layer is subjected to tensile stress.

[0013] In a second aspect, the present invention provides a semiconductor device, wherein the semiconductor device is manufactured by the semiconductor device manufacturing method described in any one of the aforementioned embodiments.

[0014] The beneficial effects of the embodiments of the present invention are: The present invention provides a method for preparing a semiconductor device, comprising the steps of: S10. providing a GaAs substrate; S20. corroding a first surface of the GaAs substrate using a first treatment liquid, wherein the first treatment liquid is H 3 PO 4 :H 2 O 2 :H 2 O=1:1:138-2:1:50, so that the first surface forms a concave-convex structure; S30. Forming SiN covering the concave-convex structure on the first surface x layer.

[0015] In the formation of SiN x Before the layer is formed, the first surface of the GaAs substrate is roughened by using a first treatment liquid to form a concave-convex structure, thereby increasing the contact with the SiN x Layer contact area, SiN x The adhesion of the layers is improved, which avoids the gold falling off when the subsequent thick gold layer, the second metal layer, and the first metal layer are peeled off, thereby improving the product yield and the stability of device performance. Phosphoric acid (H 3 PO 4 ) is a corrosion inhibitor, which mainly forms a protective phosphate film through the reaction of phosphoric acid and GaAs substrate, thereby achieving the purpose of corrosion inhibition. This film can prevent the first surface of the GaAs substrate from further contacting and chemically reacting with substances such as acid and oxygen, thereby protecting the surface of the GaAs substrate. At the same time, phosphoric acid also has certain stability and solubility, and the corrosion is more stable. In this embodiment, the first treatment liquid is selected from H 3 PO 4 :H 2 O 2 :H 2 O=1:1:138-2:1:50, because low concentration phosphoric acid cannot effectively etch the GaAs substrate to increase the surface roughness, and high concentration phosphoric acid speed is uncontrollable. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 A schematic diagram of a semiconductor device prepared by the semiconductor device preparation method provided by an embodiment of the present invention; Figure 2 A schematic diagram of step S21 in the method for preparing a semiconductor device provided by an embodiment of the present invention; Figure 3 This is a flow chart of step S40 in the method for preparing a semiconductor device provided in an embodiment of the present invention.

[0018] Icon: 1-GaAs substrate; 2-SiN x layer; 3-first metal layer; 4-thick gold layer; 5-second metal layer; 6-pit; 7-photoresist layer; 8-window. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0020] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0022] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, or the positions or positional relationships in which the product of the invention is usually placed when in use. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0023] In addition, the terms "horizontal", "vertical" and the like do not mean that the components are required to be absolutely horizontal or suspended, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0024] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0025] like Figure 1 As shown, the present invention provides a method for preparing a semiconductor device, comprising the steps of: S10. Provide a GaAs substrate 1.

[0026] S20. Using a first treatment liquid to etch the first surface of the GaAs substrate 1, wherein the first treatment liquid is H 3 PO 4 :H 2 O 2 :H 2 O=1:1:138-2:1:50, so that the first surface of the GaAs substrate 1 forms a rough concavo-convex structure.

[0027] First, phosphoric acid (H 3 PO 4 ) is a corrosion inhibitor, which forms a protective phosphate film through the reaction of phosphoric acid and GaAs substrate 1, thereby achieving the purpose of corrosion inhibition. This film can prevent the first surface of GaAs substrate 1 from further contacting and chemically reacting with substances such as acid and oxygen, thereby protecting the surface of GaAs substrate 1. At the same time, phosphoric acid also has certain stability and solubility, and the corrosion is more stable.

[0028] In the scheme, hydrochloric acid is not used for etching because: x Before forming layer 2, the ridge waveguide of the GaAs substrate 1 was etched (the exposed part of this layer is a high Al component). Hydrochloric acid will accelerate the corrosion of the high Al layer, but phosphoric acid will not cause such a phenomenon. Hydrofluoric acid is not used because hydrofluoric acid itself is not a corrosion-inhibiting solvent, but a highly corrosive acid. When the solution ratio concentration is low, it will also have a strong corrosive effect on the GaAs substrate 1. In summary: phosphoric acid is selected as a corrosion-inhibiting solvent for the purpose of removing the surface oxide layer and coarsening, and its stability and corrosion inhibition are used to achieve a stable and controllable effect, which can not only remove the oxide layer but also have a controllable chemical reaction with the GaAs substrate 1.

[0029] The corrosion time range t in step S20 can be 15s-20s. If the time is too long, the corrosion is too deep. If the time is too short, the concave-convex degree is insufficient and the roughening effect is not achieved. After the reaction, the maximum height difference of the concave-convex structure is 8nm-10nm, and the maximum height difference refers to the longitudinal distance between the lowest point of the concave part and the highest point of the convex part.

[0030] Among them, the main steps of surface corrosion are as follows: A. Prepare the first treatment solution (H 3 PO 4 :H 2 O 2 :H 2 O=1:1:138-2:1:50); then the first treatment liquid is introduced into the circulation tank of the spin dryer (SRD) for circulation, and when the temperature of the first treatment liquid is cooled to 24°C±2°C, a wafer verification is performed (at a rate of about 40n / min), and then the GaAs substrate 1 is placed in the first treatment liquid and etched for 15s; B. Take the GaAs substrate 1 out of the first treatment liquid, and put it into pure water (DIW) for 255 seconds. Specifically, first, inject deionized water; then, spray ionized water; then, nitrogen blast: it can increase the impact force to enhance the cleaning effect and avoid the formation of oxides on the wafer surface; finally, quickly drain: quickly drain the deionized water.

[0031] C. After flushing, take it out and put it into the dryer for drying. Specifically, rinse it first; then blow it clean; then dry it once: coarse drying, speed 600; finally, dry it twice: fine drying, speed 800.

[0032] S30. Forming SiN covering the concave-convex structure on the first surface x Layer 2.

[0033] Specifically, a plasma enhanced chemical vapor deposition method can be used to prepare SiN on the first surface of the GaAs substrate 1. x Layer 2.

[0034] Furthermore, the step S30 includes the following specific steps: Obtain the warping direction of the first surface of the GaAs substrate 1. Due to the limitation of its own properties, the first surface of the existing GaAs substrate 1 may not be a plane, but a completely curved surface upward or downward. x Before layer 2, the curvature of the first surface is detected, and then SiN with different properties is prepared according to its curvature. x Layer 2.

[0035] S N x Layer 2 uses low-frequency SiN x Single layer and high frequency SiN x The single layer is formed by multiple alternating depositions. x When one side of layer 2 is warped, the layer in contact with the first surface of GaAs substrate 1 is low-frequency SiN x When the first surface of the GaAs substrate 1 faces away from the SiN x When one side of layer 2 is warped, the layer in contact with the first surface of GaAs substrate 1 is high-frequency SiN x Single layer; the low frequency SiN x The single layer is subjected to compressive stress, the high frequency SiN x The single layer is subjected to tensile stress. x The stress of the single layer of layer 2 in contact with the first surface is more compatible with the first surface of GaAs, and the two fit more closely.

[0036] Specifically, SiN x The deposition of layer 2 is divided into the following steps: 1. Preheating: N 2 Volume flow rate: 1 000 sccm, pressure: 1000 mT, temperature: 300°C.

[0037] Second. Gas stability: N 2 Volume flow rate: 900 sccm, pressure 900 mT, temperature: 300°C.

[0038] Third.N 2 Plasma surface treatment: N 2 Volume flow: 900sccm, pressure 900mT, power: 90W, temperature: 300°C.

[0039] Third.N 2Cleaning: 30s vacuuming, 30s breaking vacuum, 3 cycles.

[0040] 5. Gas stabilization: SiH 4 50sscm, NH 3 38sccm,N 2 200sccm, pressure 1080mT, temperature: 300°C.

[0041] 6. High-frequency SiN x Single layer: SiH 4 Volume flow rate: 50sscm, NH 3 Volume flow rate: 38sccm, N 2 Volume flow rate: 200 sccm, pressure 1080 mT, power 30 W (HF), temperature: 300°C.

[0042] 7. Low frequency SiN x Single layer: SiH 4 Volume flow rate: 50sscm, NH 3 Volume flow rate: 38sccm, N 2 Volume flow rate: 200sccm, pressure 1080mT, power 30W (LF), temperature: 300°C. (Whether the sixth step or the seventh step is performed first is selected according to the warping direction of the first surface of the GaAs substrate 1. The sixth step and the seventh step are repeated for 15 cycles. For example, the sixth step is performed first, then the seventh step, and then the sixth step is performed again. This is repeated for 15 cycles.)

[0043] 8. Vacuum.

[0044] The method further includes a step of forming an ohmic contact layer after step S30, specifically including: S41. Forming a first metal layer 3 of an ohmic contact layer on the first surface, wherein the first metal layer 3 covers a portion of SiN x The method may further include the following steps before step S30: step S21. forming a pit 6 in the first region of the first surface, wherein the SiN x Layer 2 covers the first region, wherein the SiN x The area formed by the projection of the area of ​​the layer 2 not covered by the first metal layer 3 onto the first surface of the GaAs substrate 1 is the first area; along the depth direction of the pit 6, there is at least one position in the pit 6 where the cross-sectional area is larger than the opening area of ​​the pit 6, so that in step S30, the pit 6 is filled with SiN x Layer 2 material.

[0045] like Figure 2 As shown, when preparing the ohmic contact layer, SiN x Part of the layer 2 is covered by the first metal layer 3, while part of the layer is not covered (i.e., the first region). Since the stress is the largest when the thick gold layer 4 and the second metal layer 5 are peeled off, the SiN x The area covered by the first metal layer 3 in the layer 2 is protected, while the first area is not protected. Therefore, it is necessary to further increase the GaAs substrate 1 and the SiN x Adhesion of layer 2. After the pit 6 is formed, SiN x When preparing layer 2, part of SiN x will enter the pit 6. Since the pit 6 is a pocket-shaped structure with a wide middle and a narrow opening, the SiN x The layer 2 will be partially stuck in the pit 6, thereby increasing the gap between the GaAs substrate 1 and the SiN x Adhesion of layer 2.

[0046] In this embodiment, the ratio of the width L of the opening of the pit 6 to the depth H of the pit 6 is L:H>5:1, and L:H<12:1. x It has step coverage, and controlling the ratio of the opening length and height does not affect the silicon nitride deposition.

[0047] The pit 6 can be formed by wet etching. Due to the isotropy during etching, the etching process will be lateral, and a pocket-shaped opening with a wide middle and a narrow opening will naturally be formed. Specifically, the step S21 specifically includes the following steps: S211. A mask having an opening is formed at a first area on the first surface of the GaAs substrate 1. The mask can be formed by photolithography. S212. The first area is etched through the opening using a first processing liquid to form a pit 6 of the above-mentioned morphology.

[0048] The formation of the pit 6 can be performed before the surface roughening treatment, that is, the surface of the GaAs substrate 1 is first subjected to photolithography development and then stripping to form a mask, and then the surface of the GaAs substrate 1 is etched using the mask to form the pit 6, and then stripping; then the first treatment liquid is used for roughening to form a concave-convex structure, and finally rinsed and dried to obtain a GaAs substrate 1 with pits 6 and a rough surface. The provision of the pit 6 can further increase the degree of surface roughening and improve the first surface and SiN x The contact area of ​​layer 2 increases its adhesion.

[0049] like Figure 3 As shown, the semiconductor device manufacturing method further includes a step of forming an ohmic contact layer after step S30, wherein the step of forming the ohmic contact layer further includes: S42. A photoresist layer 7 is formed on the first metal layer 3, and windows 8 are formed on the photoresist layer 7 and penetrate the upper and lower surfaces thereof.

[0050] The photoresist layer 7 is used to form a mask for the thick gold layer 4. Photoresist is coated on the upper surface of the first metal layer 3, and after exposure and development, a window 8 penetrating the upper and lower surfaces of the photoresist layer 7 is formed in a preset thick gold layer 4 area.

[0051] S43 . forming a thick gold layer 4 , wherein a portion of the thick gold layer 4 covers the photoresist layer 7 , and another portion is located in the window 8 .

[0052] The thick gold layer 4 is gradually formed by deposition from top to bottom, a part of which covers the photoresist layer 7 , and another part of which is located in the window 8 .

[0053] S43 . Form a second metal layer 5 on the thick gold layer 4 .

[0054] After the thick gold layer 4 is prepared, the second metal layer 5 is directly prepared thereon.

[0055] S44. Remove the photoresist layer 7, so that the part of the thick gold layer 4 and the part of the second metal layer 5 above the photoresist layer 7 are uniformly peeled off, and the projections of the thick gold layer 4 and the second metal layer 5 toward the GaAs substrate 1 are both located on the SiN x Outside layer 2.

[0056] The photoresist layer 7 is peeled off, and the part of the thick gold layer 4 and the part of the second metal layer 5 covering the photoresist layer 7 are peeled off together, and the morphology of the part of the thick gold layer 4 and the part of the second metal layer 5 at the position of the window 8 is retained.

[0057] In the prior art, in the step of forming the ohmic contact layer: the thick gold layer 4 is first peeled off, and then the second metal layer 5 is plated, and then the second metal layer 5 is peeled off. When the second metal layer 5 is peeled off, it has a great impact on the warpage of the GaAs substrate 1. The wafer warpage changes greatly, that is, the stress of the second metal layer 5 is large, which will cause the film stress mismatch. Therefore, in this method, the edge of the second metal layer 5 is shrunk, and SiN is formed in the area not protected by the thick gold layer 4. x Layer 2 + first metal layer 3 system, not SiN x The system of layer 2+first metal layer 3+second metal layer 5 has a significant improvement in adhesion. Therefore, in this method, the thick gold layer 4 and the second metal layer 5 are uniformly peeled off, and the stress generated during the peeling of the thick gold layer 4 is small, thereby reducing the generation of large stress and reducing the impact of the peeling of the second metal layer 5 on the GaAs substrate 1.

[0058] The present invention provides a semiconductor device, wherein the semiconductor device is prepared by the semiconductor device preparation method described in any one of the above embodiments. In the semiconductor device, the GaAs substrate 1 and the SiN x Layer 2 has strong adhesion and is not prone to gold falling off during peeling.

[0059] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing a semiconductor device, characterized in that: Includes steps: S10. Providing a GaAs substrate (1); S20. Etching the first surface of the GaAs substrate (1) using a first treatment liquid, wherein the first treatment liquid is H3PO4:H2O2:H2O=1:1:138-2:1:50, so that a concave-convex structure is formed on the first surface; S30. Forming a SiNx layer (2) covering the concave-convex structure on the first surface.

2. The method for preparing a semiconductor device according to claim 1, characterized in that: The time t for corroding the first surface in the step S20 ranges from 15s to 20s.

3. The method for preparing a semiconductor device according to claim 1, wherein: In the step S20, the maximum height difference of the concave-convex structure ranges from 8 nm to 10 nm.

4. The method for preparing a semiconductor device according to claim 1, wherein: The following steps are also included after step S30: S41. Forming a first metal layer (3) of an ohmic contact layer on the first surface, wherein the first metal layer (3) covers a portion of the SiN x layer(2); The following steps are also included after step S20: Step S21. Form a pit (6) in the first region of the first surface, wherein the SiN x The layer (2) covers the first region, wherein the SiN x The area formed by the projection of the area in the layer (2) not covered by the first metal layer (3) onto the first surface of the GaAs substrate (1) is the first area; Along the depth direction of the pit (6), there is at least one position in the pit (6) where the area of ​​the cross section is larger than the area of ​​the opening of the pit (6).

5. The method for preparing a semiconductor device according to claim 4, characterized in that: The step S21 specifically includes the following steps: S211. Forming a mask having an opening at a first region of a first surface of a GaAs substrate (1); S212. Etching the first area through the opening using the first processing liquid to form a pit (6).

6. The method for preparing a semiconductor device according to claim 4, characterized in that: The ratio of the width L of the opening of the pit (6) to the depth H of the pit (6) is L:H>5:1, and L:H<12:

1.

7. The method for preparing a semiconductor device according to any one of claims 1 to 6, characterized in that: The following steps are also included after step S30: S41. Forming a first metal layer (3) of an ohmic contact layer on the first surface, wherein the first metal layer (3) covers a portion of the SiN x layer(2); S42. forming a photoresist layer (7) on the first metal layer (3), wherein windows (8) are formed on the photoresist layer (7) and penetrate the upper and lower surfaces thereof; S43. forming a thick gold layer (4), wherein a portion of the thick gold layer (4) covers the photoresist layer (7), and another portion is located within the window (8); S43. Forming a second metal layer (5) on the thick gold layer (4); S44. Remove the photoresist layer (7) so that part of the thick gold layer (4) and part of the second metal layer (5) above the photoresist layer (7) are uniformly peeled off, and the projections of the thick gold layer (4) and the second metal layer (5) toward the GaAs substrate (1) are both located on the SiN x Outside layer (2).

8. The method for preparing a semiconductor device according to any one of claims 1 to 6, characterized in that: In the step S30, a SiN substrate is prepared on the first surface of the GaAs substrate (1) by using a plasma enhanced chemical vapor deposition method. x Layer (2).

9. The method for preparing a semiconductor device according to claim 8, characterized in that: The step S30 comprises the steps of: S31. Obtaining a warping direction of a first surface of the GaAs substrate (1); S32. When the first surface of the GaAs substrate (1) faces the SiN x When one side of the layer (2) is warped, a low-frequency SiN x Single layer; When the first surface of the GaAs substrate (1) faces away from the SiN x When one side of the layer (2) is warped, the layer in contact with the first surface of the GaAs substrate (1) is a high-frequency SiN x Single layer; The low frequency SiN x The single layer is subjected to compressive stress, the high frequency SiN x The single layer is subjected to tensile stress.

10. A semiconductor device, characterized in that: The semiconductor device is manufactured by the semiconductor device manufacturing method according to any one of claims 1 to 9.

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