A manufacturing method for a multi-grain chip packaging structure

Abstract

The present invention relates to the technical field of packaging structures, and particularly to a manufacturing method of a multi-die chip packaging structure. Steps: The silicon wafer contains Die C, and Die A and Die B are pasted on the silicon wafer on both sides of Die C by a pick-and-place process; Die A and Die B are encapsulated to form an encapsulation layer covering the silicon wafer; the encapsulation layer is fixed on a substrate, and a controllable de-bonding material is covered between the substrate and the encapsulation layer. The thickness of the silicon wafer is thinned, vias are etched on the silicon wafer, and a conductive layer is deposited in the vias; a protective layer is formed on the silicon wafer, and re-wiring is performed on the surface of the protective layer, and the circuit is connected to the silicon wafer and the conductive layer to form a circuit layer; bumps are fabricated on the protective layer, and the bumps are connected to the circuit layer; the substrate is removed by a de-bonding process to obtain the final structure; wherein, the controllable de-bonding material is formed by compounding microspheres and BCB resin, and the microspheres include expandable microspheres. The process of the present invention is simple, has low cost and high yield.

Description

Technical Field

[0001] The present invention relates to the technical field of packaging structures, and in particular to a manufacturing method for a multi-die chip packaging structure. Background Art

[0002] In existing multi-chip stack structures, referring to Figure 8 and Figure 9 as shown, the interconnect technologies used are generally Mega Pillar + Solder or TSV + Solder. These two technical processes are complex to fabricate, have a low yield rate, and are costly. Summary of the Invention

[0003] Object of the Invention: To solve the technical deficiencies of the existing technology, the present invention provides a manufacturing method for a multi-die chip packaging structure.

[0004] The technical solution of the present invention is as follows:

[0005] A manufacturing method for a multi-die chip packaging structure includes the following steps:

[0006] The dies include Die A, Die B, and Die C. Die C is included in the silicon wafer. Die A and Die B are pasted on the silicon wafer on both sides of Die C by a pick-and-place process;

[0007] Encapsulate Die A and Die B to form an encapsulation layer covering the silicon wafer;

[0008] Fix the encapsulation layer on the substrate by a bonding process. A controllable de-bonding material is covered between the substrate and the encapsulation layer. Thin the thickness of the silicon wafer, etch a plurality of through holes in the silicon wafer, and deposit a conductive material in the through holes to form a conductive layer;

[0009] Form a protective layer on the silicon wafer, rewire the lines on the surface of the protective layer by an RDL process, and connect the lines to the silicon wafer and the conductive layer to form a circuit layer;

[0010] Fabricate bumps on the protective layer by a bump process, and connect the bumps to the circuit layer;

[0011] Remove the substrate by a de-bonding process to obtain a multi-die chip packaging structure;

[0012] Among them, the controllable de-bonding material is formed by compounding microspheres and BCB resin, and the microspheres include expandable microspheres.

[0013] Furthermore, the number of through holes is at least six, and there are at least two through holes at the connection between Die A and the silicon wafer, at least two through holes at the connection between Die B and the silicon wafer, and at least two through holes at the connection between Die C and the silicon wafer.

[0014] Further, the material of the protective layer includes an insulating material, and the insulating material includes PI.

[0015] Further, the RDL process is used in combination with photolithography, development, and deposition to rewire the surface of the protective layer, connecting the circuit to the silicon wafer and the conductive layer to form a circuit layer.

[0016] Further, after forming the encapsulation layer covering the silicon wafer, the thickness of the encapsulation layer is thinned by a grinding process, and then the bonding process is performed.

[0017] Further, after fixing the encapsulation layer on the substrate by the bonding process, the substrate is flipped so that the substrate faces downward and the silicon wafer faces upward.

[0018] Further, the preparation method of the controllable debonding material includes the following steps:

[0019] BCB resin is added to mesitylene and heated with stirring until dissolved to obtain a BCB solution;

[0020] Microspheres or pretreated microspheres are added to the BCB solution, stirred evenly to obtain a slurry, and the slurry is degassed under vacuum to obtain the controllable debonding material.

[0021] Further, the preparation method of the pretreated microspheres includes the following steps:

[0022] The microspheres are dispersed in isopropanol, a silane coupling agent is added, dispersed, filtered to obtain the treated microspheres, and dried to obtain the pretreated microspheres.

[0023] Further, during vacuum degassing, the vacuum is pumped to -0.05 MPa to -0.15 MPa.

[0024] Further, the debonding process includes the following steps:

[0025] Heat the bottom of the substrate to the target temperature, keep it warm, and stop heating after the controllable debonding material is separated from the substrate and the encapsulation layer respectively. The target temperature is 80 - 130 °C.

[0026] The present invention provides a manufacturing method for a multi - die chip packaging structure. Compared with the prior art, the following beneficial effects exist:

[0027] In the prior art, the die size is small, and the related interconnect technologies usually involve Mega Pillar, TSV, such as the two processes mentioned in the background art. The process fabrication is complex, the yield is low, and the cost is high.

[0028] The present invention stacks multiple dies using a method different from the prior art to achieve the interconnection of multiple dies. The present invention does not stack the dies vertically or with an offset or create vertical channels between the dies.

[0029] The silicon wafer of the present invention contains Die C. Die A and Die B are pasted on the silicon wafer on both sides of Die C by a pick-and-place process. After encapsulation, grinding (optional), bonding, flipping, and grinding, multiple through-holes are etched on the silicon wafer. The number of through-holes is at least six, which are respectively connected to Die A, Die B, and Die C. Conductive materials are deposited in the through-holes, ensuring efficient electrical connection between each die, reducing signal delay, improving the overall performance of the chip, and avoiding the use of complex processes at the same time. After etching, it also includes CVD, RDL, bump process, and debonding process.

[0030] In order to improve the fineness of the die process and further improve the yield, the present invention improves the controllable debonding process. Based on the composite preparation of microspheres and BCB resin, a controllable debonding material is prepared, which solves the problems that the traditional debonding process is prone to cause chip cracking, residual chemical substances, or high-temperature damage to devices. The controllable debonding material realizes self-peeling through the thermal expansion characteristics of the microspheres, and the debonding temperature can be as low as 80°C, reducing the risk of damage to the chip and packaging structure caused by thermal stress. The debonding process mainly occurs at the interface between the microspheres and the BCB resin, reducing the residues on the substrate and realizing non-destructive debonding.

[0031] Generally speaking, the method of the present invention has simple process, low cost, and high yield. Brief Description of the Drawings

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative work, other drawings can also be obtained based on these drawings.

[0033] Figure 1 It is a schematic structural diagram of the incoming wafer of the present invention;

[0034] Figure 2 It is a schematic structural diagram of the pick-and-place process of the present invention;

[0035] Figure 3 It is a schematic structural diagram of the encapsulation process of the present invention;

[0036] Figure 4 It is a schematic structural diagram of the bonding and flipping of the present invention;

[0037] Figure 5 It is a schematic structural diagram of the through-hole process of the present invention;

[0038] Figure 6 It is a schematic structural diagram of the three processes of CVD-RDL-C4 of the present invention;

[0039] Figure 7Schematic diagram of the structure for the debonding process of the present invention;

[0040] Figure 8 Schematic diagram of the prior art structure cited in the background art of the present invention Figure 1 ;

[0041] Figure 9 Schematic diagram of the prior art structure cited in the background art of the present invention Figure 2 .

[0042] Figures 1 - 7 The combination reflects the change process of the structure in the preparation of the present invention.

[0043] In the figure, the markings are: 1. Silicon wafer; 2. Die C; 3. Die A; 4. Die B; 5. Encapsulation layer; 6. Substrate; 7. Through hole; 8. Conductive layer; 9. Protective layer; 10. Circuit layer; 11. Bump. Detailed implementation manners

[0044] Next, the technical solutions of the present invention will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without making creative efforts shall fall within the protection scope of the present invention.

[0045] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation to the present invention. In addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0046] In the description of the present invention, it should be noted that unless otherwise clearly specified and defined, the terms "mounted", "connected", "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0047] In addition, the technical features involved in different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0048] A manufacturing method of a multi-die chip package structure is provided below.

[0049] Example 1

[0050] Below, in order to distinguish the dies in the chip, they are named Die A, Die B, and Die C respectively. Supplementary note, the foregoing are not numbered, and the following will be described in conjunction with the drawings and numbers.

[0051] Referring to Figure 1 , the incoming wafer is silicon wafer 1, and there are Die C 2 in silicon wafer 1.

[0052] Referring to Figure 2 , on silicon wafer 1, Die A 3 and Die B 4 are pasted on both sides of Die C 2 on silicon wafer 1 by the pick-and-place process (PNP). Among them, for pasting, a DAF film (wafer bonding film) can be used, that is, a DAF film is covered between Die A 3 or Die B 4 and silicon wafer 1.

[0053] Molding: Referring to Figure 3 , epoxy molding compound (EMC) is used for molding, Die A 3 and Die B 4 are molded inside, and a molding layer 5 is formed on silicon wafer 1.

[0054] Grinding: The thickness of the molding layer 5 is reduced by the grinding process. Grinding is an optional step and can be selected according to actual needs.

[0055] Bonding and Flip Carrier: Referring to Figure 4 , the molding layer 5 is fixed on the substrate 6 (Carrier) by the bonding process, the substrate 6 is flipped, and the substrate 6 is facing down and the silicon wafer 1 is facing up. It should be noted that the bonding here is a temporary bonding, and debonding is required later.

[0056] Grinding and Dry Etch: Referring to Figure 5 , the thickness of the silicon wafer 1 is reduced by the grinding process. Through the dry etch process, vias 7 are formed on the silicon wafer 1. The number of vias 7 is at least six. There are at least two symmetric vias 7 at the connection between Die A 3 and the silicon wafer 1, at least two symmetric vias 7 at the connection between Die B 4 and the silicon wafer 1, and at least two symmetric vias 7 at the connection between Die C 2 and the silicon wafer 1.

[0057] Chemical Vapor Deposition (CVD): Referring to Figure 6 , a conductive material is deposited in the vias 7 by the CVD process to form a conductive layer 8, and the conductive material includes metal.

[0058] Redistribution Layer (RDL): Refer to Figure 6 , a protective layer 9 is pasted or coated on the silicon wafer 1. The protective layer 9 can be an insulating material, such as PI (polyimide).

[0059] Using the RDL (Redistribution Layer) process in combination with photolithography, development, and deposition to perform redistribution on the surface of the protective layer 9, connecting the circuit to the silicon wafer 1 and the conductive layer 8, thereby forming a circuit layer 10. Among them, the RDL process in combination with photolithography, development, and deposition is as follows: applying a photoresist on the protective layer 9, exposing it with a mask in combination, developing it to produce a new circuit pattern, and then using electroplating technology to produce a new circuit in the circuit pattern, connecting this circuit to the silicon wafer 1 and the conductive layer 8 to achieve redistribution on the surface of the protective layer 9 and form the circuit layer 10. It should be noted that the circuit is usually a metal circuit, and the metal of the metal circuit can select conventional metal materials in the RDL technology, such as copper. Through the above steps, a high-precision circuit layer 10 is constructed on the surface of the protective layer 9, and reliable interconnection with the silicon wafer 1 and the conductive layer 8 is achieved.

[0060] Bump process: Refer to Figure 6 , using the C4 bump process to fabricate bumps 11 on the protective layer 9, and the bumps 11 are connected to the circuit layer 10.

[0061] Debond: Refer to Figure 7 , using the debonding process to remove the substrate 6 to complete the final structure.

[0062] The final structure prepared by the method of the present invention realizes the stacking of multiple chips. It is not a vertical or offset stacking. Die A 3 and Die B 4 are stacked on both sides of Die C 2 and do not coincide.

[0063] It should be noted that in the steps of the foregoing process, the processes not specifically described are conventional and can be known to those skilled in the art, and are not key factors affecting the process of this application, so they will not be elaborated here.

[0064] Furthermore, in the bonding and debonding processes, traditional methods include thermal slip dissociation, mechanical peeling, chemical dissolution, and laser ablation. The debonding process usually requires precise control and cannot damage the chip and the packaging structure. Traditional mechanical debonding is prone to generating stress, resulting in chip breakage. Chemical dissolution is prone to leaving chemical residues, affecting the device performance, or requires the use of a cleaning agent to further dissolve the reagent, which is prone to uneven dissolution leading to stress concentration or long dissolution time and requires a large amount of cleaning agent. In the process of using the thermal slip method, the stress generated by the slip may cause cracks in the ultra-thin wafer. The instantaneous high temperature of laser ablation may damage the silicon device.

[0065] Therefore, the following further studies are carried out on the temporary bonding materials used in the bonding and debonding processes.

[0066] Unless otherwise specified, raw materials, reagents, equipment, or parts can be obtained through regular purchases.

[0067] Example 2

[0068] The manufacturer models of the raw materials used in Example 2 are as follows:

[0069] Silane coupling agent: Dynasylan® MEMO;

[0070] BCB resin: The BCB resin is benzocyclobutene resin. Here, a liquid form, Dow Cyclotene 3022-46 with a solid content of 46 wt% is selected.

[0071] Microspheres: Expanded microspheres, Nouryon Expancel 031 WUF 40;

[0072] Mesitylene: Analytically pure;

[0073] Isopropyl alcohol: AR, ≥99.7%.

[0074] Use the raw materials of the manufacturer models in this example to prepare a controllable debonding material. The specific steps are as follows:

[0075] Step 1: Weigh 5 g of microspheres, disperse the microspheres in 50 mL of isopropyl alcohol, add 0.1 g of silane coupling agent, ultrasonically disperse for 15 - 30 minutes, filter the dispersion, collect the microspheres, obtain the treated microspheres, and vacuum dry the treated microspheres at 30 - 60 °C to obtain the pretreated microspheres.

[0076] Step 2: Put 50 g of BCB resin into a brown glass bottle, add 35 mL of mesitylene, place the glass bottle on a magnetic stirrer, heat and stir at 45 °C at a speed of 300 rpm until the BCB is completely dissolved to obtain a BCB solution, and store it in the dark.

[0077] Step 3: Slowly add 5 g of pretreated microspheres to the BCB solution, stir evenly to obtain a slurry. Vacuum degas the slurry, pump to -0.1 MPa and keep for 20 minutes. After degassing, obtain the controllable debonding material.

[0078] It should be noted that the surface-modified microspheres are compounded with the BCB resin to prepare a composite material with a controllable debonding function.

[0079] The temporary bonding / delamination techniques in the prior art (such as mechanical peeling, wet chemical dissolution, etc.) usually rely on external physical or chemical conditions (such as solvent immersion, laser irradiation) to achieve delamination. However, in this solution, through the surface modification of microspheres and the compounding with BCB resin, the controllable fracture of chemical bonds inside the material can be achieved.

[0080] When the controllable delamination material is used in the bonding process, the selected microspheres are thermoplastic microspheres containing volatile hydrocarbon blowing agents, which can expand when heated within a specific temperature range. The microspheres are surface-modified by a silane coupling agent, which attaches to the surface of the microspheres through physical adsorption or molecular chain entanglement. The introduction of the silane coupling agent can change the surface energy and wettability of the microspheres, making them more compatible with the BCB resin. Moreover, the double bond of the silane coupling agent can react with BCB to form covalent bonds through a free radical polymerization reaction. In this way, the silane coupling agent acts as a "bridge", with one end of its double bond connected to the BCB resin through a covalent bond and the other end combined with the microspheres through physical adsorption, molecular chain entanglement, or weak hydrogen bonds. Thus, the microspheres can be more tightly incorporated into the BCB network.

[0081] When the controllable delamination material is used in the delamination process, it is heated to the delamination temperature of the controllable delamination material. The microspheres in the bonding layer rapidly expand, generating internal stress, which "pushes open" the substrate 6 and the encapsulation layer 5 respectively, similar to the explosion of "popcorn", to achieve rapid self-peeling. It can also achieve non-destructive delamination: the delamination mainly occurs at the interface between the microspheres and the BCB resin. The fracture of the Si-O-Si bonds of the microspheres ensures that the separation occurs at the interface rather than within the substrate.

[0082] Example 3

[0083] Different from Example 2, the microspheres are not pretreated, that is:

[0084] Put 50 g of BCB resin into a brown glass bottle, add 35 mL of mesitylene, place the glass bottle on a magnetic stirrer, and heat and stir at 45 °C at a speed of 300 rpm until the BCB is completely dissolved to obtain a BCB solution, which is stored in the dark.

[0085] Slowly add 5 g of microspheres to the BCB solution and stir evenly to obtain a slurry. Vacuum degas the slurry, evacuate to -0.1 MPa, and hold for 20 minutes to obtain the controllable delamination material.

[0086] The raw materials are the same as those in Example 2.

[0087] It should be noted that through the above process, the microspheres are attached to the BCB network.

[0088] Example 4

[0089] Different from Example 1,

[0090] During the bonding process, the controllable debonding material of Example 2 is spin-coated between the substrate 6 and the encapsulation layer 5 with a film thickness of 5 μm and dried at 30 - 60 °C.

[0091] During the debonding process, heat is applied to the bottom of the substrate 6 at a rate of 10 °C / min to the target temperature and held there. After the controllable debonding material separates from the substrate 6 and the encapsulation layer 5 respectively, heating is stopped. It should be noted that an epoxy molding compound with a high decomposition temperature of 150 - 200 °C or higher is selected to avoid affecting the encapsulation layer 5 during debonding.

[0092] The rest is the same as in Example 1.

[0093] It should be noted that drying at 30 - 60 °C volatilizes the solvent of the controllable debonding material to form a solid coating with temporary bonding effect, and does not completely cure the controllable debonding material. Moreover, material curing is not required during temporary bonding, and debonding is still needed later. When drying at 30 - 60 °C, the BCB resin will crosslink to a certain extent to form a preliminary solid layer with certain mechanical strength and adhesion, which can meet the requirements of temporary bonding. The BCB resin is a thermosetting resin, and the temperature required for complete curing can reach 200 °C, which may damage the packaging structure. Moreover, its cured state is generally irreversible, resulting in difficult debonding. Therefore, in the technical solution of this application, drying at 30 - 60 °C is set to avoid premature expansion of the microspheres.

[0094] Since the BCB resin is not completely crosslinked and cured, its viscosity is low and it is easy to remove, which also reduces the residues on the substrate 6 after debonding.

[0095] Example 5

[0096] Different from Example 4, the controllable debonding material of Example 3 is selected. The rest is the same as in Example 4.

[0097] It should be noted that in Examples 4 and 5, the temperature does not reach the target temperature instantaneously, but rises to the required temperature gradually in a gradient manner. Moreover, the expansion temperature of the materials selected in this application can be adjusted according to the debonding situation. The target temperature is the temperature at which debonding occurs. After reaching the target temperature, it is held until complete debonding.

[0098] Controllable debonding performance test method:

[0099] For Examples 4 and 5, during the debonding process, heat is applied to the bottom of the substrate 6 at a rate of 10 °C / min to the target temperature and held there. After the controllable debonding material separates from the substrate 6 and the encapsulation layer 5 respectively, heating is stopped. Observe whether the debonding process is smooth and whether the substrate and the encapsulation layer can be completely separated. Record the time required for debonding and the target temperature required.

[0100] Results:

[0101] Example 4: Smooth separation. Target temperature: 100 °C. Debonding time: 121 s.

[0102] Example 5: Smooth separation. Target temperature: 80 °C. Debonding time: 187 s.

[0103] Among them, the debonding time does not include the time for heating up to the target temperature.

[0104] Analysis: The microspheres used in Example 4 were pretreated with a silane coupling agent, which improved the binding force between the microspheres and the BCB matrix. The microspheres were restricted in the BCB network, and the restriction intensity of the BCB network on the microspheres was relatively high. This requires a higher temperature to fully expand the microspheres and generate sufficient internal stress to break the bond and achieve debonding.

[0105] The microspheres used in Example 5 were not pretreated, and the binding force with the BCB resin was weakened. Although the microspheres were restricted in the BCB network, the restriction intensity of the BCB network on the microspheres was relatively low. Therefore, a lower temperature is sufficient to expand the microspheres and initiate debonding. However, the lower temperature results in a smaller internal stress generated by the expansion, so a longer time is required to accumulate enough to break the bond.

[0106] The debonding temperature of the controllable debonding material prepared in this application can be as low as 80 °C. The debonding temperature can be adjusted according to different contacting materials (such as the substrate 6 and the encapsulation layer 5), or the debonding temperature can be increased (such as 100 °C) according to different microspheres.

[0107] The controllable debonding material prepared in this application can achieve non-destructive debonding, protect the chip structure, shorten the debonding time, and reduce or avoid residues.

[0108] Obviously, the above examples are only for clear illustration and not a limitation of the implementation manners. For those of ordinary skill in the art, other different forms of changes or variations can be made based on the above description. It is not necessary and impossible to list all the implementation manners here. And the obvious changes or variations derived therefrom are still within the protection scope of the present invention.

Claims

1. A manufacturing method of a multi-grain chip packaging structure, characterized in that, It includes the following steps: The die includes Die A, Die B, and Die C. Die C is included in the silicon wafer. Die A and Die B are pasted on the silicon wafer on both sides of Die C by a pick-and-place process; there is no overlap between the dies; Encapsulate Die A and Die B to form an encapsulation layer covering the silicon wafer; Fix the encapsulation layer on the substrate by a bonding process. A controllable de-bonding material is covered between the substrate and the encapsulation layer. Thin the thickness of the silicon wafer. Etch a plurality of through holes in the silicon wafer, and deposit a conductive material in the through holes to form a conductive layer; Form a protective layer on the silicon wafer. Re-distribute the lines on the surface of the protective layer by RDL process, and connect the lines to the silicon wafer and the conductive layer to form a line layer; Fabricate bumps on the protective layer by a bump process, and connect the bumps to the line layer; Remove the substrate by a de-bonding process to obtain a multi-die chip packaging structure; Among them, the controllable de-bonding material is formed by the compounding of microspheres and BCB resin. The microspheres include expandable microspheres. The preparation method of the controllable de-bonding material includes the following steps: Add BCB resin to mesitylene, heat and stir until dissolved to obtain a BCB solution; Add the microspheres or pretreated microspheres to the BCB solution, stir evenly to obtain a slurry, and vacuum degas the slurry to obtain the controllable de-bonding material.

2. The manufacturing method of a multi-die chip packaging structure as described in claim 1, characterized in that The number of through holes is at least six. There are at least two through holes at the connection between Die A and the silicon wafer, at least two through holes at the connection between Die B and the silicon wafer, and at least two through holes at the connection between Die C and the silicon wafer.

3. The manufacturing method of a multi-grain chip packaging structure according to claim 1, characterized in that The material of the protective layer includes an insulating material, and the insulating material includes PI.

4. The manufacturing method of a multi-grain chip packaging structure according to claim 1, characterized in that Re-distribute the lines on the surface of the protective layer by RDL process in cooperation with photolithography, development, and deposition, and connect the lines to the silicon wafer and the conductive layer to form a line layer.

5. The manufacturing method of a multi-grain chip packaging structure according to claim 1, characterized in that, After forming the encapsulation layer covering the silicon wafer, thin the thickness of the encapsulation layer by a grinding process, and then perform a bonding process.

6. The manufacturing method of a multi-grain chip packaging structure as described in claim 1, characterized in that, After fixing the encapsulation layer on the substrate by a bonding process, flip the substrate so that the substrate is facing down and the silicon wafer is facing up.

7. The manufacturing method of a multi-die chip packaging structure according to claim 1, characterized in that The preparation method of the pretreated microspheres includes the following steps: Disperse the microspheres in isopropyl alcohol, add a silane coupling agent, disperse, filter to obtain the treated microspheres, and dry to obtain the pretreated microspheres.

8. The manufacturing method of a multi-grain chip packaging structure as described in claim 1, characterized in that, When vacuum degassing, evacuate to -0.05 MPa ~ -0.15 MPa.

9. The manufacturing method of a multi-grain chip packaging structure according to claim 1, characterized in that The de-bonding process includes the following steps: Heat the bottom of the substrate to the target temperature, keep warm, and stop heating after the controllable de-bonding material is separated from the substrate and the encapsulation layer respectively. Among them, the target temperature is 80 - 130 °C.

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