Chip Packaging Method, Structure and System

Abstract

The present invention provides a chip packaging method, structure and system, relating to the field of chip processing. The method includes: determining a first length and a first height of a signal line, and a second length and a second height of a shielding line; bonding the signal line to a chip and a substrate according to the first length and the first height, and bonding the shielding line to the chip and the substrate according to the second length and the second height; packaging a shielding cover on the substrate; the chip, the signal line and the shielding line are arranged in the shielding cover; one or more of a first capacitance between the signal line and the shielding cover, a second capacitance between the shielding line and the signal line, and a third capacitance between the signal line and the substrate are used to adjust the isolation degree of the chip packaging structure.

Description

Technical Field

[0001] The present invention relates to the field of chip processing, and in particular, to a chip packaging method, structure and system. Background Art

[0002] In radio frequency chip packaging, in order to solve the cavity resonance problem formed by the metal cavity packaging structure (such as metal ceramic packaging, substrate POP (Package on Package) packaging), a shielding cover scheme is often adopted to isolate the chip spatially.

[0003] The scheme of adding a shielding cover can shield the cavity resonance problem inside the entire package, but it will cause the capacitance effect between the inside of the shielding cover and the signal line to increase, and more energy radiated from the signal output port by the gold wire bonding wire (the wire length is usually not less than 500um) is coupled to the radio frequency input port, resulting in a decrease in the isolation degree between the ports, and further may cause self-excitation of the chip and abnormal operation. Currently, the conventional solution is to increase the height of the shielding cover to reduce the capacitance between the inner surface of the shielding cover and the signal line, so as to improve the isolation degree between the ports and avoid chip self-excitation. However, increasing the height of the packaging cover will make the size of the entire package larger and increase the volume of the chip packaging structure. Summary of the Invention

[0004] In view of this, the purpose of the embodiments of the present invention is to provide a chip packaging method, structure and system, which can improve the isolation degree between chip ports without increasing the size of the chip packaging structure.

[0005] In a first aspect, an embodiment of the present invention provides a chip packaging method, which is applied to a chip packaging structure. The method includes: determining a first length and a first height of a signal line, and a second length and a second height of a shielding line; bonding the signal line to a chip and a substrate according to the first length and the first height, and bonding the shielding line to the chip and the substrate according to the second length and the second height; packaging a shielding cover on the substrate; wherein the chip, the signal line and the shielding line are arranged in the shielding cover; one or more of a first capacitance between the signal line and the shielding cover, a second capacitance between the shielding line and the signal line, and a third capacitance between the signal line and the substrate are used to adjust the isolation degree of the chip packaging structure.

[0006] In the above implementation process, by adding a shielding wire in the chip package and setting a shielding cover above the chip, the signal wire and the inner cavity of the shielding cover can be regarded as two substrates of a parallel capacitor, and the signal wire and the shielding wire can also be regarded as two substrates of a parallel capacitor. By adjusting the first capacitance between the signal wire and the shielding cover, the second capacitance between the shielding wire and the signal wire, and the third capacitance between the signal wire and the substrate, the isolation degree between ports is adjusted. Compared with the existing method of improving the isolation degree by increasing the height of the shielding cover, there is no need to increase the size of the chip package structure, meeting the requirements of chip miniaturization. That is, the isolation degree between the chip ports can be improved without increasing the size of the chip package structure.

[0007] In one embodiment, the determining the first length and the first height of the signal wire, and the second length and the second height of the shielding wire includes: determining the first capacitance, the second capacitance, and the third capacitance according to the target isolation degree of the chip package structure; determining the first length, the first height, the second length, and the second height according to the first capacitance, the second capacitance, and the third capacitance.

[0008] In the above implementation process, by determining the corresponding first length and first height of the signal wire, and the second length and second height of the shielding wire according to the target isolation degree, the first capacitance formed by the signal wire and the shielding cover after bonding and the third capacitance formed by the signal wire and the substrate after bonding can meet the requirements, and the second capacitance formed between the shielding wire and the signal wire after bonding can meet the requirements, thereby realizing the improvement of the isolation degree between the chip ports of the chip package structure.

[0009] In one embodiment, the determining the first length, the first height, the second length, and the second height according to the first capacitance, the second capacitance, and the third capacitance includes: based on the bonding process and material type of the signal wire, calculating a plurality of first reference capacitances and a plurality of second reference capacitances according to a plurality of preset first lengths and a plurality of preset first heights; determining the preset first lengths and the preset first heights corresponding to the first reference capacitances that meet the first capacitance range and the second reference capacitances that meet the second capacitance range as the first length and the first height respectively; based on the bonding process and material type of the shielding wire, calculating a plurality of third reference capacitances according to a plurality of preset second lengths and a plurality of preset second heights; determining the preset second lengths and the preset second heights corresponding to the third reference capacitances that meet the third capacitance range as the second length and the second height respectively.

[0010] In the above implementation process, by determining that the preset first length and the preset first height corresponding to the first reference capacitor satisfying the first capacitance range and the second reference capacitor satisfying the second capacitance range are the first length and the first height respectively, and determining that the preset second length and the preset second height corresponding to the third reference capacitor satisfying the third capacitance range are the second length and the second height respectively, the first capacitance formed by the signal line and the shielding cover, the third capacitance formed by the signal line and the substrate, and the second capacitance formed by the signal line and the shielding wire can meet the target isolation requirement, thereby improving the inter-port isolation of the chip package structure.

[0011] In one embodiment, the isolation of the chip package structure is improved by reducing the first capacitance and / or increasing the second capacitance; wherein, the first capacitance is configured to be adjusted by adjusting the relative area of the signal line and the shielding cover, and the second capacitance is configured to be adjusted by adjusting the relative area of the signal line and the shielding wire.

[0012] In the above implementation process, when packaging the chip, by reducing the first capacitance, the impedance on the coupling path can be increased, the energy coupling between ports can be reduced, thereby improving the inter-port isolation, avoiding chip self-oscillation, and improving the safety and stability of the chip. By increasing the second capacitance, the signal can return to ground nearby, reducing the radiation into space, thereby improving the inter-port isolation, avoiding chip self-oscillation, and improving the safety and stability of the chip.

[0013] In one embodiment, bonding the signal line to the chip and the substrate according to the first length and the first height, and bonding the shielding wire to the chip and the substrate according to the second length and the second height includes: bonding the signal line to the chip and the substrate according to the first length and the first height and by means of reverse bonding; and / or bonding the shielding wire to the chip and the substrate according to the second length and the second height and by means of reverse bonding.

[0014] In the above implementation process, by bonding the signal line and the shielding wire in a reverse bonding manner, the signal line and the shielding wire can have a lower arc height, reducing the occupied area of the signal line and the shielding wire, thereby reducing the volume of the chip package structure.

[0015] In one embodiment, the method further includes: encapsulating the inside of the shielding cover.

[0016] In the above implementation process, by encapsulating the inside of the shielding cover, the welding positions of the signal line and the shielding wire can be protected from impact or fluctuation, improving the stability of the signal line and the shielding wire.

[0017] In a second aspect, an embodiment of the present invention further provides a chip packaging structure, including: a substrate, a chip, a shielding cover, a signal line, and a shielding line; the chip is mounted on the substrate; the signal line and the shielding line connect the chip and the substrate; the shielding cover is mounted on the substrate, and the chip, the signal line, and the shielding line are disposed inside the shielding cover; wherein, one or more of a first capacitance between the signal line and the shielding cover, a second capacitance between the shielding line and the signal line, and a third capacitance between the signal line and the substrate are used to adjust the isolation degree of the chip packaging structure.

[0018] In the above implementation process, by adding a shielding line in the chip packaging structure and arranging a shielding cover above the chip, the inner cavity of the signal line and the shielding cover can be regarded as two substrates of a parallel capacitor, and the signal line and the shielding line can also be regarded as two substrates of a parallel capacitor. By adjusting the first capacitance between the signal line and the shielding cover, the second capacitance between the shielding line and the signal line, and the third capacitance between the signal line and the substrate, the adjustment of the isolation degree between ports is realized. Compared with the existing method of improving the isolation degree by increasing the height of the shielding cover, there is no need to increase the size of the chip packaging structure, meeting the requirements of chip miniaturization. That is, the isolation degree between chip ports can be improved without increasing the size of the chip packaging structure.

[0019] In one embodiment, a first bonding point of the signal line on the substrate and a second bonding point of the shielding line on the substrate are disposed within a preset range from the chip; and / or the distance between the first bonding point and the second bonding point is set within a preset spacing range.

[0020] In the above implementation process, by setting the first bonding point of the signal line on the substrate and the second bonding point of the shielding line on the substrate within a preset range from the chip, the arc lengths of the signal line and the shielding line can be reduced, thereby reducing the occupied area of the signal line and the shielding line, saving the costs of the signal line and the shielding line while reducing the volume of the chip packaging structure. In addition, by setting the distance between the first bonding point and the second bonding point within a preset spacing range, the distance between the signal line and the shielding line can be shortened, thereby increasing the second capacitance and improving the isolation degree between chip ports.

[0021] In one embodiment, the chip is centrally disposed in the shielding cover; wherein, the chip transmits signals to and from the substrate through the signal line.

[0022] In the above implementation process, since one of the main functions of the shielding cover is to prevent external electromagnetic fields from interfering with the internal circuits of the chip. By centrally arranging the chip in the shielding cover, it can ensure that the electromagnetic environment around the chip is relatively uniform, thereby reducing the degree of interference of external electromagnetic fields on the internal circuits of the chip. At the same time, centrally arranging the chip also helps to reduce the interference of electromagnetic radiation generated by the internal circuits of the chip on the outside world and improve the overall electromagnetic compatibility.

[0023] In a third aspect, an embodiment of the present invention further provides a chip packaging system, including: a processing device, a bonding device, and a packaging device; the processing device is used to determine the first length and the first height of the signal line, and the second length and the second height of the shielding line; the bonding device is used to bond the signal line to the chip and the substrate according to the first length and the first height, and bond the shielding line to the chip and the substrate according to the second length and the second height; the packaging device is used to package the shielding cover on the substrate; wherein, the chip, the signal line, and the shielding line are arranged in the shielding cover; one or more of the first capacitance between the signal line and the shielding cover, the second capacitance between the shielding line and the signal line, and the third capacitance between the signal line and the substrate are used to adjust the isolation degree of the chip packaging structure.

[0024] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is run by a processor, it executes the steps of the chip packaging method in the first aspect or any possible implementation manner of the first aspect.

[0025] To make the above objects, features, and advantages of the present invention more obvious and understandable, specific embodiments are hereinafter given, and in conjunction with the accompanying drawings, the detailed description is as follows. Description of the Drawings

[0026] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0027] Figure 1 It is a schematic structural diagram of the chip packaging structure provided by the embodiment of the present invention;

[0028] Figure 2 It is a flowchart of the chip packaging method provided by the embodiment of the present invention;

[0029] Figure 3Isolation degree comparison diagram between the chip packaging method provided by the embodiment of the present invention and the existing chip packaging method;

[0030] Figure 4 Schematic diagram of functional modules of the chip packaging system provided by the embodiment of the present invention.

[0031] Description of the drawings: 110 - substrate, 120 - chip, 130 - shielding cover, 140 - signal line, 150 - shielding wire, 301 - processing device, 302 - bonding device, 303 - packaging device, C1 - first capacitor, C2 - second capacitor, C3 - third capacitor. Detailed implementation manners

[0032] Next, the technical solutions in the embodiments of the present invention will be described with reference to the drawings in the embodiments of the present invention.

[0033] It should be noted that: similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of the present invention, terms such as "first", "second", etc. are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance.

[0034] Radio frequency chip packaging technology is one of the key technologies in modern electronic devices, especially playing a crucial role in fields such as wireless communication, radar systems, and medical devices. In these applications, metal cavity packaging structures (such as ceramic-metal packaging, substrate PoP packaging) are widely used to protect radio frequency chips from external environmental interference and ensure their stable operation. However, this packaging structure often faces a key problem in practical applications - cavity resonance.

[0035] Cavity resonance refers to the electromagnetic wave resonance phenomenon formed inside the metal cavity at a specific frequency. When the radio frequency chip works, it generates radio frequency signals. When these signals propagate in the metal cavity, if the size, shape, and material properties of the cavity match the frequency of the radio frequency signal, cavity resonance may be triggered. Cavity resonance not only causes loss and distortion of radio frequency signals, but may also trigger self-excited oscillation, making the circuit unable to work properly and even possibly burning out the chip.

[0036] To solve the problem of cavity resonance, the currently common solutions include:

[0037] 1. Increase the height of the shielding cover to reduce the capacitance between the inner surface of the shielding cover and the signal line, so as to improve the isolation degree between ports and avoid chip self-excitation. However, when the space layout of the packaging structure is limited, increasing the height of the shielding cover will make the size of the entire package larger, increasing the volume of the chip packaging structure.

[0038] Second, flip the chip using RDL (Redistribution layer) technology. This solution does not require a shielding cover. This solution requires the pins on the chip to be re-arranged through the RDL layer and then connected to the substrate through metal bumps (usually with a diameter of no more than 150um). This solution uses metal bumps instead of signal lines, which greatly reduces the energy radiated outward from the signal port, thereby improving the isolation between ports. However, the chip RDL process will increase the overall cost of the package, and the high loss characteristics of the RDL medium will also greatly affect the high-frequency performance of the chip.

[0039] In view of this, the present invention proposes a chip packaging method. By adding a shielding line in the chip package and setting a shielding cover above the chip, the signal line and the inner cavity of the shielding cover can be regarded as two substrates of a parallel capacitor, and the signal line and the shielding line can also be regarded as two substrates of a parallel capacitor. By adjusting the first capacitor between the signal line and the shielding cover, the second capacitor between the shielding line and the signal line, and the third capacitor between the signal line and the substrate, the isolation between the ports can be adjusted. Compared with the existing method of increasing the isolation by increasing the height of the shielding cover, there is no need to increase the size of the chip packaging structure, and the chip miniaturization requirements are met. That is, the isolation between the chip ports can be improved without increasing the size of the chip packaging structure.

[0040] To facilitate understanding of this embodiment, a chip packaging structure disclosed in an embodiment of the present invention is first introduced in detail.

[0041] like Figure 1 , is a schematic structural diagram of a chip 120 packaging structure provided in an embodiment of the present invention, including: a substrate 110 , a chip 120 , a shielding cover 130 , a signal line 140 and a shielding line 150 .

[0042] The chip 120 is mounted on the substrate 110 ; the signal line 140 and the shielding line 150 connect the chip 120 and the substrate 110 ; the shielding cover 130 is mounted on the substrate 110 , and the chip 120 , the signal line 140 and the shielding line 150 are arranged inside the shielding cover 130 .

[0043] The chip 120 here may be a controller, a processor, a memory, etc. The type of the chip 120 may be selected according to actual conditions.

[0044] The chip 120 may be made of gallium arsenide material. The size of the chip 120 may be adjusted according to actual conditions. For example, the size of the chip 120 may be 1 mm*1.5 mm*0.1 mm.

[0045] The above-mentioned substrate 110 refers to the IC packaging substrate 110, which is used to provide physical support for the chip 120 to avoid the chip 120 being affected by external physical factors such as dust, moisture, mechanical shock, etc.

[0046] Optionally, the substrate 110 can be a rigid packaging substrate 110, a flexible packaging substrate 110, a ceramic packaging substrate 110, etc. The type of the substrate 110 can be selected according to the actual situation.

[0047] In one embodiment, the substrate 110 is a copper foil. For example, a 0.2 mm thick copper foil.

[0048] The shielding cover 130 is usually a housing made of metal or alloy, which is used to isolate and shield the interference inside the electronic device or the external signal from the antenna, and can be used to improve the working stability of the device and the transmission quality of the signal. In some special occasions, the shielding cover 130 can also be used for safety performance such as dust prevention and waterproofing.

[0049] The shielding cover 130 here can be a metal shielding cover 130, and the size of the shielding cover 130 can be set according to the size of the chip 120 and the size requirements of the corresponding electronic device. For example, the size of the shielding cover 130 can be 3.2 mm * 1.8 mm * 0.6 mm.

[0050] The signal line 140 refers to the line used to transmit sensing information and control information in the electrical control circuit. The main function of the signal line 140 is to transmit the audio signal or other types of sensing information and control information generated by the signal source. In an electronic device, the signal line 140 is responsible for transmitting and connecting the signals between various components to ensure the normal operation of the device.

[0051] The signal line 140 here is configured to connect the pins of the chip 120 and the substrate 110 to achieve signal transmission between the chip 120 and the substrate 110.

[0052] The shielded wire 150 usually consists of an insulating layer, a shielding layer and a conductor. The shielding layer can conduct the external interference signal to the ground to avoid the interference signal entering the inner conductor, thereby reducing the loss of the transmitted signal.

[0053] Optionally, the signal line 140 can be one or more, and the shielded wire 150 can also be one or more. The number of the signal line 140 and / or the shielded wire 150 can be selected according to the actual situation.

[0054] Understandably, after the shielding cover 130 is disposed above the chip 120, the signal line 140 and the inner cavity of the shielding cover 130 can be regarded as two plates of a parallel-plate capacitor. According to the principle of a parallel-plate capacitor, a parallel-plate capacitor is composed of two parallel metal conductors separated by a dielectric material in the middle. When there is a certain potential difference between the two plates, an electrostatic field distribution will exist between the plates.

[0055] One or more of the first capacitance C1 between the signal line 140 and the shielding cover 130, the second capacitance C2 between the shielded wire 150 and the signal line 140, and the third capacitance C3 between the signal line 140 and the substrate 110 are used to adjust the isolation of the chip 120 packaging structure.

[0056] According to the parallel-plate capacitor formula, when the height between the signal line 140 and the shielding cover 130 is not increased, the first capacitance C1 can be reduced by decreasing the relative area between the signal line 140 and the shielding cover 130, and the second capacitance C2 can be increased by increasing the relative area between the signal line 140 and the ground wire.

[0057] In the above implementation process, by adding a shielded wire 150 to the chip 120 packaging structure and disposing a shielding cover 130 above the chip 120, the inner cavity of the signal line 140 and the shielding cover 130 can be regarded as two substrates 110 of a parallel capacitor, and the signal line 140 and the shielded wire 150 can also be regarded as two substrates 110 of a parallel capacitor. By adjusting the first capacitance C1 between the signal line 140 and the shielding cover 130, the second capacitance C2 between the shielded wire 150 and the signal line 140, and the third capacitance C3 between the signal line 140 and the substrate 110, the isolation adjustment between ports is achieved. Compared with the existing method of improving the isolation by increasing the height of the shielding cover 130, there is no need to increase the size of the chip 120 packaging structure, meeting the miniaturization requirements of the chip 120. That is, the isolation between the ports of the chip 120 can be improved without increasing the size of the chip 120 packaging structure.

[0058] In a possible implementation, the first bonding point of the signal line 140 on the substrate 110 and the second bonding point of the shielded wire 150 on the substrate 110 are set within a preset range from the chip 120; and / or the distance between the first bonding point and the second bonding point is set within a preset spacing range.

[0059] The first bonding point here refers to the connection point of the signal line 140 on the substrate 110, and the second bonding point refers to the connection point of the shielded wire 150 on the substrate 110.

[0060] Understandably, to reduce the arc length, the bonding points of the signal line 140 and / or the shielding line 150 on the substrate 110 should be as close as possible to the chip 120. Therefore, by setting the first bonding point and the second bonding point within a preset range from the chip 120, the arc lengths of the signal line 140 and the shielding line 150 can be restricted.

[0061] Among them, the preset range is configured to reduce the distance between the first bonding point and / or the second bonding point and the chip 120. This preset range can be the range where the welding material used to weld the signal line 140 and / or the shielding line 150 does not contact the chip 120. Of course, the preset range can also be other ranges according to actual requirements.

[0062] It should be understood that when the first bonding point and the second bonding point are close to each other, the distance between the signal line 140 and the shielding line 150 can be reduced, thereby increasing the second capacitance C2.

[0063] The above-mentioned preset spacing range is configured to shorten the distance between the signal line 140 and the shielding line 150, and this preset spacing range can be adjusted according to actual requirements.

[0064] In the above implementation process, by setting the first bonding point of the signal line 140 on the substrate 110 and the second bonding point of the shielding line 150 on the substrate 110 within a preset range from the chip 120, the arc lengths of the signal line 140 and the shielding line 150 can be reduced, thereby reducing the occupied area of the signal line 140 and the shielding line 150. While saving the cost of the signal line 140 and the shielding line 150, the volume of the chip 120 packaging structure is reduced. In addition, by setting the distance between the first bonding point and the second bonding point within the preset spacing range, the distance between the signal line 140 and the shielding line 150 can be shortened, thereby increasing the second capacitance C2 and improving the isolation degree between the ports of the chip 120.

[0065] In a possible implementation manner, the chip 120 is centrally disposed in the shielding cover 130.

[0066] Among them, the chip 120 transmits signals to the substrate 110 through the signal line 140.

[0067] Here, the signal line 140 is configured to transmit control signals, audio signals, status signals, radio frequency signals, etc., and the signals transmitted by the signal line 140 can be determined according to the actual requirements of the chip 120.

[0068] In one embodiment, the signal line 140 can be a gold wire.

[0069] Optionally, the chip 120 can be mounted on the substrate 110.

[0070] In the above implementation process, since one of the main functions of the shielding cover 130 is to prevent external electromagnetic fields from interfering with the internal circuits of the chip 120. By centrally arranging the chip 120 in the shielding cover 130, it can ensure that the electromagnetic environment around the chip 120 is relatively uniform, thereby reducing the degree of interference of external electromagnetic fields on the internal circuits of the chip 120. At the same time, centrally arranging the chip 120 also helps to reduce the interference of electromagnetic radiation generated by the internal circuits of the chip 120 to the outside world and improve the overall electromagnetic compatibility.

[0071] The implementation process of the chip packaging method will be described in detail through several embodiments below.

[0072] Please refer to Figure 2 , which is the flowchart of the chip packaging method provided by the embodiments of the present invention. The following will elaborate on the Figure 2 specific process shown in detail.

[0073] Step S201, determine the first length and the first height of the signal line, and the second length and the second height of the shielding line.

[0074] Here, the first length refers to the arc length of the signal line, and the first height refers to the arc height of the signal line. The second length refers to the arc length of the shielding line, and the second height refers to the arc height of the shielding line.

[0075] Among them, the first length, the second length, the first height, and the second height are jointly determined by the first capacitance between the signal line and the shielding cover, the second capacitance between the shielding line and the signal line, and the third capacitance between the signal line and the substrate.

[0076] Step S202, bond the signal line to the chip and the substrate according to the first length and the first height, and bond the shielding line to the chip and the substrate according to the second length and the second height.

[0077] After determining the first length and the first height, the arc length and the arc height of the signal line can be determined according to the first length and the first height, and then the shape of the signal line can be basically determined according to the arc length and the arc height, and the signal line is bonded to the chip and the substrate according to the shape. Among them, the arc length of the signal line bonded to the chip and the substrate is the first length, and the arc height is the first height.

[0078] Similarly, after determining the second length and the second height, the arc length and the arc height of the shielding line can be determined according to the second length and the second height, and then the shape of the shielding line can be basically determined according to the arc length and the arc height, and the shielding line is bonded to the chip and the substrate according to the shape. Among them, the arc length of the shielding line bonded to the chip and the substrate is the second length, and the arc height is the second height.

[0079] Optionally, the bonding method of the signal line may include wire bonding, flip chip bonding, automatic soldering, etc., and the bonding method of the shield wire may include wire bonding, flip chip bonding, automatic soldering, etc. The bonding method of the signal line and the shield wire can be selected according to the actual situation.

[0080] Step S203, encapsulate the shielding cover on the substrate.

[0081] Among them, the chip, the signal line, and the shield wire are arranged in the shielding cover.

[0082] It can be understood that after the shielding cover is arranged above the chip, the signal line and the inner cavity of the shielding cover can be regarded as two electrodes of a parallel plate capacitor. According to the principle of the parallel plate capacitor, a parallel plate capacitor is composed of two parallel metal conductors, separated by a dielectric material in the middle. When there is a certain potential difference between the two electrodes, there will be an electrostatic field distribution between the electrodes.

[0083] If represents the relative area of the two parallel metal plates, represents the distance between the two plates, and the space between the two plates is filled with a dielectric with a relative permittivity of . Assuming that the two corresponding surfaces on the two plates are respectively charged with and charges, and the charge density is , ignoring the edge effect, then according to Gauss's theorem:

[0084]

[0085] The electric field between the two plates is:

[0086]

[0087] The voltage between the two plates is:

[0088]

[0089] Substituting the voltage into the capacitance definition formula, the capacitance of the parallel plate capacitor is obtained as:

[0090]

[0091] Among them, is the relative permittivity of the medium between the two parallel metal plates, is the charge on the parallel metal plate, is the vacuum permittivity, is the electric charge quantity, is the electric field between the two parallel metal plates, is the voltage between the two parallel metal plates, is the capacitance between the two parallel metal plates.

[0092] Understandably, different settings of the first capacitor, the second capacitor, and the third capacitor may result in different isolation degrees between the chip ports. Therefore, when packaging the chip packaging structure, the isolation degree required to be achieved by the chip packaging structure can be determined first, and then the corresponding first capacitor, second capacitor, and third capacitor can be determined according to the isolation degree between the chip ports. Finally, the first length, the second length, the first height, and the second height can be determined according to the capacitance calculation formula, the first capacitor, the second capacitor, and the third capacitor.

[0093] One or more of the first capacitor between the signal line and the shielding cover, the second capacitor between the shielding line and the signal line, and the third capacitor between the signal line and the substrate here are used to adjust the isolation degree of the chip packaging structure.

[0094] In the above implementation process, by adding a shielding line in the chip package and setting a shielding cover above the chip, the inner cavity of the signal line and the shielding cover can be regarded as two substrates of a parallel capacitor, and the signal line and the shielding line can also be regarded as two substrates of a parallel capacitor. By adjusting the first capacitor between the signal line and the shielding cover, the second capacitor between the shielding line and the signal line, and the third capacitor between the signal line and the substrate, the isolation degree between the ports can be adjusted. Compared with the existing method of increasing the height of the shielding cover to improve the isolation degree, there is no need to increase the size of the chip packaging structure, meeting the requirements of chip miniaturization. That is, the isolation degree between the chip ports can be improved without increasing the size of the chip packaging structure.

[0095] In a possible implementation manner, step S201 includes: determining the first capacitor, the second capacitor, and the third capacitor according to the target isolation degree of the chip packaging structure; determining the first length, the first height, the second length, and the second height according to the first capacitor, the second capacitor, and the third capacitor.

[0096] Among them, the target isolation degree refers to the isolation degree that the chip packaging structure needs to achieve, and this target isolation degree can be set in advance according to the specific usage scenario and requirements of the chip packaging structure.

[0097] Optionally, corresponding first capacitor, second capacitor, and third capacitor can be set for each target isolation degree. After determining the target isolation degree, the corresponding first capacitor, second capacitor, and third capacitor can be matched; alternatively, a calculation formula between the target isolation degree and the first capacitor, the second capacitor, and the third capacitor can be established. After determining the target isolation degree, the first capacitor, the second capacitor, and the third capacitor can be calculated through this calculation formula; a preset model can also be set, and the target isolation degree is input into the preset model to output the corresponding first capacitor, second capacitor, and third capacitor. The acquisition method of the first capacitor, the second capacitor, and the third capacitor can be selected according to the actual situation.

[0098] It should be understood that since the capacitance calculation formula is: (wherein, is the capacitance of two parallel metal plates, is the relative area of two parallel metal plates, is the distance between two parallel metal plates, is the relative permittivity of the medium between two parallel metal plates, is the permittivity of vacuum), then after determining the first capacitance, the second capacitance, and the third capacitance, the first capacitance calculation formula, the second capacitance calculation formula, and the third capacitance calculation formula can be established respectively. By solving the formula group formed by the first capacitance calculation formula, the second capacitance calculation formula, and the third capacitance calculation formula, the first length, the first height, the second length, and the second height can be obtained respectively.

[0099] In one embodiment, the first length, the first height, the second length, and the second height can be determined by means of simulation.

[0100] In the above implementation process, by determining the first length and the first height of the corresponding signal line and the second length and the second height of the shield line according to the target isolation degree, the first capacitance formed by the signal line and the shield cover after bonding and the third capacitance formed by the signal line and the substrate after bonding can meet the requirements, and the second capacitance formed between the shield line and the signal line after bonding can meet the requirements, thereby improving the isolation degree between the chip ports of the chip package structure.

[0101] In one possible implementation manner, determining the first length, the first height, the second length, and the second height according to the first capacitance, the second capacitance, and the third capacitance includes: based on the bonding process and material type of the signal line, calculating a plurality of first reference capacitances and a plurality of second reference capacitances according to a plurality of preset first lengths and a plurality of preset first heights; determining that the preset first lengths and preset first heights corresponding to the first reference capacitances that meet the first capacitance range and the second reference capacitances that meet the second capacitance range are the first length and the first height respectively; based on the bonding process and material type of the shield line, calculating a plurality of third reference capacitances according to a plurality of preset second lengths and a plurality of preset second heights; determining that the preset second lengths and preset second heights corresponding to the third reference capacitances that meet the third capacitance range are the second length and the second height respectively.

[0102] The material type of the signal line here may include metal conductors (such as copper, aluminum, gold, silver, etc.), non-metal conductors (such as optical fibers, cables, etc.), and the material type of the signal line can be selected according to the actual situation.

[0103] The material type of the shield line may include metal conductors (such as copper, aluminum, gold, silver, etc.), non-metal conductors (such as optical fibers, cables, etc.), and the material type of the shield line can be selected according to the actual situation.

[0104] The above-mentioned preset first length refers to the settable length of the signal line set in advance, and there can be multiple such preset first lengths; the preset first height refers to the settable height of the signal line set in advance, and there can be multiple such preset first heights. The preset second length refers to the settable length of the shielding line set in advance, and there can be multiple such preset second lengths; the preset second height refers to the settable height of the shielding line set in advance, and there can be multiple such preset second heights.

[0105] Understandably, before packaging the chip, multiple preset first lengths, preset first heights, preset second lengths, and preset second heights can be set for the signal line and the shielding line first. Then, the multiple preset first lengths and preset first heights are arranged and combined, and the first reference capacitance and the third reference capacitance obtained for each combination are calculated respectively. Similarly, the multiple preset second lengths and preset second heights are arranged and combined, and the second reference capacitance obtained for each combination is calculated respectively.

[0106] Match the first reference capacitance that meets the first capacitance requirement, and determine the preset first length and preset first height used to calculate the first reference capacitance; match the third reference capacitance that meets the third capacitance requirement, and determine the preset first length and preset first height used to calculate the third reference capacitance; use the preset first length and preset first height for calculating the first reference capacitance that meets the first capacitance requirement and the third reference capacitance that meets the third capacitance requirement as the first length and first height of the signal line to be bonded.

[0107] Match the second reference capacitance that meets the second capacitance requirement, and determine the preset second length and preset second height used to calculate the second reference capacitance; use the preset second length and preset second height for calculating the second reference capacitance that meets the second capacitance requirement as the second length and second height of the shielding line to be bonded.

[0108] The above-mentioned first capacitance range refers to the difference range from the first capacitance, the second capacitance range refers to the difference range from the second capacitance, and the third capacitance range refers to the difference range from the third capacitance.

[0109] Understandably, in the actual calculation process, the first reference capacitance obtained according to the preset first length and preset first height may not be exactly equal to the first capacitance. Under normal circumstances, a certain error is allowed between the first reference capacitance and the first capacitance, and the first capacitance range is the range that allows an error between the first reference capacitance and the first capacitance. Similarly, the third reference capacitance obtained according to the preset first length and preset first height may not be exactly equal to the third capacitance. Under normal circumstances, a certain error is allowed between the third reference capacitance and the third capacitance, and the third capacitance range is the range that allows an error between the third reference capacitance and the third capacitance. The second reference capacitance obtained according to the preset second length and preset second height may not be exactly equal to the second capacitance. Under normal circumstances, a certain error is allowed between the second reference capacitance and the second capacitance, and the second capacitance range is the range that allows an error between the second reference capacitance and the second capacitance.

[0110] In the above implementation process, by determining that the preset first length and preset first height corresponding to the first reference capacitance that satisfies the first capacitance range and the second reference capacitance that satisfies the second capacitance range are the first length and the first height respectively, and determining that the preset second length and preset second height corresponding to the third reference capacitance that satisfies the third capacitance range are the second length and the second height respectively, the first capacitance formed by the signal line and the shielding cover, the third capacitance formed by the signal line and the substrate, and the second capacitance formed by the signal line and the shielding wire can meet the target isolation requirement, thereby improving the inter-port isolation of the chip package structure.

[0111] In a possible implementation, the isolation of the chip package structure is improved by reducing the first capacitance and / or increasing the second capacitance.

[0112] Among them, the first capacitance is configured to be adjusted by adjusting the relative area between the signal line and the shielding cover, and the second capacitance is configured to be adjusted by adjusting the relative area between the signal line and the shielding wire.

[0113] Exemplarily, as Figure 1 shown, inside the shielding cover, the capacitance is composed of the third capacitance between the signal line and the substrate surface, the second capacitance between the signal line and the shielding wire, and the first capacitance between the signal line and the shielding cover.

[0114] According to the impedance formula, the larger the capacitance on the coupling path, the smaller the path impedance and the more serious the energy coupling. Therefore, to reduce the energy coupling between signal ports, it is necessary to reduce the first capacitance and increase the third capacitance and the second capacitance.

[0115] Among them, the impedance formula can be expressed as:

[0116]

[0117] Among them, is the impedance between two parallel metal plates, is the capacitance between two parallel metal plates, is the angular frequency, is the imaginary unit.

[0118] Understandably, in practical applications, the relative area between the signal line and the shielding cover, the relative area between the signal line and the substrate, and the relative area between the signal line and the shielding wire can be adjusted by controlling the length of the signal line.

[0119] The distance between the signal line and the shielding cover, the distance between the signal line and the substrate, and the distance between the signal line and the shielding wire can be adjusted by controlling the arc height of the signal line.

[0120] Similarly, the relative area between the signal line and the shielding wire can be adjusted by controlling the length of the shielding wire. The distance between the signal line and the shielding cover can be adjusted by controlling the arc height of the shielding wire.

[0121] It should be understood that the second capacitance is the capacitance between the signal line and the shielding wire. In order to make the signal return to ground nearby and reduce the radiation into space, the value of the second capacitance should be increased; the first capacitance is the capacitance on the spatial coupling path of the signal port. In order to increase the impedance on the coupling path and reduce the energy coupling between ports, the value of the first capacitance should be reduced.

[0122] In the above implementation process, when packaging the chip, by reducing the first capacitance, the impedance on the coupling path can be increased, the energy coupling between ports can be reduced, thereby improving the isolation between ports, avoiding chip self-oscillation, and improving the security and stability of the chip. By increasing or increasing the second capacitance, the signal can return to ground nearby, reducing the radiation into space, thereby improving the isolation between ports, avoiding chip self-oscillation, and improving the security and stability of the chip.

[0123] In a possible implementation manner, the signal line is bonded to the chip and the substrate according to the first length and the first height, and the shielding wire is bonded to the chip and the substrate according to the second length and the second height, including: bonding the signal line to the chip and the substrate according to the first length and the first height and by means of reverse bonding; and / or bonding the shielding wire to the chip and the substrate according to the second length and the second height and by means of reverse bonding.

[0124] The reverse bonding method here refers to a special bonding technique used in the wire bonding process. In this technique, the bonding wire (such as gold wire, aluminum wire, or copper wire) is not bonded in the conventional forward order. Instead, in certain specific situations, such as chip stacking, low arc height requirements, etc., it is bonded in a reverse bonding order or angle. This technique can solve the limitations of traditional bonding methods in some special packaging structures and improve the flexibility and reliability of bonding.

[0125] Exemplarily, bonding by the reverse bonding method can be achieved through the following steps: Pretreat the chip, such as cleaning, drying, etc., to ensure the bonding quality. Set appropriate bonding parameters according to the chip type, packaging structure, and bonding requirements, such as bonding force, bonding temperature, bonding time, etc. Perform the bonding operation according to the predetermined reverse bonding order and angle.

[0126] It should be understood that in the wire bonding technology, the reverse bonding method refers to the bonding method where the wire arc direction is from the bracket to the chip. Compared with the traditional forward bonding (the wire arc direction is from the chip to the bracket), the reverse bonding method has a lower arc height. This is mainly because the reverse bonding method can better control the shape and position of the bonding wire, enabling it to cross the space between the chip and the bracket in a flatter and lower manner.

[0127] In the above implementation process, by bonding the signal wire and the shield wire using the reverse bonding method, the signal wire and the shield wire can have a lower arc height, reducing the occupied area of the signal wire and the shield wire, and thus reducing the volume of the chip packaging structure.

[0128] In one possible implementation, the method further includes: encapsulating the inside of the shield cover.

[0129] Optionally, the encapsulation method inside the shield cover can be injection molding, insert molding, secondary molding, etc., and the encapsulation method inside the shield cover can be selected according to the actual situation.

[0130] It can be understood that the welding positions of the signal wire and the shield wire may affect the values of the relative areas and distances used to form the first capacitor, the second capacitor, and the third capacitor, and thus affect the values of the first capacitor, the second capacitor, and the third capacitor. By encapsulating the inside of the shield cover, the position of the leads can be prevented from being affected by impacts or fluctuations, improving the stability of the signal wire and the shield wire.

[0131] In the chip packaging structure proposed in the embodiments of the present invention, structurally, there is no need to change the packaging outer dimensions. In addition, there is no need to reduce the layout area and size inside the shield cover, which helps the design of product miniaturization while improving the deli between ports.

[0132] In terms of the encapsulation method, compared with the prior art solution of reducing the coupling capacitance, increasing the impedance of the coupling path, and increasing the isolation of the ports by changing the height of the shielding cover, the chip encapsulation method proposed in the embodiments of the present invention reduces the coupling capacitance by adding shielding signal lines, thereby improving the isolation of the ports; at the same time, in the embodiments of the present invention, RDL is not required, which can save costs and improve performance.

[0133] To further illustrate the effects of the present invention, the following uses an embodiment to illustrate the embodiments of the present invention:

[0134] Exemplarily, if the chip package structure is: the substrate uses a 0.2 mm thick copper foil, the external dimensions of the shielding cover are 3.2 mm * 1.8 mm * 0.6 mm, the wall thickness is 0.1 mm, the external dimensions of the chip are 1 mm * 1.5 mm * 0.1 mm, the material is gallium arsenide, and the chip is centered and mounted relative to the shielding cover; the input and output signal pins of the chip are interconnected with the substrate through signal lines to achieve signal transmission, and the ground pins of the chip are interconnected with the substrate through shielded lines to achieve grounding.

[0135] Then the prior art solution is: by increasing the height of the shielding cover, reducing the capacitance between the signal line and the shielding cover, and improving the isolation between the chip ports. Here, the external dimensions of the shielding cover can be set to 3.2 mm * 1.8 mm * 1.1 mm. Compared with the shielding cover with external dimensions of 3.2 mm * 1.8 mm * 0.6 mm, the simulation results of the isolation improvement between the ports are as Figure 3 shown by the solid line, and the isolation is improved by about 5 dB in the entire frequency band.

[0136] The technical solution in the embodiments of the present invention, without changing the package size, reduces the relative area between the signal line and the shielding cover by adding a shielding ground wire, thereby reducing the capacitance and reducing the coupling between the signal ports; increasing the relative area between the signal line and the shielded wire, thereby increasing the capacitance and increasing the coupling between the signal port and the ground. Compared with the isolation improvement simulation results of the non-shielding ground wire with the same shielding cover size, as Figure 3 shown by the dotted line, the isolation is improved by about 11 dB in the entire frequency band. It can be seen from the results that the present solution has a more obvious improvement effect on the isolation without changing the size of the shielding cover.

[0137] In the above implementation process, by plastic-encapsulating the inside of the shielding cover, the welding positions of the signal line and the shielded wire can be made not affected by impacts or fluctuations, improving the stability of the signal line and the shielded wire.

[0138] Based on the same inventive concept, an embodiment of the present invention further provides a chip packaging system corresponding to the chip packaging method. Since the principle of problem-solving of the system in the embodiment of the present invention is similar to that of the foregoing chip packaging method embodiment, the implementation of the system in this embodiment can refer to the description in the embodiment of the above method, and repeated parts will not be elaborated.

[0139] Please refer to Figure 4 , which is a schematic diagram of the functional modules of the chip packaging system provided by an embodiment of the present invention. Each module in the chip packaging system in this embodiment is used to execute each step in the above method embodiment. The chip packaging system includes: a processing device 301, a bonding device 302, and a packaging device 303; wherein,

[0140] The processing device 301 is used to determine the first length and the first height of the signal line, as well as the second length and the second height of the shielding line;

[0141] The bonding device 302 is used to bond the signal line to the chip and the substrate according to the first length and the first height, and bond the shielding line to the chip and the substrate according to the second length and the second height;

[0142] The packaging device 303 is used to package a shielding cover on the substrate; wherein, the chip, the signal line, and the shielding line are arranged in the shielding cover; one or more of the first capacitance between the signal line and the shielding cover, the second capacitance between the shielding line and the signal line, and the third capacitance between the signal line and the substrate are used to adjust the isolation degree of the chip packaging structure.

[0143] In a possible implementation manner, the processing device 301 is further used to: determine the first capacitance, the second capacitance, and the third capacitance according to the target isolation degree of the chip packaging structure; determine the first length, the first height, the second length, and the second height according to the first capacitance, the second capacitance, and the third capacitance.

[0144] In a possible implementation manner, the processing device 301 is specifically used to: based on the bonding process and material type of the signal line, calculate a plurality of first reference capacitances and a plurality of second reference capacitances according to a plurality of preset first lengths and a plurality of preset first heights; determine that the preset first lengths and preset first heights corresponding to the first reference capacitances that meet the first capacitance range and the second reference capacitances that meet the second capacitance range are the first length and the first height respectively; based on the bonding process and material type of the shielding line, calculate a plurality of third reference capacitances according to a plurality of preset second lengths and a plurality of preset second heights; determine that the preset second lengths and preset second heights corresponding to the third reference capacitances that meet the third capacitance range are the second length and the second height respectively.

[0145] In a possible implementation, the bonding device 302 is further configured to: bond the signal line to the chip and the substrate according to a first length and a first height, and by means of reverse bonding; and / or bond the shield line to the chip and the substrate according to a second length and a second height, and by means of reverse bonding.

[0146] In a possible implementation, the chip packaging system further includes a plastic encapsulation device for plastic encapsulating the interior of the shield cover.

[0147] In addition, an embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is run by a processor, it executes the steps of the chip packaging method described in the above method embodiment.

[0148] The computer program product of the chip packaging method provided by the embodiment of the present invention includes a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the steps of the chip packaging method described in the above method embodiment. For details, reference can be made to the above method embodiment, which will not be elaborated here.

[0149] In several embodiments provided by the present invention, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions, and operations of devices, methods, and computer program products according to multiple embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code, and the module, program segment, or part of code includes one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order from that marked in the accompanying drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0150] In addition, in each embodiment of the present invention, the functional modules can be integrated together to form an independent part, or each module can exist alone, or two or more modules can be integrated to form an independent part.

[0151] If the above-mentioned functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs that can store program codes. It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, the elements defined by the statement "comprising..." do not exclude the presence of additional identical elements in the process, method, article or device comprising the said elements.

[0152] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention. It should be noted that similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0153] The above is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of changes or replacements, which should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A chip packaging method, characterized in that, Applied to a chip packaging structure, the method includes: Determine a first length and a first height of a signal line, and a second length and a second height of a shielding line; Bond the signal line to the chip and the substrate according to the first length and the first height, and bond the shielding line to the chip and the substrate according to the second length and the second height; Encapsulate a shielding cover on the substrate; wherein, the chip, the signal line and the shielding line are disposed in the shielding cover; one or more of a first capacitance between the signal line and the shielding cover, a second capacitance between the shielding line and the signal line, and a third capacitance between the signal line and the substrate are used to adjust the isolation degree of the chip packaging structure; The determining the first length and the first height of the signal line, and the second length and the second height of the shielding line includes: Determine the first capacitance, the second capacitance and the third capacitance according to a target isolation degree of the chip packaging structure; Determine the first length, the first height, the second length and the second height according to the first capacitance, the second capacitance and the third capacitance.

2. The method according to claim 1, wherein The determining the first length, the first height, the second length and the second height according to the first capacitance, the second capacitance and the third capacitance includes: Based on the bonding process and material type of the signal line, calculate a plurality of first reference capacitances and a plurality of second reference capacitances according to a plurality of preset first lengths and a plurality of preset first heights; Determine that the preset first length and the preset first height corresponding to the first reference capacitance satisfying the first capacitance range and the second reference capacitance satisfying the second capacitance range are the first length and the first height respectively; Based on the bonding process and material type of the shielding line, calculate a plurality of third reference capacitances according to a plurality of preset second lengths and a plurality of preset second heights; Determine that the preset second length and the preset second height corresponding to the third reference capacitance satisfying the third capacitance range are the second length and the second height respectively.

3. The method according to claim 1, wherein Improve the isolation degree of the chip packaging structure by reducing the first capacitance and / or increasing the second capacitance; Wherein, the first capacitance is configured to be adjusted by adjusting the relative area between the signal line and the shielding cover, and the second capacitance is configured to be adjusted by adjusting the relative area between the signal line and the shielding line.

4. The method according to any one of claims 1 to 3, characterized in that The bonding the signal line to the chip and the substrate according to the first length and the first height, and bonding the shielding line to the chip and the substrate according to the second length and the second height includes: Bond the signal line to the chip and the substrate according to the first length and the first height, and in a reverse bonding manner; and / or Bond the shielding line to the chip and the substrate according to the second length and the second height, and in a reverse bonding manner.

5. The method according to any one of claims 1 to 3, characterized in that The method further includes: Encapsulate the interior of the shielding cover.

6. A chip packaging structure, characterized in that, Includes: A substrate, a chip, a shielding cover, a signal line and a shielding line; The chip is mounted on the substrate; The signal line and the shield line are connected to the chip and the substrate; The shield cover is mounted on the substrate, and the chip, the signal line, and the shield line are disposed inside the shield cover; Wherein, one or more of a first capacitor between the signal line and the shield cover, a second capacitor between the shield line and the signal line, and a third capacitor between the signal line and the substrate are used to adjust the isolation degree of the chip packaging structure; The first capacitor, the second capacitor, and the third capacitor are determined according to the target isolation degree of the chip packaging structure; the first capacitor, the second capacitor, and the third capacitor are used to determine a first length and a first height of the signal line, and a second length and a second height of the shield line.

7. The structure according to claim 6, wherein, A first bonding point of the signal line on the substrate and a second bonding point of the shield line on the substrate are disposed within a preset range from the chip; and / or A distance between the first bonding point and the second bonding point is set within a preset pitch range.

8. The structure according to claim 6, characterized in that, The chip is centrally disposed in the shield cover; Wherein, the chip transmits signals to the substrate through the signal line.

9. A chip packaging system, characterized in that, Comprising: A processing device, a bonding device, and a packaging device; The processing device is used to determine a first length and a first height of the signal line, and a second length and a second height of the shield line; The bonding device is used to bond the signal line to the chip and the substrate according to the first length and the first height, and bond the shield line to the chip and the substrate according to the second length and the second height; The packaging device is used to package the shield cover on the substrate; wherein, the chip, the signal line, and the shield line are disposed in the shield cover; one or more of a first capacitor between the signal line and the shield cover, a second capacitor between the shield line and the signal line, and a third capacitor between the signal line and the substrate are used to adjust the isolation degree of the chip packaging structure; The processing device is further used to determine the first capacitor, the second capacitor, and the third capacitor according to the target isolation degree of the chip packaging structure; determine the first length, the first height, the second length, and the second height according to the first capacitor, the second capacitor, and the third capacitor.

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