Method for monitoring performance of semiconductor device, test structure and test system

Abstract

The invention relates to a method for monitoring the performance of a semiconductor device, in particular to a method, a test structure and a test system for monitoring the performance of the semiconductor device, which comprises the following steps: forming at least two test units comprising semiconductor structures on a silicon wafer, comprising at least one first test unit with a first structure cluster and at least one second test unit with a second structure; performing a laser annealing process on the silicon wafer, and testing electrical parameters of the second structure; and evaluating the influence of the laser annealing process on the performance of the second structure based on the electrical parameters of the second structure measured under different first structure densities. According to the invention, the influence of the laser annealing process on the performance of semiconductor devices with different materials and different densities is evaluated by measuring the electrical parameters of the second structure corresponding to different first structure densities after laser annealing; and by improving the semiconductor structure design and laser annealing process conditions, the performance and yield of the semiconductor device are improved, and the production cost is reduced.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and in particular relates to a method, test structure and test system for monitoring the performance of semiconductor devices. Background Art

[0002] In semiconductor device manufacturing, laser beams can be used to repair implanted lattice damage and activate impurity atoms. In nano-CMOS manufacturing, laser annealing is often used for implantation annealing in source / drain extension and contact regions to achieve ultra-shallow junctions and low resistance. However, due to the varying materials and structures of semiconductor structures grown on different regions of the silicon wafer surface, laser annealing can easily cause temperature variations in different regions, impacting device performance. Summary of the Invention

[0003] This application evaluates the impact of laser annealing on the performance of semiconductor devices of different materials and densities by measuring the electrical parameters of the second structure corresponding to different first structure densities after laser annealing; the aim is to improve the performance and yield of semiconductor devices and reduce production costs by improving semiconductor structure design and laser annealing process conditions.

[0004] Other purposes and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0005] To achieve one or more of the above objectives or other objectives, the present invention provides a method, test structure and test system for monitoring the performance of semiconductor devices.

[0006] In a first aspect, this embodiment provides a method for monitoring the performance of a semiconductor device, comprising: At least two types of test units containing semiconductor structures are formed on a silicon wafer, including at least one first test unit having a first structural cluster and at least one second test unit having a second structure; wherein the area ratio of the first structural cluster in the first test unit is used to characterize the first structural density. The silicon wafer is subjected to laser annealing, and the electrical parameters of the second structure are tested. The impact of laser annealing on the performance of the second structure is evaluated based on the electrical parameters of the second structure measured at different densities of the first structure.

[0007] In some of these embodiments, the first structural cluster is at least one of an active region cluster and a polycrystalline silicon cluster; The second structure is at least one of an active region, polysilicon, or a MOSFET.

[0008] In some embodiments, multiple first structures are centrally distributed within the first test unit, forming a cluster of first structures; When there are multiple configurations of the first test unit, the first structure cluster of each first test unit is different.

[0009] In some embodiments, when multiple second test units are provided, the second structure of each second test unit is different; There are multiple second structures in each of the second test units, and the multiple second structures are clustered and distributed relative to the first structure in different forms; The different forms include at least one of the following: The doping type, size, setting direction, and setting direction or distance of the second structure relative to the first structure cluster.

[0010] In some embodiments, the electrical parameters of the second structure are tested, including: Test the resistance value of the second structure; and / or Test the saturation current, saturation threshold voltage, or shutdown current of the second structure.

[0011] In some embodiments, evaluating the impact of laser annealing on the performance of the second structure based on the electrical parameters of the second structure measured at different first structure densities includes: A relationship curve between different densities of the first structure and the electrical parameters of the second structure is drawn according to the measured electrical parameters, and a required laser annealing process window is determined according to the relationship curve.

[0012] In some embodiments, evaluating the impact of laser annealing on the performance of the second structure based on the electrical parameters of the second structure measured at different first structure densities includes: Acquiring a plurality of electrical parameters of the second structure to obtain an electrical parameter set; Based on the set of electrical parameters corresponding to different first structure densities, multiple relationship curves between the first structure density and the electrical parameters of the second structure are plotted, and the required laser annealing process window is determined according to the multiple relationship curves.

[0013] In some embodiments, determining the desired laser annealing process window based on a plurality of said relationship curves includes: The fluctuation range of the electrical parameters of the second structure is determined based on the relationship curve, and it is determined whether the fluctuation range is within a preset threshold. If the fluctuation range is within the preset threshold, the density of the first structure corresponding to the relationship curve is the required laser annealing process window.

[0014] Secondly, this embodiment provides a test structure for monitoring the performance of semiconductor devices, used to implement the method for monitoring the performance of semiconductor devices as described in any of the first aspects above, comprising: Silicon wafers; At least two types of test units are grown on the silicon wafer, including at least one first test unit having a first structural cluster and at least one second test unit having a second structure; The test circuit is electrically connected to the second structure and is used to measure the electrical parameters of the second structure.

[0015] In some embodiments, multiple first structures are centrally distributed within the first test unit, forming a cluster of first structures; Each of the second test units has multiple second structures, and the multiple second structures are distributed relative to the first structure cluster in different distribution patterns. Among them, different morphologies include at least one of the following: the doping type, size, setting direction, and direction or distance relative to the first structure cluster of the second structure.

[0016] In some of these embodiments, the first structural cluster is an active region cluster or a polysilicon cluster; The second structure is an active region, polysilicon, or MOSFET, and the test circuit is electrically connected to the second structure. Alternatively, the second structure is a MOS transistor, and the test circuit is electrically connected to the gate, source, drain and base of the MOS transistor respectively.

[0017] Thirdly, this embodiment provides a test system for monitoring the impact of laser annealing on the performance of semiconductor devices, comprising multiple test structures as described in the second aspect, wherein the area ratio of the first structure cluster in the first test unit is used to characterize the first structure density, and the first test units in the multiple test structures correspond to different first structure densities.

[0018] Compared with the prior art, the beneficial effects of the present invention mainly include: 1. This application provides a method for monitoring semiconductor device performance. The method comprises forming a first test cell having at least one cluster of first structures and at least one second test cell having a second structure on a silicon wafer. After the silicon wafer is subjected to a laser annealing process, the electrical parameters of the second structure are measured under conditions of varying first structure densities. This method is used to evaluate the impact of varying first structure densities of the first test cells on the performance of the second structure during the laser annealing process. 2. This application provides a test structure for monitoring the performance of semiconductor devices. The design includes a silicon wafer, a first test unit grown on the silicon wafer including at least one first structure cluster and at least one second test unit having a second structure, and a test circuit electrically connected to the second structure. It can achieve specific quantitative monitoring of the impact of different materials and densities on the performance of devices by measuring the electrical parameters of the second structure. 3. This application also designs a test system for monitoring the impact of laser annealing on the performance of semiconductor devices. By monitoring the impact of laser annealing process on the performance of semiconductor devices of different materials and densities, the semiconductor structure design and laser annealing process conditions can be optimized to improve the performance and yield of semiconductor devices and reduce production costs.

[0019] In order to make the above and other objects, features and advantages of the present invention more clearly understood, preferred embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 A schematic flow chart of a method for monitoring semiconductor device performance provided in Example 1 of the present application.

[0022] Figure 2 A schematic diagram of a test structure for monitoring semiconductor device performance provided in Example 1 of the present application Figure 1 .

[0023] Figure 3 Schematic diagram of a test structure for monitoring semiconductor device performance in a polysilicon lateral arrangement process provided in Example 1 of the present application Figure 2 .

[0024] Figure 4 Schematic diagram of a test structure for monitoring semiconductor device performance in a polysilicon vertical arrangement process provided in Example 1 of the present application Figure 3 .

[0025] Figure 5 A relationship curve diagram of an application scenario provided in Example 1 of the present application.

[0026] Figure 6 A relationship curve diagram of another application scenario provided in Example 1 of the present application.

[0027] Figure 7A schematic diagram of a test structure for monitoring semiconductor device performance provided in Example 2 of the present application. DETAILED DESCRIPTION

[0028] The foregoing and other technical aspects, features, and functions of the present invention are clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. Directional terms such as up, down, left, right, front, and back, used in the following embodiments, are intended solely to refer to the directions in the accompanying drawings. Therefore, the directional terms used are for illustrative purposes only and are not intended to limit the present invention.

[0029] This application evaluates the impact of the laser annealing process on the performance of semiconductor devices of different materials and densities by measuring the electrical parameters of the second structure corresponding to different first structure densities after laser annealing; and by improving the semiconductor structure design and laser annealing process conditions, improves the performance and yield of semiconductor devices and reduces production costs.

[0030] The following detailed description of the various embodiments of the present application is provided in conjunction with the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present application to facilitate a better understanding of the present application. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0031] The laser annealing process in this application is performed in the front-end of chip manufacturing. The semiconductor structure on the silicon wafer usually only includes AA (active region), poly (polycrystalline silicon), and MOS devices. However, the second structural electrical parameters measured in this application are performed after all structures on the chip have been grown. In order to facilitate the description of the technical solution, the semiconductor substrate (silicon wafer) and the various metal layers, metal interconnects, pads, etc. on the substrate are not shown in the embodiments of this application.

[0032] Example 1 Figure 1 A method for monitoring semiconductor device performance provided in Example 1 of the present application is shown.

[0033] like Figure 1 As shown, a method for monitoring the performance of a semiconductor device includes: At least two types of test units containing semiconductor structures are formed on a silicon wafer, including at least one first test unit having a first structure cluster and at least one second test unit having a second structure. The area ratio of the first structure cluster in the first test unit is used to characterize the density of the first structure. Performing a laser annealing process on the silicon wafer to test electrical parameters of the second structure; The effect of laser annealing process on the performance of the second structure is evaluated based on the electrical parameters of the second structure measured under different first structure densities.

[0034] By measuring the electrical parameters of the second structure, the impact between different semiconductor structures on the silicon wafer during the laser annealing process is quantitatively evaluated, that is, the impact of the first test unit at the first structure density on the second structure in the second test unit. This can be used to optimize semiconductor structure design and laser annealing process conditions, improve the performance and yield of semiconductor devices, and reduce production costs.

[0035] In some specific embodiments, the first structure cluster is at least one of an active area cluster and a polysilicon cluster; the second structure is at least one of an active area, polysilicon, or a MOS transistor. Generally, the impact of MOS devices on themselves or other devices is not considered, and therefore, the first test unit does not include MOS devices. This application does not limit the specific type of semiconductor devices. The first structure cluster in the first test unit and the second structure in the second test unit can be designed based on the needs of specific application scenarios.

[0036] In some specific embodiments, multiple first structures are concentrated in the first test unit to form a first structure cluster; the first test unit has a certain semiconductor structure density, and the semiconductor structures in the first test unit are usually distributed relatively concentratedly and can be regarded as a cluster, and the density of this cluster can be changed according to test requirements, and the density of the cluster serves as a variable of the test.

[0037] In some specific embodiments, when multiple first test units are provided, the first structure clusters of each first test unit are different; similarly, when multiple second test units are provided, the second structure clusters of each second test unit are different. The differences mentioned here can be differences caused by differences in any variable, including the material, size, arrangement direction, distance, density, etc. of the semiconductor structure.

[0038] In some specific embodiments, there are multiple second structures in each second test unit, and the multiple second structures are distributed in different forms relative to the first structure cluster; specifically, the second structures in the second test unit are scattered around the first test unit in different distribution forms, and the distribution form of the second structure, such as the doping type, size, setting direction, direction or distance relative to the first structure cluster, etc. of the second structure can all be used as multiple control variables.

[0039] In practical applications, when testing the impact of the first test unit on the second test unit, the test can involve testing the influence of AA / poly clusters of different densities on one or more AA / poly / MOS devices of a fixed form factor, i.e., a one-to-one or one-to-many relationship. Alternatively, it can involve testing the influence of AA / poly clusters of different densities on AA / poly / MOS devices with different form factor distributions. Simultaneously, it can also involve the influence of AA and poly clusters of different densities on AA / poly / MOS devices of a fixed form factor, i.e., a many-to-one, many-to-many, or simultaneous influence of AA and poly clusters of different densities on AA / poly / MOS devices with different form factor distributions. This application does not impose specific limitations and can be designed based on specific application scenarios.

[0040] In some specific embodiments, a laser annealing process is performed on the silicon wafer having the first test unit and the second test unit to test the electrical parameters of the second structure; wherein, the electrical parameters of the second structure include: testing the resistance value of the second structure; and / or testing the saturation current, saturation threshold voltage, or turn-off current of the second structure. This application does not specifically limit the electrical parameters of the second structure, and can be designed according to specific application scenarios; for example, when measuring the electrical parameters of the second structure based on different first structure densities: 1) If the first structure density is AA density (active area density) and the second structure is poly (polysilicon), then the resistance can be measured for poly; 2) If the first structure density is Poly density (density of polysilicon) and the second structure is AA, then the resistance can be measured for AA; 3) If the first structure density is AA density and the second structure is a MOS device, the resistance of the MOS device can be measured, and other electrical parameters of the MOS can also be measured (connect the four terminals G / S / D / B of the MOS tube, and measure the saturation current, saturation threshold voltage, or off-state current); 4) If the first structure density is Poly density and the second structure is a MOS device, the resistance of the MOS device can be measured, and other electrical parameters of the MOS can also be measured (connecting the four terminals G / S / D / B of the MOS tube, saturation current, saturation threshold voltage or off-state current).

[0041] In some specific embodiments, evaluating the impact of a laser annealing process on the performance of the second structure based on electrical parameters of the second structure measured at different first structure densities includes: plotting a relationship curve between the electrical parameters of the second structure at different first structure densities based on the measured electrical parameters, and determining a desired laser annealing process window based on the relationship curve. A first test cell has a certain first structure density, while the second structures in the second test cell are relatively dispersed, being scattered around the first test cell. The distribution morphology of the semiconductor structures (device structure doping type, size, distance, arrangement orientation, etc.) can serve as multiple control variables. After measuring the electrical parameters of the second structure at these different control variables at a certain first structure density and plotting the relationship curve, the design adjustable range of the control variable at the current first structure density can be determined based on the relationship curve.

[0042] The first test unit is a cluster of semiconductor structures, and the density of the first structure of this cluster can be changed according to test requirements. The density of the cluster is used as a test variable. Therefore, in some specific applications, based on the electrical parameters of the second structure measured at different first structure densities, the impact of the laser annealing process on the performance of the second structure is evaluated, including: Obtain the electrical parameters of multiple second structures to obtain a set of electrical parameters; Based on electrical parameter sets corresponding to different first structure densities, multiple relationship curves between the first structure density and the electrical parameters of the second structure are drawn, and the required laser annealing process window is determined according to the multiple relationship curves.

[0043] Specifically, the required laser annealing process window is determined based on the multiple relationship curves, including: determining the fluctuation range of the electrical parameters of the second structure based on the relationship curve, and judging whether the fluctuation range is within a preset threshold; if the fluctuation range is within the preset threshold, then the first structure density corresponding to the relationship curve is the required laser annealing process window.

[0044] Figure 2 The figure shows a test structure for monitoring the performance of a semiconductor device provided in Example 1 of the present application. Figure 1 This test structure can be used to implement the above-mentioned method for monitoring the performance of semiconductor devices.

[0045] like Figure 2 As shown, a test structure for monitoring the performance of a semiconductor device includes: silicon wafers ( Figure 2 (Not shown in the middle) At least two test cells, grown on a silicon wafer, including at least one cluster with a first structure ( Figure 2 a first test unit in the AA cluster) and at least one having a second structure ( Figure 2The second test unit of poly); Test circuit ( Figure 2 Not shown), and the second structure ( Figure 2 The poly) electrical connection is used to measure the electrical parameters of the second structure.

[0046] The design of this test structure allows for the quantitative exploration of the impact of the first test unit on the second test unit during the laser annealing process by using the measured electrical parameters after the silicon wafer has undergone laser annealing. It is simple, convenient, and effective, and the variables can be designed based on different application scenarios.

[0047] In this embodiment, if Figure 2 The test structure shown is used to monitor the effect of a large area of ​​AA (active region) on poly (polycrystalline silicon). Figure 2 In the test, the first test unit is composed of multiple active areas, which are concentrated in the first test unit to form a first structure cluster, namely the active area cluster. The outer frame area of ​​the entire active area cluster is 200 microns * 200 microns, and the area of ​​the inner frame part is 25 microns * 25 microns. The first structure density is the ratio of the actual active area area in the active area cluster to the outer frame area. The second structure in the second test unit refers to poly, and there can be multiple second structures. The multiple second structures are distributed relative to the first structure cluster in different distribution forms; wherein the different forms include at least any one of the following: the doping type, size, setting direction, and setting direction or distance of the second structure relative to the first structure cluster; Figure 2 For ease of explanation and demonstration, only one poly is drawn for illustration, and the meanings of the variables indicated by space (distance relative to the first structure cluster), width (width of the second structure), and length (length of the second structure) are marked.

[0048] based on Figure 2 The test structure shown below, along with the DOE (Design of Effect) calculations performed on each variable (structural data, distribution pattern, etc.) within the test structure, are illustrated in Table 1 to obtain a test structure that meets the requirements of the test scenario. The data units for the width, length, and space columns in Table 1 are micrometers.

[0049] Table 1 Among them, implantType is the doping type, width is the width of the polysilicon, length is the length of the polysilicon, polyOrientation indicates the direction of the polysilicon (the polysilicon is arranged horizontally h or vertically v), space is the distance between the polysilicon and the active area, location is the position of the polysilicon relative to the active area, #of DOE refers to the designed number of polysilicon, and AA density is the active area density.

[0050] Figure 3 、 Figure 4 The following are schematic diagrams of a test structure for monitoring semiconductor device performance provided in Example 1 of the present application in a polysilicon lateral arrangement process. Figure 2 Schematic diagram of the vertically aligned polysilicon process. Figure 3 , Figure 3 、 Figure 4 All based on Figure 2 The test structure is a new test structure formed by different DOE designs in Table 1 above. Figure 3 、 Figure 4 They are mainly used to illustrate the poly distribution designed for different test structures. The figure does not show the connection of the metal layer, nor does it illustrate the pad and its connection.

[0051] Each polysilicon is tested separately and the measurement results are plotted into a relationship curve graph.

[0052] For example, when testing the effect of active regions AA of different densities on polycrystalline silicon with a fixed shape, the horizontal axis is set to the active region density and the vertical axis is set to the polycrystalline silicon resistance value, and a relationship curve is plotted. When testing the effect of active areas AA of different densities on polysilicon poly of different forms, the horizontal axis is set to space and the vertical axis is set to multiple relationship curves of resistance, each relationship curve corresponding to an active area density.

[0053] In the embodiment of the present application, the first structure cluster is an active area cluster or a polysilicon cluster; the second structure is an active area, polysilicon or MOS tube, and the test circuit is electrically connected to the second structure; during the test, a two-terminal method or a four-terminal method, i.e., a KLV test, is used to test the resistance value of the polysilicon. Since the measured resistance value of the polysilicon is small, the KLV test is generally used, and the resistance value measurement is more accurate.

[0054] Figure 5 、 Figure 6 These are relationship curve diagrams obtained in different application scenarios of this application.

[0055] like Figure 5The data shown illustrates the variation of resistance Rs with space under three AA density (active region structure density) conditions. The resistance Rs does not change significantly, indicating that the current process and density conditions have little impact on the surrounding poly, thus allowing for a relatively large adjustable range in the design.

[0056] like Figure 6 The figure shows the resistance Rs as a function of space under three active area density (AA) conditions. 20% has little effect on Rs, while 50% / 90% show significant changes, with 90% having the greatest impact. This indicates that under current technology, high AA density has a certain impact on surrounding polysilicon, while low AA density has a very small impact. Therefore, the design range of AA density needs to be considered during the design process, as well as the limitations on polysilicon usage within a certain distance. For example, some important devices need to be kept away from areas with high AA density to maintain performance stability. In Example 1 of this application, subsequent results, such as different relationship curves and other charts, can be used to determine whether the impact of the active area density used during laser annealing on polysilicon performance is acceptable, thereby guiding the subsequent design of active area density and semiconductor structure.

[0057] Example 2 Example 2 of the present application monitors the impact of a large area of ​​AA (active area) on the MOS tube structure.

[0058] like Figure 7 As shown, a test structure for monitoring the performance of a semiconductor device includes: silicon wafers ( Figure 7 (Not shown in the middle) At least two test cells, grown on a silicon wafer, including at least one cluster with a first structure ( Figure 7 a first test unit in the AA cluster) and at least one having a second structure ( Figure 7 The second test unit of the MOS tube in the test chamber; Test circuit ( Figure 7 Not shown), and the second structure ( Figure 7 The MOS tube in the second structure is electrically connected to the MOS tube in the second structure for measuring the electrical parameters of the second structure.

[0059] The first structure is concentrated in the first test unit, forming a first structure cluster; each second test unit has multiple second structures, which are distributed relative to the first structure cluster in different distribution patterns.

[0060] In this embodiment, if Figure 6 The test structure shown is for the effect of AA (active area) clustering on MOS devices. Figure 7In the test, the first test unit is composed of multiple active areas, which are concentrated in the first test unit to form a first structure cluster, that is, an active area cluster. The outer frame area of ​​the entire active area cluster is 200 microns * 200 microns, and the area of ​​the inner frame part is 25 microns * 25 microns. The first structure density is the ratio of the actual active area area in the active area cluster to the outer frame area. The second structure in the second test unit refers to the MOS tube, which can be provided in multiple forms. The multiple second structures are distributed relative to the first structure cluster in different distribution forms; wherein the different forms include at least any one of the following: the doping type, size, setting direction, and setting direction or distance of the second structure relative to the first structure cluster; Figure 7 For ease of illustration, only one MOS tube is drawn for illustration, and the meanings of the variables indicated by space (the distance relative to the first structure cluster), gl (the channel length of the second structure), and gw (the channel width of the second structure) are indicated.

[0061] based on Figure 7 Table 2 shows the test structure shown below. DOEs were performed on various variables (structural data, distribution morphology, etc.) to obtain the test structure required to meet the test scenario. The data in the gl, gw, and space columns in Table 1 are in micrometers.

[0062] Table 2 Where implantType is the doping type, gL is the channel length of the MOS transistor structure, gW is the channel width of the MOS transistor structure, MOS Orientation is whether the polysilicon in the MOS transistor structure is arranged horizontally (h) or vertically (v), space is the distance between the MOS transistor structure and the active area, location is the position of the MOS transistor structure relative to the active area, #of DOE refers to the number of MOS transistor structures designed, and AA density is the active area density.

[0063] In this application embodiment, the first structure cluster is an active region cluster or a polysilicon cluster; the second structure is an active region, polysilicon, or a MOSFET, and the test circuit is electrically connected to the second structure.

[0064] Specifically, the second structure of the embodiment of the present application is a MOS tube. During testing, the test circuit is electrically connected to the gate, source, drain and base of the MOS tube respectively, and the resistance of the MOS tube can be tested, and the electrical parameters of the MOS tube can also be tested.

[0065] In the second embodiment of this application, the specific data from DOE and the measured electrical parameters can be used to obtain the relationship curves for specific application scenarios. Different relationship curves and other result charts can be used to determine whether the active region density used during laser annealing has an acceptable impact on the performance of the MOS transistor structure, thereby guiding the design of the subsequent active region density and semiconductor structure.

[0066] Example 3 A test system for monitoring the effect of laser annealing on semiconductor device performance, comprising a plurality of test structures for monitoring semiconductor device performance; Specifically, at least two test units are grown on a silicon wafer, including at least one first test unit having a first structure cluster and at least one second test unit having a second structure; The test circuit is electrically connected to the second structure and is used to measure electrical parameters of the second structure.

[0067] The first structure is concentrated in the first test unit, forming a first structure cluster; each second test unit has multiple second structures, which are distributed relative to the first structure cluster in different distribution patterns.

[0068] The area ratio of the first structure cluster in the first test unit is used to represent the first structure density, and the first test units in the multiple test structures correspond to different first structure densities.

[0069] This application evaluates the impact of laser annealing on the performance of semiconductor devices of different materials and densities by measuring the electrical parameters of the second structure corresponding to different first structure densities after laser annealing; and improves the performance and yield of semiconductor devices and reduces production costs by improving semiconductor structure design and laser annealing process conditions.

[0070] The common English terms or letters used in this invention for clarity of description are for illustrative purposes only and are not limiting interpretations or specific uses. They should not be used to limit the scope of protection of this invention based on their possible Chinese translations or specific letters.

[0071] It should also be noted that in this article, relational terms such as “first” and “second” are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

Claims

1. A method for monitoring the performance of a semiconductor device, characterized in that: include: Forming at least two test units including semiconductor structures on a silicon wafer, including at least one first test unit having a first structure cluster and at least one second test unit having a second structure; wherein the area ratio of the first structure cluster in the first test unit is used to characterize the first structure density; Performing a laser annealing process on the silicon wafer to test electrical parameters of the second structure; Based on the electrical parameters of the second structure measured at different densities of the first structure, the influence of the laser annealing process on the performance of the second structure is evaluated.

2. A method for monitoring semiconductor device performance according to claim 1, characterized in that: The first structure cluster is at least one of an active area cluster and a polysilicon cluster; The second structure is at least one of an active region, polysilicon or a MOS tube.

3. A method for monitoring semiconductor device performance according to claim 1, characterized in that: A plurality of the first structures are concentratedly distributed in the first test unit to form a first structure cluster; When the first test units are provided in multiple types, the first structural clusters of each type of the first test units are different.

4. The method for monitoring semiconductor device performance according to claim 1, characterized in that: When the second test unit is provided in multiple types, the second structure of each type of the second test unit is different; There are a plurality of second structures in each of the second test units, and the plurality of second structures are clustered and distributed relative to the first structure in different forms; The different forms include at least any one of the following: the doping type, size, setting direction, and the direction or distance of the second structure relative to the first structure cluster.

5. The method for monitoring semiconductor device performance according to claim 2, characterized in that: Testing the electrical parameters of the second structure includes: testing the resistance value of the second structure; and / or The saturation current, saturation threshold voltage or off current of the second structure is tested.

6. The method for monitoring semiconductor device performance according to claim 1, characterized in that: The evaluating the influence of the laser annealing process on the performance of the second structure based on the electrical parameters of the second structure measured at different densities of the first structure includes: A relationship curve between different densities of the first structure and the electrical parameters of the second structure is drawn according to the measured electrical parameters, and a required laser annealing process window is determined according to the relationship curve.

7. A method for monitoring semiconductor device performance according to claim 4, characterized in that: The evaluating the influence of the laser annealing process on the performance of the second structure based on the electrical parameters of the second structure measured at different densities of the first structure includes: Acquire electrical parameters of a plurality of the second structures to obtain an electrical parameter set; Based on electrical parameter sets corresponding to different first structure densities, multiple relationship curves between the first structure density and the electrical parameters of the second structure are plotted, and the required laser annealing process window is determined according to the multiple relationship curves.

8. A method for monitoring semiconductor device performance according to claim 7, characterized in that: Determining the required laser annealing process window according to the plurality of relationship curves comprises: The fluctuation range of the electrical parameters of the second structure is determined according to the relationship curve, and it is judged whether the fluctuation range is within a preset threshold; if the fluctuation range is within the preset threshold, the first structure density corresponding to the relationship curve is the required laser annealing process window.

9. A test structure for monitoring the performance of a semiconductor device, used to implement a method for monitoring the performance of a semiconductor device as claimed in any one of claims 1 to 8, characterized in that: include: Silicon wafer; At least two test units, grown on the silicon wafer, including at least one first test unit having a first structure cluster and at least one second test unit having a second structure; A test circuit is electrically connected to the second structure and is used to measure electrical parameters of the second structure.

10. A test structure for monitoring semiconductor device performance according to claim 9, characterized in that: A plurality of the first structures are concentratedly distributed in the first test unit to form a first structure cluster; There are a plurality of second structures in each of the second test units, and the plurality of second structures are clustered and distributed relative to the first structure in different distribution forms; The different forms include at least any one of the following: the doping type, size, setting direction, and the direction or distance of the second structure relative to the first structure cluster.

11. A test structure for monitoring semiconductor device performance according to claim 10, characterized in that: The first structure cluster is an active region cluster or a polysilicon cluster; The second structure is an active area, polysilicon or a MOS tube, and the test circuit is electrically connected to the second structure; Alternatively, the second structure is a MOS tube, and the test circuit is electrically connected to the gate, source, drain and base of the MOS tube respectively.

12. A test system for monitoring the effect of laser annealing on semiconductor device performance, characterized in that: The method comprises a plurality of test structures as claimed in claim 9, wherein the area ratio of the first structure cluster in the first test unit is used to characterize the first structure density, and the first test units in the plurality of test structures correspond to different first structure densities.

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