Semiconductor device shallow trench isolation structure and manufacturing method thereof

Abstract

The invention provides a semiconductor device shallow trench isolation structure and a manufacturing method thereof, and the method comprises the steps: 1, providing a substrate, forming a hard mask layer with trench patterns on the substrate, forming a plurality of trenches in the substrate, and then forming a pad oxidation layer on the surface of an unshielded region of the hard mask layer; step 2, back-etching the hard mask layer; 3, after the liner oxide layer formed in the step 1 is removed, another liner oxide layer is formed on the surface of the unshielded area of the hard mask layer; and 4, depositing an oxide to fill the groove. The top corner of the formed shallow trench isolation structure in contact with the edge of the active region is not sharp any more, electric leakage of a parasitic transistor formed on the side edge of the active region can be effectively reduced, and a roll-off curve of threshold voltage is remarkably improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a shallow trench isolation structure of a semiconductor device and a manufacturing method thereof. Background Art

[0002] In the manufacturing process of semiconductor devices, after a trench for filling shallow trench isolation (STI) is formed in a substrate, the filling of the shallow trench isolation is usually completed in two steps, namely, first forming a pad oxide layer on the inner wall of the trench and the corner of the top of the trench, and then completing the oxide filling, respectively forming the edge and filling material where the STI contacts the active area (AA).

[0003] The top corner morphology of the STI and AA edge contact formed by the prior art is usually sharp, and the electric field strength at this position is high after the semiconductor device is formed, which easily leads to the double hump effect, that is, when the device does not reach the threshold voltage in the subthreshold region, leakage occurs, causing the device to turn on prematurely. The main reason for the double hump is that the top corner morphology of the STI and AA edge contact is not good, that is, the parasitic transistor at the edge of the channel is turned on, which increases the leakage of the device, and the threshold voltage Vt starts from a certain critical point on the roll-off curve. The shorter the channel, the lower the Vt. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a shallow trench isolation structure of a semiconductor device and a manufacturing method thereof, so as to solve the problem in the prior art that the top corner morphology of the STI and AA edge contact is poor, which increases the device leakage.

[0005] To achieve the above-mentioned purpose and other related purposes, the present application provides a method for manufacturing a shallow trench isolation structure of a semiconductor device, comprising:

[0006] Step 1, providing a substrate, forming a hard mask layer with a groove pattern on the substrate, forming a plurality of grooves in the substrate, and then forming a pad oxide layer on the surface of the area not masked by the hard mask layer;

[0007] Step 2, etching back the hard mask layer;

[0008] Step 3, after removing the pad oxide layer formed in step 1, another pad oxide layer is formed on the surface of the area not masked by the hard mask layer;

[0009] Step 4: Deposit oxide to fill the trench.

[0010] Preferably, the duration of the back etching in step 2 is 40s-80s.

[0011] Preferably, the etching solution used in the back etching is hot phosphoric acid.

[0012] Preferably, in step one, an in-situ steam oxidation process is used to form the liner oxide layer.

[0013] Preferably, the temperature of the in-situ steam oxidation process is 1050°C-1250°C, and the thickness of the liner oxide layer is

[0014] Preferably, in step three, the liner oxide layer is removed by wet etching with a high selectivity ratio.

[0015] Preferably, in step three, an in-situ steam oxidation process is used to form another liner oxide layer.

[0016] Preferably, the temperature of the in-situ steam oxidation process is 1050°C-1250°C, and the thickness of the other liner oxide layer is

[0017]

[0018] Preferably, the oxide deposited in step 4 is HARP.

[0019] Preferably, after implementing step 4, an etch-back process is first performed to make the thickness of the oxide between the hard mask layers reach a predetermined value, and then a wet etching process is performed to remove the hard mask layer.

[0020] The present application also provides a shallow trench isolation structure prepared according to the manufacturing method of the shallow trench isolation structure of the semiconductor device.

[0021] As described above, the shallow trench isolation structure of the semiconductor device and the manufacturing method thereof provided in the present application have the following beneficial effects: the top corner of the formed shallow trench isolation structure contacting the edge of the active area is no longer sharp, which can effectively reduce the leakage of the parasitic transistor formed on the side of the active area, and the roll-off curve of the threshold voltage is significantly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1A-Figure 1D It is a schematic diagram showing a cross-sectional structure of a device formed after various steps of forming a shallow trench isolation structure according to the prior art are completed;

[0024] Figure 1E Display as Figure 1D A magnified image of the top corner morphology of the shallow trench isolation structure contacting the edge of the active area;

[0025] Figure 1F A schematic diagram showing that the top corner of the shallow trench isolation structure in contact with the edge of the active region has a sharp morphology, resulting in the formation of a parasitic transistor region on the side of the active region;

[0026] Figure 2 A flow chart showing a method for manufacturing a shallow trench isolation structure of a semiconductor device provided by an embodiment of the present application;

[0027] Figure 3A-3D It is a schematic diagram showing a cross-sectional structure of a device formed after each step is completed in a method for manufacturing a shallow trench isolation structure of a semiconductor device provided in an embodiment of the present application;

[0028] Figure 3E and Figure 3F They respectively show the enlarged views of the top corner morphology of the trench after forming the liner oxide layer for the first time and after forming the liner oxide layer for multiple times in the method for manufacturing the shallow trench isolation structure of the semiconductor device provided by the embodiment of the present application. DETAILED DESCRIPTION

[0029] The following describes the implementation of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0030] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0031] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating directions or positional relationships, are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0032] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0033] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0034] The steps of forming a shallow trench isolation structure in the prior art include:

[0035] First, if Figure 1A As shown, a substrate 100 is provided. After a trench 101 is formed in the substrate 100 , the hard mask layer 102 is etched back.

[0036] Then, if Figure 1B As shown, a pad oxide layer 103 is formed on the surface of the unshielded area of ​​the hard mask layer 102 , which includes the inner wall of the trench 101 and the top corner surface of the trench 101 .

[0037] Then, if Figure 1C As shown, an oxide 105 is deposited to fill the trench 101 . The oxide 105 is typically a HARP (high aspect ratio process) oxide.

[0038] Then, if Figure 1D As shown, after the oxide 105 is etched back, the hard mask layer 102 is removed to form a shallow trench isolation structure 106 .

[0039] like Figure 1E As shown, the top corner of the shallow trench isolation structure 106 that contacts the edge of the active area is sharp, resulting in the formation of a ridge on the side of the active area. Figure 1F The parasitic transistor area shown in the figure causes the device leakage to increase, and the larger the proportion of the parasitic transistor area (the smaller the width of the device active area, the larger the proportion of the parasitic transistor area, Figure 1F The parasitic transistor area shown in the upper middle figure accounts for a large proportion), the shorter the channel, the lower the Vt.

[0040] In order to solve this problem, the present application provides a method for manufacturing a shallow trench isolation structure of a semiconductor device.

[0041] See also Figure 2 , which shows a flow chart of a method for manufacturing a shallow trench isolation structure of a semiconductor device provided in an embodiment of the present application.

[0042] like Figure 2 As shown, the method for manufacturing the shallow trench isolation structure of the semiconductor device comprises the following steps:

[0043] Step 1, providing a substrate, forming a hard mask layer with a groove pattern on the substrate, forming a plurality of grooves in the substrate, and then forming a pad oxide layer on the surface of the area not masked by the hard mask layer;

[0044] Step 2, etching back the hard mask layer;

[0045] Step 3, after removing the pad oxide layer formed in step 1, another pad oxide layer is formed on the surface of the area not masked by the hard mask layer;

[0046] Step 4: Deposit oxide to fill the trench.

[0047] In step one, if Figure 3A As shown, optionally, the substrate 300 is a silicon substrate, a germanium substrate, or a silicon-on-insulator substrate, etc.; or the material of the substrate 300 may also include other materials, such as III-V compounds such as gallium arsenide. Those skilled in the art can select the constituent material of the substrate 300 according to the type of device structure formed on the substrate 300, so the type of the substrate 300 should not limit the protection scope of the present invention.

[0048] As an example, a hard mask layer 302 having a trench 301 pattern is formed on the substrate 300 by photolithography and etching processes, and the material of the hard mask layer 302 includes silicon nitride.

[0049] Next, a plurality of trenches 301 are formed in the substrate 300 by an etching process using the hard mask layer 302 as a mask.

[0050] Then, a pad oxide layer 303 is formed on the surface of the unshielded area of ​​the hard mask layer 302. Exemplarily, the pad oxide layer 303 is formed by an in-situ steam oxidation (ISSG) process, the temperature of the ISSG process is 1050° C.-1250° C., and the thickness of the pad oxide layer 303 is like Figure 3E As shown, the top corner of the groove 301 is sharp.

[0051] In step 2, if Figure 3B As shown, the hard mask layer 302 is etched back. Exemplarily, the etching solution used for the back etching is hot phosphoric acid, and the duration of the back etching is 40s-80s. Repeated tests have shown that if the duration of the back etching is too short or too long, the roundness of the top corner of the groove 301 will deteriorate when the subsequent steps are performed.

[0052] In step three, if Figure 3CAs shown, the pad oxide layer 303 is removed by wet etching with a high selectivity. Then, the pad oxide layer 303 is formed again on the surface of the unshielded area of ​​the hard mask layer 302. Exemplarily, the pad oxide layer 303 is formed by an in-situ steam oxidation (ISSG) process, the temperature of the ISSG process is 1050° C.-1250° C., and the thickness of the pad oxide layer 303 is

[0053] In order to gradually change the top corner of the trench 301 from the initial sharp corner to a rounded corner, step three can be repeated, that is, after removing the liner oxide layer 303 formed last time, the liner oxide layer 303 is formed again on the surface of the unshielded area of ​​the hard mask layer 302. The process used for forming the liner oxide layer each time is the ISSG process and the temperature is 1050° C.-1250° C. The thickness of the liner oxide layer 303 formed each time is After the pad oxide layer 303 is formed for the last time, Figure 3F As shown, the top corners of the groove 301 become rounded.

[0054] In step 4, if Figure 3D As shown, an oxide 305 is deposited to fill the trench 301. To achieve a better filling effect, the oxide 305 is usually a HARP (oxide formed using a high aspect ratio process).

[0055] Next, the thickness of the oxide 305 between the hard mask layers 302 is made to reach a predetermined value through an etch-back process, and then the hard mask layer 302 is removed through a wet etching process to complete the manufacturing of the shallow trench isolation structure.

[0056] The top corner of the shallow trench isolation structure formed by the manufacturing method of the shallow trench isolation structure of the semiconductor device provided by the present application, which contacts the edge of the active area, is no longer sharp, which can effectively reduce the Figure 1F The leakage of the parasitic transistor and the roll-off curve of the threshold voltage Vt are significantly improved. Therefore, the present application effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0057] The present application also provides a shallow trench isolation structure prepared according to the manufacturing method of the shallow trench isolation structure of the above-mentioned semiconductor device. The top corner of the shallow trench isolation structure that contacts the edge of the active area is no longer sharp, which can effectively reduce the leakage of the parasitic transistor formed on the side of the active area.

[0058] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present application in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0059] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present application.

Claims

1. A method for manufacturing a shallow trench isolation structure of a semiconductor device, characterized in that: The method comprises: Step 1, providing a substrate, forming a hard mask layer with a groove pattern on the substrate, forming a plurality of grooves in the substrate, and then forming a pad oxide layer on the surface of the unshielded area of ​​the hard mask layer; Step 2, etching back the hard mask layer; Step 3, after removing the pad oxide layer formed in step 1, forming another pad oxide layer on the surface of the unshielded area of ​​the hard mask layer; Step 4: deposit oxide to fill the trench.

2. The method according to claim 1, characterized in that The duration of the back etching in step 2 is 40s-80s.

3. The method according to claim 1 or 2, characterized in that: The etching solution used in the back etching is hot phosphoric acid.

4. The method according to claim 1, characterized in that In the step 1, an in-situ steam oxidation process is used to form the liner oxide layer.

5. The method according to claim 4, characterized in that The temperature of the in-situ steam oxidation process is 1050°C-1250°C, and the thickness of the liner oxide layer is 6. The method according to claim 1, characterized in that In the step three, the pad oxide layer is removed by wet etching with a high selectivity.

7. The method according to claim 1, characterized in that In the step three, another liner oxide layer is formed by an in-situ steam oxidation process.

8. The method according to claim 7, characterized in that The temperature of the in-situ steam oxidation process is 1050°C-1250°C, and the thickness of the other liner oxide layer is 9. The method according to claim 1, characterized in that: The oxide deposited in step 4 is HARP.

10. The method according to claim 1, characterized in that After the step 4 is implemented, the thickness of the oxide between the hard mask layers is firstly made to reach a predetermined value by an etch-back process, and then the hard mask layer is removed by a wet etching process.

11. A shallow trench isolation structure manufactured according to the method for manufacturing a shallow trench isolation structure of a semiconductor device according to any one of claims 1 to 10.

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