Semiconductor structure and test method thereof

Abstract

The embodiment of the invention discloses a semiconductor structure and a test method thereof, relates to the technical field of semiconductors, can reduce the size of the semiconductor structure, improves the test efficiency, and enables the semiconductor structure to be suitable for tests of different performances. The semiconductor structure includes a semiconductor substrate, a stacked structure, at least one first test pad, at least one second test pad, at least one third test pad, and at least one fourth test pad. The stacked structure comprises a plurality of test chips and a conductive layer which are stacked and coupled with each other. The conductive layer is arranged between two adjacent test chips and is coupled with the test chips. The conductive layer comprises a plurality of conductive structures which are arranged at intervals in the stacking direction perpendicular to the semiconductor substrate and the stacking structure; one first test bonding pad is coupled with one second test bonding pad through one conductive structure; a third test pad is coupled to a fourth test pad through a conductive structure.

Description

Technical Field

[0001] The embodiments of the present application relate to computer information technology, and relate to but are not limited to a semiconductor structure and a testing method thereof. Background Art

[0002] In order to realize a high-performance and small-sized semiconductor memory device, a plurality of chips are stacked in a single package to achieve high integration of the semiconductor memory device. The stacked plurality of chips can be interconnected using a through silicon via (TSV) type conductive structure.

[0003] In the related art, a semiconductor structure for testing the performance of a plurality of stacked chips occupies a large space, and the test efficiency of testing the plurality of semiconductor structures separately is low. Summary of the invention

[0004] In view of this, an embodiment of the present application provides a semiconductor structure and a testing method thereof to solve at least one problem existing in the prior art, which relates to the field of semiconductor technology, can reduce the size of the semiconductor structure, improve the testing efficiency, and enable the semiconductor structure to be suitable for testing of different performances.

[0005] The technical solution of the embodiment of the present application is implemented as follows:

[0006] In a first aspect, an embodiment of the present application provides a semiconductor structure, which includes: a semiconductor substrate, a stacked structure, at least one first test pad, at least one second test pad, at least one third test pad, and at least one fourth test pad.

[0007] The stacking structure is arranged on one side of the semiconductor substrate, and comprises a plurality of test chips which are stacked and coupled to each other and a conductive layer; the conductive layer is arranged between two adjacent test chips and coupled to the test chips.

[0008] At least one first test pad is disposed on a side of the stack structure away from the semiconductor substrate and is coupled to the stack structure. At least one second test pad is disposed on a side of the stack structure away from the semiconductor substrate and is spaced apart from the at least one first test pad; the at least one second test pad is coupled to the stack structure. At least one third test pad is disposed on a side of the stack structure close to the semiconductor substrate and is coupled to the stack structure. At least one fourth test pad is disposed on a side of the stack structure close to the semiconductor substrate and is spaced apart from the at least one third test pad; the at least one fourth test pad is coupled to the stack structure.

[0009] Among them, the conductive layer includes a plurality of conductive structures arranged at intervals along a stacking direction perpendicular to the semiconductor substrate and the stacking structure; one of the first test pads is coupled to one of the second test pads through one of the conductive structures; and one of the third test pads is coupled to one of the fourth test pads through one of the conductive structures.

[0010] In some examples, one of the conductive structures is coupled to one of the first test pads and one of the second test pads, and is coupled to one of the third test pads and one of the fourth test pads.

[0011] In some examples, the number of the test chips on the side of the conductive layer away from the semiconductor substrate may be different from the number of the test chips on the side of the conductive layer close to the semiconductor substrate.

[0012] In some examples, the semiconductor structure includes: an interconnection structure and a transfer structure. A plurality of interconnection structures are disposed in the test chip. Two opposite ends of the interconnection structure extending along the stacking direction of the semiconductor substrate and the stack structure are respectively exposed from the surface of the test chip. The transfer structure is disposed between two adjacent test chips; one transfer structure is respectively coupled to two interconnection structures of two adjacent test chips.

[0013] In some examples, along a stacking direction parallel to the semiconductor substrate and the stacked structure, the conductive layer is located between the first test chip and the second test chip. Along a stacking direction parallel to the semiconductor substrate and the stacked structure, one conductive structure covers two interconnect structures of the first test chip and covers two interconnect structures of the second test chip.

[0014] In some examples, the test chip includes a first redistribution layer and a second redistribution layer located on two opposite side surfaces of the test chip along a stacking direction of the semiconductor substrate and the stack structure.

[0015] A layer of conductive signal lines in the first redistribution layer is used as a first heating layer, and the first heating layer is coupled to the first test pad and the second test pad; and / or a layer of conductive signal lines in the second redistribution layer is used as a second heating layer, and the second heating layer is coupled to the third test pad and the fourth test pad. The conductive layer is used as a sensing layer.

[0016] In some examples, the interconnect structures in different test chips have the same material and / or size.

[0017] In some examples, the interconnect structure is made of the same material as the transfer structure; and / or the conductive layer is made of the same material as the interconnect structure.

[0018] In the above semiconductor structure, the stacked structure can be divided into two test structures, upper and lower, by the connection relationship and setting position of the conductive layer. On the basis that a first test pad is coupled to a second test pad through a conductive structure; and a third test pad is coupled to a fourth test pad through a conductive structure, the upper and lower test structures can reduce the occupied space of the semiconductor structure compared to two test structures arranged in the horizontal direction.

[0019] Furthermore, considering the scenario in which the semiconductor structure is used to test the performance of a multi-layer chip, a portion of the test structure can be tested through a conductive structure and a first test pad and a second test pad; another portion of the test structure can be tested through a conductive structure and a third test pad and a fourth test pad, which can improve the test efficiency, especially improve the scope of application of semiconductor structures for testing different properties.

[0020] In a second aspect, an embodiment of the present application provides a method for testing a semiconductor structure, for performing a radio frequency parameter test on a semiconductor structure as described in any of the above examples. The semiconductor structure includes a first test structure and a second test structure; the first test structure includes a plurality of test chips stacked between a first test pad and a conductive layer; the second test structure includes a plurality of test chips stacked between a third test pad and a conductive layer.

[0021] The test method includes: measuring the return loss of the reflected signal of the first test pad and the second test pad respectively, and measuring the power of the signal transmitted between the first test pad and the second test pad to determine the power of the signal transmitted by the first test structure. Measuring the return loss of the reflected signal of the third test pad and the fourth test pad respectively, and measuring the power of the signal transmitted between the third test pad and the fourth test pad to determine the power of the signal transmitted by the second test structure.

[0022] In the process of performing radio frequency parameter testing on the semiconductor structure, the first test structure can be tested through the conductive structure and a first test pad and a second test pad; the second test structure can be tested through the conductive structure and a third test pad and a fourth test pad. The first test structure and the second test structure can be tested separately. In a test machine, only the test pad coupled to the semiconductor structure needs to be changed to implement the testing of different test structures, which is conducive to improving the test efficiency.

[0023] In the third aspect, an embodiment of the present application provides a method for testing a semiconductor structure, characterized in that it is used to perform thermal testing on a semiconductor structure as described in any of the above examples; the semiconductor structure includes a first test structure and a second test structure; the first test structure includes a plurality of test chips stacked between a first heating layer and a conductive layer in a first redistribution layer coupled to a first test pad; the second test structure includes a plurality of test chips stacked between a second heating layer and a conductive layer in a second redistribution layer coupled to a third test pad.

[0024] The testing method includes: inputting current to the first test structure through the first test pad to achieve a thermal equilibrium state, determining the current and voltage between the first test pad and the second test pad; and determining the temperature of the conductive structure and the thermal resistance of the first test structure.

[0025] And, inputting current into the second test structure through the third test pad to reach a thermal equilibrium state, determining the current and voltage between the third test pad and the fourth test pad; and determining the temperature of the conductive structure and the thermal resistance of the second test structure.

[0026] In the above-mentioned process of thermal testing of the semiconductor structure, the first test structure can be tested through the conductive structure and a first test pad and a second test pad; the second test structure can be tested through the conductive structure and a third test pad and a fourth test pad. The first test structure and the second test structure can be tested separately, or the thermal test data can be collected at the same time during the operation steps of the RF signal test. Specifically, the interference factors involved in the actual test operation can be eliminated and the operation can be implemented to improve the test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In the accompanying drawings, like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation.

[0028] Figure 1 Structural schematic diagram of the semiconductor structure provided for the implementation of this application Figure 1 ;

[0029] Figure 2 Structural schematic diagram of the semiconductor structure provided for the implementation of this application Figure 2 ;

[0030] Figure 3 Structural schematic diagram of the semiconductor structure provided for the implementation of this application Figure 3 ;

[0031] Figure 4A schematic flow chart of a method for testing a semiconductor structure provided for the implementation of the present application;

[0032] Figure 5 A schematic flow chart of another method for testing a semiconductor structure provided for the implementation of the present application. DETAILED DESCRIPTION

[0033] The technical solution of the present application is further elaborated in detail below in conjunction with the accompanying drawings and specific embodiments of the specification.

[0034] In the embodiments of the present application, the terms "first", "second", etc. are used to distinguish similar objects, but are not used to describe a specific order or sequence.

[0035] In the embodiments of the present application, the term "A is in contact with B" includes the situation where A is in direct contact with B, or the situation where A is in indirect contact with B with other components interposed between A and B.

[0036] It should be understood that the "some embodiments" or "some examples" mentioned throughout the specification mean that specific features, structures or characteristics related to the embodiments are included in at least one embodiment of the present application. Therefore, "in some embodiments" or "in some examples" appearing throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the sequence number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned sequence numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments.

[0037] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0038] It will be understood that the meanings of “on,” “over,” and “over” in this application should be interpreted in the broadest manner, so that “on” not only means that it is “on” something with no intervening features or layers (i.e., directly on something), but also includes the meaning of “on” something with intervening features or layers.

[0039] It should be noted that although this specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each implementation mode may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

[0040] In order to meet the demand for reliable, small-size packaging of semiconductor integrated circuits, stacked packaging technology has been developed that enables miniaturization and high performance of electrical / electronic devices.

[0041] "Stacked packaging" in the field of semiconductor technology refers to a device having two or more chips or packages stacked in a vertical direction. By implementing stacked packaging, a semiconductor memory device with a capacity more than twice the allowable storage capacity achieved through a typical semiconductor process can be formed.

[0042] The stacked packaging technology has the advantages of large storage capacity, high packaging density and small packaging size. The stacked package can be formed by stacking a plurality of semiconductor chips and then packaging these stacked semiconductor chips together. Alternatively, the stacked package can be formed by first packaging the semiconductor chips and then stacking the above-mentioned packaged semiconductor chips. Among them, the individual semiconductor chips in the stacked package can be electrically connected to each other via metal wires or conductive structures formed by through-silicon vias (TSV), so that the multiple semiconductor chips are physically and electrically connected to each other in the vertical direction by means of the TSV-type conductive structure formed inside themselves. In this way, testing can be performed based on the TSV-type conductive structure in the semiconductor structure after stacking packaging and the test pads of the peripherals.

[0043] For example, the signal transmission quality of the entire semiconductor structure can be tested. Multiple semiconductor structures need to be tested separately, and the horizontal space occupied by the multiple semiconductor structures is relatively large.

[0044] Alternatively, a heating layer and a sensing layer may be additionally provided between the stacked multiple semiconductor chips, and then the thermal resistance of the multiple semiconductor chips between the heating layer and the sensing layer may be tested. In other words, only the thermal resistance of a certain number of stacked semiconductor chips as a whole structure can be tested in a semiconductor structure. Furthermore, for thermal testing of multiple semiconductor structures, each semiconductor structure needs to be provided with a heating layer and a sensing layer, which significantly increases the occupied space of the multiple semiconductor structures when testing multiple semiconductor structures.

[0045] In order to solve the above problems, the present application provides a semiconductor structure and a testing method thereof, which can reduce the size of the semiconductor structure, improve the testing efficiency, and enable the semiconductor structure to be suitable for testing of different performances.

[0046] In some embodiments, Figure 1 to Figure 3 As shown, the present application provides a semiconductor structure 100 . The semiconductor structure 100 includes: a semiconductor substrate 110 , a stack structure 120 , at least one first test pad 130 , at least one second test pad 140 , at least one third test pad 150 , and at least one fourth test pad 160 .

[0047] For example, the semiconductor substrate 110 may be a composite layer of multiple layers of materials. For example, the semiconductor substrate 110 may include a conductive stack formed with a conductive signal line and a dielectric stack. The specific structure of the semiconductor substrate 110 may be set according to actual needs and is not limited here.

[0048] The stack structure 120 is disposed on one side of the semiconductor substrate 110 and includes a plurality of test chips 121 stacked and coupled to each other and a conductive layer 122. The conductive layer 122 is disposed between two adjacent test chips 121 and coupled to the test chips 121.

[0049] For example, the test chip 121 can be a chip or a die. It can be understood that the chip and the die can refer to the same structure (the names can be interchangeable), and the die can be a chip that is not packaged. The present application does not limit the specific structure of the test chip 121. In the subsequent examples, the test chip 121 represents an integrated structure with an internal circuit structure.

[0050] At least one first test pad 130 is disposed on a side of the stack structure 120 away from the semiconductor substrate 110 and is coupled to the stack structure 120 .

[0051] The at least one second test pad 140 is disposed on a side of the stack structure 120 away from the semiconductor substrate 110 and is spaced apart from the at least one first test pad 130. The at least one second test pad 140 is coupled to the stack structure 120.

[0052] At least one third test pad 150 is disposed on a side of the stack structure 120 close to the semiconductor substrate 110 and is coupled to the stack structure 120 .

[0053] The at least one fourth test pad 160 is disposed on a side of the stack structure 120 close to the semiconductor substrate 110 and is spaced apart from the at least one third test pad 150. The at least one fourth test pad 160 is coupled to the stack structure 120.

[0054] For example, the first test pad 130, the second test pad 140, the third test pad 150 and the fourth test pad 160 can be conductive structures for transmitting the current or voltage signal of the external test equipment to the stack structure 120. For example, the first test pad 130 can be a solder ball. Similarly, the second test pad 140, the third test pad 150 and the fourth test pad 160 can be conductive structures with the same structure and material as the first test pad 130, and can be prepared and formed using the same manufacturing process to improve process efficiency.

[0055] Among them, the conductive layer 122 includes a plurality of conductive structures 1221 spaced apart along a stacking direction perpendicular to the semiconductor substrate 110 and the stacking structure 120. For example, the conductive layer 122 can be a plurality of independent conductive structures 1221 formed in the same layer and the same process, and one conductive structure 1221 is used to implement a test structure (based on the different numbers of multiple test chips stacked between the test pad and the conductive structure 1221); or it can be a plurality of conductive structures 1221 coupled to different regions of the same signal line based on the change in the extension direction of the signal line in different test chips, and the plurality of conductive structures are used to implement a test structure. The present application does not impose specific restrictions on the arrangement relationship between the point structure and the test chip, and can be adjusted according to actual needs.

[0056] A first test pad 130 is coupled to a second test pad 140 via a conductive structure 1221 . A third test pad 150 is coupled to a fourth test pad 160 via a conductive structure 1221 .

[0057] For example, the conductive structure 1221 coupling a first test pad 130 and a second test pad 140 may be the same as or different from the conductive structure 1221 coupling a third test pad 150 and a fourth test pad 160 , and may be configured according to actual needs.

[0058] In the semiconductor structure 100, the stacked structure 120 can be divided into two upper and lower test structures by the connection relationship and the setting position of the conductive layer 122. On the basis that a first test pad 130 is coupled to a second test pad 140 through a conductive structure 1221; and a third test pad 150 is coupled to a fourth test pad 160 through a conductive structure 1221, the upper and lower test structures can reduce the occupied space of the semiconductor structure 100 compared with two test structures arranged in the horizontal direction.

[0059] Furthermore, considering the scenario in which the semiconductor structure 100 is applied to test the performance of a multi-layer chip, a part of the test structure can be tested through the conductive structure 1221 and a first test pad 130, and a second test pad 140; another part of the test structure can be tested through the conductive structure 1221 and a third test pad 150, and a fourth test pad 160, which can improve the test efficiency, especially improve the scope of application of the semiconductor structure 100 for testing different properties.

[0060] In some examples, such as Figure 2 As shown, a conductive structure 1221 is coupled to a first test pad 130 and a second test pad 140 , and is coupled to a third test pad 150 and a fourth test pad 160 .

[0061] A conductive structure 1221 can be coupled to a first test pad 130, a second test pad 140, a third test pad 150 and a fourth test pad 160 respectively, which is beneficial to improving the electrical connection effect of the conductive structure 1221 in the test scenario of the semiconductor structure 100, and improving the test accuracy of the test chip 121 in the upper / lower half of the test conductive structure 1221.

[0062] In some examples, such as Figure 2 and Figure 3 As shown, the number of the test chips 121 on the side of the conductive layer 122 away from the semiconductor substrate 110 may be different from the number of the test chips 121 on the side of the conductive layer 122 close to the semiconductor substrate 110 .

[0063] For example, Figure 2 As shown, in a semiconductor structure 100, the stacked structure 120 includes 7 stacked test chips 121. The number of test chips 121 on the side of the conductive layer 122 away from the semiconductor substrate 110 is 3, and the number of test chips 121 on the side of the conductive layer 122 close to the semiconductor substrate 110 is 4.

[0064] In this way, the test structure (ie, the structure between the test pad and the conductive layer 122 ) with different numbers of chips stacked can be tested, satisfying the performance test of the semiconductor structure 100 in the application scenario of stacking different numbers of test chips 121 .

[0065] For example, Figure 3 As shown, in a semiconductor structure 100, the stacked structure 120 includes 8 stacked test chips 121. The number of test chips 121 on the side of the conductive layer 122 away from the semiconductor substrate 110 is 3, and the number of test chips 121 on the side of the conductive layer 122 close to the semiconductor substrate 110 is 5.

[0066] In different semiconductor structures 100, the conductive layer 122 can be set at different positions. For example, multiple semiconductor structures 100 all include 8 layers of test chips 121. In a semiconductor structure 100, the conductive layer 122 can be set between the first layer test chip 121 and the second layer test chip 121. Alternatively, in a semiconductor structure 100, the conductive layer 122 can be set between the second layer test chip 121 and the third layer test chip 121, and so on. In multiple semiconductor structures 100 with the same number of test chips 121 stacked, changing the position of the conductive layer 122 can test the performance of test chips 121 with different numbers of stacked.

[0067] In this way, compared with the method of testing the semiconductor structure composed of each test structure separately, the semiconductor structure 100 provided in the present application has two test structures, which can reduce the preparation quantity of the semiconductor structure 100 and improve the test efficiency.

[0068] In addition, the number of test chips 121 on the side of the conductive layer 122 close to the semiconductor substrate 110 is 4. The number of test chips 121 on the side of the conductive layer 122 far from the semiconductor substrate 110 may be the same as the number of test chips 121 on the side of the conductive layer 122 close to the semiconductor substrate 110.

[0069] For example, Figure 1 As shown, in a semiconductor structure 100, the stacked structure 120 includes eight stacked test chips 121. The number of the test chips 121 on the side of the conductive layer 122 away from the semiconductor substrate 110 is four.

[0070] In the case of testing the test chip 121 in the upper part of the conductive layer 122, a pre-test is performed and stored as reference data based on the possible interference of the test chip 121 in the lower part of the conductive layer 122 on the signal transmission performance or thermal balance. In this way, in the process of testing the test chips 121 in the upper and lower parts of the entire semiconductor structure 100, respectively, the influence of the pre-tested reference data is eliminated, and the influence of the first test pad 130 and the second test pad 140 (or the third test pad 150 and the fourth test pad 160) on the signal transmission performance or thermal balance effect can be quickly determined.

[0071] In some examples, such as Figure 2 As shown, the semiconductor structure 100 includes an interconnect structure 170 and a transfer structure 180 .

[0072] A plurality of interconnect structures 170 are disposed in the test chip 121. Opposite ends of the interconnect structures 170 extending along the stacking direction of the semiconductor substrate 110 and the stack structure 120 are exposed from the surface of the test chip 121, respectively.

[0073] For example, the interconnection structure 170 can be a conductive structure formed based on TSV holes and penetrates the test chip 121. The present application does not specifically limit how the interconnection structure 170 penetrates the test chip 121, and can be adjusted in combination with the arrangement of the integrated circuit structure inside the different test chips 121.

[0074] like Figure 2 As shown, the transfer structure 180 is disposed between two adjacent test chips 121. One transfer structure 180 is coupled to two interconnection structures 170 of two adjacent test chips 121, respectively.

[0075] For example, the transfer structure 180 is configured to improve the connection reliability of different interconnect structures 170. For example, in the process of coupling different test chips 121 through the interconnect structure 170, the transfer structure 180 is set to couple the interconnect structures 170 located in different areas (one end of the two interconnect structures 170 is not directly facing each other) together.

[0076] In some examples, the interconnect structures 170 in different test chips 121 have the same material and / or size.

[0077] For example, the interconnection structures 170 in different test chips 121 are made of the same material. Alternatively, the interconnection structures 170 in different test chips 121 are made of the same size. Alternatively, the interconnection structures 170 in different test chips 121 are made of the same material and have the same size.

[0078] In this way, when testing a plurality of stacked test chips 121 , the signal transmission loss caused by the interconnection structures 170 of different materials and / or sizes can be reduced, thereby improving the test accuracy.

[0079] In some examples, the material of interconnect structure 170 is the same as the material of via structure 180 ; and / or the material of conductive layer 122 is the same as the material of interconnect structure 170 .

[0080] For example, the material of the interconnect structure 170 is the same as the material of the transfer structure 180. Alternatively, the conductive layer 122 is the same as the material of the interconnect structure 170. Alternatively, the material of the interconnect structure 170 is the same as the material of the transfer structure 180, and the conductive layer 122 is the same as the material of the interconnect structure 170.

[0081] In this way, when testing a plurality of stacked test chips 121 , the difference in the influence of different materials on signal transmission loss can be reduced, thereby improving the test accuracy.

[0082] In some examples, such as Figure 3As shown, along a stacking direction parallel to the semiconductor substrate 110 and the stacked structure 120 , the conductive layer 122 is located between the first test chip 121 a and the second test chip 121 b .

[0083] Along a stacking direction parallel to the semiconductor substrate 110 and the stack structure 120 , one conductive structure 1221 covers two interconnect structures 170 of the first test chip 121 a and covers two interconnect structures 170 of the second test chip 121 b .

[0084] For example, when the conductive structure 1221 is capable of coupling the first test pad 130, the second test pad 140, the third test pad 150 and the fourth test pad 160, according to the structure in which the test chip 121 is mutually coupled through the interconnection structure 170, the size of the conductive structure 1221 along the stacking direction perpendicular to the semiconductor substrate 110 and the stacking structure 120 can be set, so that the conductive structure 1221 can be coupled to the two interconnection structures 170 of the first test chip 121a, and to the two interconnection structures 170 of the second test chip 121b, thereby improving the electrical connection reliability between the first test chip 121a and the second test chip 121b. In the process of testing the entire semiconductor structure 100, the probability of errors in signal loss due to poor electrical connection can be reduced, thereby improving the accuracy of the test.

[0085] In some examples, such as Figure 2 As shown, the test chip 121 includes a first redistribution layer 1211 and a second redistribution layer 1212 located on two opposite sides of the test chip 121 along the stacking direction of the semiconductor substrate 110 and the stack structure 120 .

[0086] It is understandable that the first redistribution layer 1211 and the second redistribution layer 1212 are respectively arranged on two opposite sides of the test chip 121, or on the same side of the test chip 121, and can be adjusted according to actual needs. In order to facilitate the use of the semiconductor structure for thermal testing, the signal line in the redistribution layer is used as a heating layer to reduce the thickness of the semiconductor structure 100, and the first redistribution layer 1211 and the second redistribution layer 1212 are respectively arranged on two opposite sides of the test chip 121.

[0087] For example, in a structure where multiple test chips 121 are stacked, the first redistribution layer 1211 may be located on a side of the test chip 121 away from the semiconductor substrate 110 , and the second redistribution layer 1212 may be located on a side of the test chip 121 close to the semiconductor substrate 110 .

[0088] A layer of conductive signal lines in the first redistribution layer 1211 serves as a first heat generating layer (not shown in the figure), and the first heat generating layer is coupled to the first test pad 130 and the second test pad 140 .

[0089] And / or, a layer of conductive signal lines in the second redistribution layer 1212 serves as a second heat generating layer (not shown in the figure), and the second heat generating layer is coupled to the third test pad 150 and the fourth test pad 160 .

[0090] The conductive layer 122 serves as a sensing layer.

[0091] For example, a layer of conductive signal lines in the first redistribution layer 1211 is used as a first heat generating layer (not shown in the figure), and the first heat generating layer is coupled to the first test pad 130 and the second test pad 140 .

[0092] The conductive layer 122 serves as a sensing layer.

[0093] In this way, a plurality of test chips 121 stacked between the first heat generating layer and the conductive layer 122 may be thermally tested through the first test pad 130 and the second test pad 140 .

[0094] As another example, a layer of conductive signal lines in the second redistribution layer 1212 serves as a second heat generating layer (not shown in the figure), and the second heat generating layer is coupled to the third test pad 150 and the fourth test pad 160 .

[0095] The conductive layer 122 serves as a sensing layer.

[0096] In this way, a plurality of test chips 121 stacked between the first heat generating layer and the conductive layer 122 may be thermally tested through the first test pad 130 and the second test pad 140 .

[0097] As another example, a layer of conductive signal lines in the first redistribution layer 1211 serves as a first heat generating layer (not shown in the figure), and the first heat generating layer is coupled to the first test pad 130 and the second test pad 140 .

[0098] A layer of conductive signal lines in the second redistribution layer 1212 serves as a second heat generating layer (not shown in the figure), and the second heat generating layer is coupled to the third test pad 150 and the fourth test pad 160 .

[0099] The conductive layer 122 serves as a sensing layer.

[0100] In this way, thermal testing can be performed on multiple test chips 121 stacked between the first heating layer and the conductive layer 122 through the first test pad 130 and the second test pad 140 respectively; and thermal testing can be performed on multiple test chips 121 stacked between the first heating layer and the conductive layer 122 through the first test pad 130 and the second test pad 140, thereby improving the thermal testing efficiency of the semiconductor structure 100.

[0101] In some embodiments, Figure 4As shown, an embodiment of the present application provides a testing method for a semiconductor structure 100, which is used to perform radio frequency parameter testing on the semiconductor structure 100 provided in any of the above examples.

[0102] like Figure 3 As shown, the semiconductor structure 100 includes a first test structure 1001 and a second test structure 1002. The first test structure 1001 includes a plurality of test chips 121 stacked between a first test pad 130 and a conductive layer 122. The second test structure 1002 includes a plurality of test chips 121 stacked between a third test pad 150 and a conductive layer 122.

[0103] like Figure 4 As shown, the testing method includes: S100 and S200.

[0104] S100 : respectively measuring the return loss of the reflected signal of the first test pad 130 and the second test pad 140 , and measuring the power of the signal transmitted between the first test pad 130 and the second test pad 140 , to determine the power of the signal transmitted by the first test structure 1001 .

[0105] For example, a vector network analyzer (VNA) is used to transmit power to the first test structure 1001 through the first test pad 130, and then the return loss of the reflected signal of the first test pad 130 is measured, so that the noise of the signal transmitted by the first test structure 1001 can be determined, and the power of the signal transmitted by the first test structure 1001 can be determined.

[0106] Similarly, a vector network analyzer (VNA) can be used to transmit power to the first test structure 1001 through the second test pad 140, and then the return loss of the reflected signal from the second test pad 140 can be measured to determine the noise of the signal transmitted by the first test structure 1001 and the power of the signal transmitted by the first test structure 1001.

[0107] In addition, the power transmitted from the first test pad 130 to the second test pad 140 may be measured. Alternatively, the power transmitted from the second test pad 140 to the first test pad 130 may be measured. The present application does not impose any specific restrictions on the test method for the signal transmission performance of the semiconductor structure 100, which may be set according to actual needs.

[0108] S200 : respectively measuring the return loss of the reflected signal of the third test pad 150 and the fourth test pad 160 , and measuring the power of the signal transmitted between the third test pad 150 and the fourth test pad 160 , to determine the power of the signal transmitted by the second test structure 1002 .

[0109] For example, a vector network analyzer (VNA) is used to transmit power to the second test structure 1002 through the third test pad 150, and then the return loss of the reflected signal of the third test pad 150 is measured, so that the noise of the signal transmitted by the second test structure 1002 can be determined, and the power of the signal transmitted by the second test structure 1002 can be determined.

[0110] Similarly, a vector network analyzer (VNA) can be used to transmit power to the second test structure 1002 through the fourth test pad 160, and then the return loss of the reflected signal of the fourth test pad 160 can be measured to determine the noise of the signal transmitted by the second test structure 1002 and the power of the signal transmitted by the second test structure 1002.

[0111] In addition, the power transmitted from the third test pad 150 to the fourth test pad 160 may also be measured. Alternatively, the power transmitted from the fourth test pad 160 to the third test pad 150 may be measured. The present application does not impose any specific restrictions on the test method for the signal transmission performance of the semiconductor structure 100, which may be set according to actual needs.

[0112] In the above-mentioned process of performing RF parameter testing on the semiconductor structure 100, the first test structure 1001 can be tested through the conductive structure 1221 and a first test pad 130 and a second test pad 140; the second test structure 1002 can also be tested through the conductive structure 1221 and a third test pad 150 and a fourth test pad 160, which can improve the test efficiency. The first test structure 1001 and the second test structure 1002 can be tested separately. In a test machine, only the test pad coupled to the semiconductor structure 100 needs to be changed to implement the testing of different test structures, which is conducive to improving the test efficiency.

[0113] In some embodiments, Figure 5 As shown, an embodiment of the present application provides a testing method for a semiconductor structure 100, which is used to perform a thermal test on the semiconductor structure 100 provided in any of the above examples.

[0114] like Figure 3 As shown, the semiconductor structure 100 includes a first test structure 1001 and a second test structure 1002. The first test structure 1001 includes a plurality of test chips 121 stacked between a first test pad 130 and a conductive layer 122. The second test structure 1002 includes a plurality of test chips 121 stacked between a third test pad 150 and a conductive layer 122.

[0115] like Figure 5 As shown, the testing method includes: S300 and S400.

[0116] S300 : inputting current to the first test structure 1001 through the first test pad 130 to reach a thermal equilibrium state, determining the current and voltage between the first test pad 130 and the second test pad 140 ; ​​determining the temperature of the conductive structure 1221 and the thermal resistance of the first test structure 1001 .

[0117] For example, a first current is input to the conductive layer 122 through the first test pad 130 to the first test structure 1001 to achieve a thermal equilibrium state.

[0118] A first voltage between the first test pad 130 and the second test pad 140 is determined.

[0119] The temperature of the conductive structure 1221 and the thermal resistance of the first test structure 1001 are determined according to the first current and the first voltage, and the relationship between the resistivity and the temperature of the conductive structure 1221 .

[0120] S400 : Inputting current to the second test structure 1002 through the third test pad 150 to achieve a thermal equilibrium state, determining the current and voltage between the third test pad 150 and the fourth test pad 160 ; determining the temperature of the conductive structure 1221 and the thermal resistance of the second test structure 1002 .

[0121] For example, the second current is input to the conductive layer 122 through the third test pad 150 to the second test structure 1002 to achieve a thermal equilibrium state.

[0122] A second voltage between the third test pad 150 and the fourth test pad 160 is determined.

[0123] The temperature of the conductive structure 1221 and the thermal resistance of the second test structure 1002 are determined according to the second current and the second voltage, and the relationship between the resistivity and the temperature of the conductive structure 1221 .

[0124] It is understandable that in the relationship between the resistivity and temperature of the conductive structure 1221, the material, thickness, area, etc. of the conductive structure 1221 are all factors affecting the resistivity and need to be determined based on the conductive structure 1221 coupled to different test structures. This application does not impose any restrictions on this.

[0125] During the thermal test of the semiconductor structure 100, the first test structure 1001 can be tested through the conductive structure 1221, a first test pad 130, and a second test pad 140; the second test structure 1002 can be tested through the conductive structure 1221, a third test pad 150, and a fourth test pad 160. The first test structure 1001 and the second test structure 1002 can be tested separately, or the thermal test data can be collected at the same time during the operation steps of the RF signal test. Specifically, the interference factors involved in the actual test operation can be eliminated and the operation can be implemented to improve the test efficiency.

[0126] The above is only an implementation method of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that: include: Semiconductor substrate; A stacking structure, arranged on one side of the semiconductor substrate, comprising a plurality of test chips stacked and coupled to each other and a conductive layer; The conductive layer is disposed between two adjacent test chips and coupled to the test chips; at least one first test pad, disposed on a side of the stack structure away from the semiconductor substrate and coupled to the stack structure; At least one second test pad is disposed on a side of the stack structure away from the semiconductor substrate and is spaced apart from the at least one first test pad; the at least one second test pad is coupled to the stack structure; at least one third test pad, disposed on a side of the stack structure close to the semiconductor substrate and coupled to the stack structure; at least one fourth test pad, disposed on a side of the stack structure close to the semiconductor substrate and spaced apart from the at least one third test pad; the at least one fourth test pad is coupled to the stack structure; Wherein, the conductive layer comprises a plurality of conductive structures spaced apart along a stacking direction perpendicular to the semiconductor substrate and the stacked structure; One of the first test pads is coupled to one of the second test pads through one of the conductive structures; and one of the third test pads is coupled to one of the fourth test pads through one of the conductive structures.

2. The semiconductor structure according to claim 1, characterized in that: One of the conductive structures is coupled to one of the first test pads and one of the second test pads, and is coupled to one of the third test pads and one of the fourth test pads.

3. The semiconductor structure according to claim 1, characterized in that: The number of the test chips on the side of the conductive layer far from the semiconductor substrate may be different from the number of the test chips on the side of the conductive layer close to the semiconductor substrate.

4. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure comprises: A plurality of interconnect structures are disposed in the test chip; opposite ends of the interconnect structures extending along the stacking direction of the semiconductor substrate and the stack structure are respectively exposed from the surface of the test chip; The transfer structure is arranged between two adjacent test chips; one transfer structure is respectively coupled to the two interconnection structures of the two adjacent test chips.

5. The semiconductor structure according to claim 4, characterized in that: The conductive layer is located between the first test chip and the second test chip along a stacking direction parallel to the semiconductor substrate and the stack structure; Along a stacking direction parallel to the semiconductor substrate and the stacked structure, one conductive structure covers the two interconnection structures of the first test chip and covers the two interconnection structures of the second test chip.

6. The semiconductor structure according to claim 1, characterized in that The test chip comprises a first redistribution layer and a second redistribution layer located on two opposite side surfaces of the test chip along a stacking direction of the semiconductor substrate and the stack structure; A layer of conductive signal lines in the first redistribution layer is used as a first heat generating layer, and the first heat generating layer is coupled to the first test pad and the second test pad; and / or, a layer of conductive signal lines in the second redistribution layer serves as a second heating layer, and the second heating layer is coupled to the third test pad and the fourth test pad; The conductive layer serves as a sensing layer.

7. The semiconductor structure according to claim 4, characterized in that: The interconnection structures in different test chips have the same material and / or size.

8. The semiconductor structure according to claim 4, characterized in that: The material of the interconnection structure is the same as the material of the transfer structure; And / or, the conductive layer and the interconnect structure are made of the same material.

9. A method for testing a semiconductor structure, characterized in that: Used to perform radio frequency parameter testing on the semiconductor structure according to any one of claims 1 to 8; the semiconductor structure comprises a first test structure and a second test structure; the first test structure comprises a plurality of test chips stacked between a first test pad and a conductive layer; The second test structure includes a plurality of test chips stacked between the third test pad and the conductive layer; The test method includes: Respectively measuring the return losses of the reflected signals of the first test pad and the second test pad, and measuring the power of the signal transmitted between the first test pad and the second test pad to determine the power of the signal transmitted by the first test structure; The return losses of the reflected signals of the third test pad and the fourth test pad are measured respectively, and the power of the signal transmitted between the third test pad and the fourth test pad is measured to determine the power of the signal transmitted by the second test structure.

10. A method for testing a semiconductor structure, characterized in that: Used to perform thermal testing on the semiconductor structure according to any one of claims 1 to 8; the semiconductor structure comprises a first test structure and a second test structure; the first test structure comprises a plurality of test chips stacked between a first heat generating layer and a conductive layer in a first redistribution layer coupled to a first test pad; The second test structure includes a plurality of test chips stacked between a second heat generating layer and a conductive layer in a second redistribution layer coupled to a third test pad; The test method includes: Inputting current to the first test structure through the first test pad to achieve a thermal equilibrium state, and determining a current and a voltage between the first test pad and a second test pad; determining a temperature of the conductive structure and a thermal resistance of the first test structure; and, inputting a current into the second test structure through the third test pad to reach a thermal equilibrium state, and determining a current and a voltage between the third test pad and a fourth test pad; A temperature of the conductive structure and a thermal resistance of the second test structure are determined.

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