Measurement structure and monitoring method of contact / through hole etching process and semiconductor structure

Abstract

The invention discloses a measuring structure and a monitoring method for a contact / through hole etching process and a semiconductor structure, and belongs to the field of semiconductors, the measuring structure comprises a first test pad which comprises an etching barrier layer and a contact hole / through hole dielectric layer, and the first test pad is provided with a first contact / through hole array; the second test pad comprises a monitoring dielectric layer, an etching barrier layer and a contact hole / through hole dielectric layer, and the second test pad is provided with a second contact / through hole array; wherein the first test pad is arranged on an insulating dielectric layer, and the depth of the first contact / through hole array extends into the insulating dielectric layer; the second test pad is arranged on the wafer silicon substrate layer, and the depth of the second contact / through hole array extends to the monitoring dielectric layer. Through the measurement structure of the contact / through hole etching process and the semiconductor structure disclosed by the invention, the over-etching of the contact / through hole can be monitored under the condition that the semiconductor structure is not damaged.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor manufacturing, and in particular relates to a measurement structure and a monitoring method for a contact / through hole etching process and a semiconductor structure. Background Art

[0002] The etching of contact holes and through holes is a key process step in the wafer manufacturing process. After forming multiple semiconductor devices on the wafer silicon substrate, a multi-layer stacked film will be formed on the semiconductor devices, and then a metal interconnection layer will be formed on the stacked film to connect the multiple semiconductor devices to each other to form a functional circuit. Among them, the first metal interconnection layer is connected to the semiconductor device through a contact hole, and other metal interconnection layers are connected through through holes.

[0003] When etching contact holes and through holes, the over-etching depth of the contact holes and through holes needs to be monitored. However, since the depth of the contact holes and through holes is deep and the over-etching depth of the contact holes and through holes is small, it is impossible to accurately measure the over-etching depth of the contact holes and through holes through optical detection. Summary of the invention

[0004] The object of the present invention is to provide a measurement structure, a monitoring method and a semiconductor structure for a contact / through hole etching process, which can solve the problem that the over-etching depth of contact holes and through holes cannot be accurately measured by optical detection methods.

[0005] In order to solve the above technical problems, the present invention is achieved through the following technical solutions: The present invention provides a measurement structure for a contact / through hole etching process, wherein the measurement structure is arranged in a cutting path of a wafer, and the measurement structure comprises: A first test pad, comprising an etch stop layer and a contact hole / through hole dielectric layer, wherein the first test pad is provided with a first contact / through hole array; and A second test pad, comprising a monitoring dielectric layer, an etching barrier layer and a contact hole / through hole dielectric layer, wherein the second test pad is provided with a second contact / through hole array; Among them, the first test pad is arranged on the insulating dielectric layer, and the depth of the first contact / through-hole array extends into the insulating dielectric layer; the second test pad is arranged on the wafer silicon substrate layer, and the depth of the second contact / through-hole array extends to the monitoring dielectric layer; the first test pad and the second test pad are arranged adjacent to each other.

[0006] In one embodiment of the present invention, the monitoring medium layer is made of a conductive metal material, and an etching selectivity ratio between the insulating medium layer and the monitoring medium layer is greater than 10.

[0007] In one embodiment of the present invention, when the measurement structure is used to measure a contact hole, the insulating dielectric layer is a silicon oxide layer in a shallow trench in a silicon substrate of a wafer.

[0008] In an embodiment of the present invention, when the measurement structure is used to measure a contact hole, the monitoring dielectric layer is a metal silicide layer.

[0009] In one embodiment of the present invention, when the measurement structure is used to measure a through hole, the monitoring medium layer is a metal wire layer.

[0010] In one embodiment of the present invention, when the measurement structure is used to measure a through hole, the insulating dielectric layer is a low-k silicon oxide layer deposited on the surface of a wafer silicon substrate.

[0011] In one embodiment of the present invention, the distance between the centers of the first test pad and the second test pad ranges from 50 um to 1 mm.

[0012] In one embodiment of the present invention, the size of the first test pad and the second test pad is equal to or greater than 50um×50um.

[0013] The present invention also provides a monitoring method for the measurement structure as described above, wherein the measurement structure is used to monitor the over-etched thickness of the monitoring medium layer of the contact hole / through hole, and the monitoring method comprises: optically measuring the depth of contacts / vias in the first array of contacts / vias in the first test pad; optically measuring the depth of contacts / vias in the second array of contacts / vias in the second test pad; The difference between the contact / via depth of the first contact / via array and the contact / via depth of the second contact / via array is obtained, and the over-etched thickness of the monitoring dielectric layer is obtained based on the depth difference and the etching rate difference between the monitoring dielectric layer and the insulating dielectric layer.

[0014] The present invention also provides a semiconductor structure, comprising a measurement structure for a contact / via etching process as described in any one of the above items.

[0015] In summary, the present invention provides a measurement structure, monitoring method and semiconductor structure for a contact / through hole etching process, wherein the measurement structure for the contact / through hole etching process includes a first test pad and a second test pad, the first test pad includes an etching barrier layer and a contact hole / through hole dielectric layer, and the first test pad is provided with a first contact / through hole array. The second test pad includes a monitoring dielectric layer, an etching barrier layer and a contact hole / through hole dielectric layer, and the second test pad is provided with a second contact / through hole array. Wherein, the first test pad is arranged on an insulating dielectric layer, and the depth of the first contact / through hole array extends into the insulating dielectric layer. The second test pad is arranged on a wafer silicon substrate layer, and the depth of the second contact / through hole array extends to the monitoring dielectric layer, and the first test pad and the second test pad are arranged adjacent to each other. When using the measurement structure for the contact / through hole etching process provided by the present application to monitor the over-etched thickness of the monitoring dielectric layer of the contact hole / through hole, the depth of the contact / through hole in the first contact / through hole array in the first test pad is first optically measured, and then the depth of the contact / through hole in the second contact / through hole array in the second test pad is optically measured. The difference between the contact / through hole depth of the first contact / through hole array and the contact / through hole depth of the second contact / through hole array is obtained, and the over-etched thickness of the monitoring dielectric layer is obtained based on the depth difference and the etching rate difference between the monitoring dielectric layer and the insulating dielectric layer. This can avoid damage to semiconductor devices caused by measurement, and can also avoid the over-etching depth being too small to measure, thereby efficiently and non-destructively obtaining the degree of contact / through hole over-etching. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0017] Figure 1 Schematic diagram of a semiconductor structure in one embodiment of the present application.

[0018] Figure 2 FIG. 1 is a schematic diagram of a structure for forming a contact hole in an embodiment of the present application.

[0019] Figure 3 FIG. 1 is a schematic diagram of a structure for forming contact in an embodiment of the present application.

[0020] Figure 4 It is a schematic diagram of a structure for forming a through hole in one embodiment of the present application.

[0021] Figure 5 It is a structural schematic diagram of forming a conductive structure in one embodiment of the present application.

[0022] Figure 6It is a top view of a measurement structure of a contact / through hole etching process when measuring a contact hole in one embodiment of the present application.

[0023] Figure 7 It is a cross-sectional view of a measurement structure of a contact / through hole etching process when measuring a contact hole in one embodiment of the present application.

[0024] Figure 8 It is a top view of a measurement structure of a contact / via etching process when measuring a via in one embodiment of the present application.

[0025] Fig. 9 It is a cross-sectional view of a measurement structure of a contact / via etching process when measuring a via in one embodiment of the present application.

[0026] Description of labels: 101, wafer silicon substrate; 102, shallow trench isolation structure; 103, active area; 104, gate; 105, metal silicide layer; 106, first etch barrier layer; 107, contact hole dielectric layer; 108, contact; 1081, contact hole; 109, metal interconnect layer; 110, first photoresist layer; 111, second etch barrier layer; 112, through hole dielectric layer; 113, conductive structure; 1131, through hole; 114, metal layer; 1141, wire layer; 1142, intermetallic dielectric layer; 115, second photoresist layer; 201, first test pad; 2011, first contact / through hole; 202, second test pad; 2021, second contact / through hole. DETAILED DESCRIPTION

[0027] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0028] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0029] In the present invention, it should be noted that, if the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, if the terms "first" and "second" appear, they are only used for description and distinction purposes, and cannot be understood as indicating or implying relative importance.

[0030] See also Figures 1 to 5 As shown, when forming an integrated circuit semiconductor structure, a shallow trench isolation structure 102 and an active area 103 are first formed on a wafer silicon substrate 101, and then a gate 104 and other structures are formed on the wafer silicon substrate 101, and then a plurality of semiconductor devices are formed on the wafer silicon substrate 101. Afterwards, a multi-layer stacked film is formed on the wafer silicon substrate 101 and the semiconductor device, and a contact hole 1081 is formed in the multi-layer stacked film, and a conductive material is filled in the contact hole 1081 to form a contact 108. Finally, a metal interconnection layer 109 is formed on the multi-layer stacked film to form a complete functional circuit. Among them, the metal interconnection layer 109 is connected to the gate 104 or the active area 103 of the semiconductor device through the contact 108, and other metal interconnection layers 109 are connected through the conductive structure 113 in the through hole 1131.

[0031] See also Figure 1 As shown, it should be noted that, on a wafer silicon substrate 101, there are usually hundreds to thousands of chips connected together, and a scribe line (not shown in the figure) is set between each chip. After the process and test of the semiconductor device on the wafer silicon substrate 101 are completed, the semiconductor device on the wafer silicon substrate 101 is divided into multiple chips through the scribe line.

[0032] See also Figures 1 to 3As shown, in one embodiment of the present invention, the multi-layer stacked film formed on the wafer silicon substrate 101 and the semiconductor device includes a metal silicide layer 105. The metal silicide layer 105 is arranged on the active area 103 and the gate 104, and the material of the metal silicide layer 105 is, for example, nickel silicide (NiSi). Specifically, an alloy layer, such as a nickel-platinum alloy layer, can be formed on the wafer silicon substrate 101 or the active area 103. Annealing is then performed so that the nickel in the nickel-platinum alloy layer reacts with the silicon in the polysilicon in the active area 103 and the gate 104 to form the metal silicide layer 105. When connecting the metal interconnect layer 109 and the active area 103 or the gate 104, the high conductivity of the silicide material in the active area 103 and the gate 104 is utilized to form a low resistance connection between the metal interconnect layer 109 and the semiconductor device in the wafer silicon substrate 101.

[0033] See also Figures 1 to 3 As shown, in one embodiment of the present invention, a multilayer stacked film is formed on a wafer silicon substrate 101 and a semiconductor device, including a contact hole etching stacked film. The contact hole etching stacked film includes a first etching stop layer (Etch Stop Layer, ESL) 106 and a contact hole dielectric layer 107. The first etching stop layer 106 is disposed on the metal silicide layer 105 and the wafer silicon substrate 101, and the material of the first etching stop layer 106 can be a material such as silicon nitride with high stress. The contact hole dielectric layer 107 is disposed on the first etching stop layer 106, and the material of the contact hole dielectric layer 107 is, for example, silicon oxide. A first photoresist layer 110 is also disposed on the contact hole etching stacked film, and the first photoresist layer 110 is used to define the position of the contact hole 1081. When etching the contact hole etching stacked film to form the contact hole 1081, the first etching is performed first. The first etching uses reactive ion etching (RIE) to etch the contact hole dielectric layer 107 and stops on the first etching stop layer 106. Then, a second etching is performed, and a gas different from that of the first etching is used to etch the first etching stopper layer 106. The etching rate of the gas of the first etching on the contact hole dielectric layer 107 is much higher than that on the first etching stopper layer 106, and the etching rate of the gas of the second etching on the first etching stopper layer 106 is much higher than that on the metal silicide layer 105.

[0034] See also Figures 1 to 3As shown, in one embodiment of the present invention, after the etching of the first etching stopper layer 106 is completed, the second etching gas is used to continue etching the surface of the metal silicide layer 105, and a portion of the metal silicide layer 105 is etched away, that is, the metal silicide layer 105 is overetched, that is, the contact hole 1081 is overetched. Since the thickness of the first etching stopper layer 106 on different wafer silicon substrates 101 is different, if the metal silicide layer 105 is not overetched, not all contact holes 1081 can stop accurately on the upper surface of the first etching stopper layer 106. Therefore, it is necessary to overetch the metal silicide layer 105 to ensure that the contact hole 1081 is in contact with the metal silicide layer 105. When the metal silicide layer 105 is overetched, if the overetching is insufficient, the residue of the first etching stopper layer 106 will remain on the top of the metal silicide layer 105, causing an open circuit failure. If the over-etching is excessive, the metal silicide layer 105 will be over-consumed due to the thinness of the metal silicide layer 105, resulting in high contact resistance failure. Therefore, during the over-etching process of the contact hole 1081, the over-etching depth of the contact hole 1081 needs to be monitored.

[0035] See also Figures 1 to 5 As shown, in one embodiment of the present invention, the metal interconnect layer 109 includes a stacked metal layer 114 and a through-hole etched stacked film. Among them, the metal layer 114 includes a metal wire layer 1141 and an intermetallic dielectric layer 1142. The metal wire layer 1141 can be a patterned metal wire layer 1141 formed of a metal such as copper, and the intermetallic dielectric layer 1142 is arranged between the metal wire layers 1141 to isolate the metal wire layers 1141 of the same layer. The intermetallic dielectric layer 1142 arranged between the metal wire layers 1141 can prevent the patterned metal wire layers 1141 of the same layer from contacting each other and causing a short circuit. The intermetallic dielectric layer 1142 can be formed of an oxide material such as silicon oxide or other materials with a low dielectric constant.

[0036] See also Figures 1 to 5As shown, in one embodiment of the present invention, the through-hole etching stack film is located between two adjacent metal layers 114 or between the metal layer 114 and the semiconductor device on the wafer silicon substrate 101, and can isolate the two adjacent metal layers 114, or isolate the metal layer 114 and the semiconductor device. The through-hole etching stack film generally includes a second etching barrier layer 111 and a through-hole dielectric layer 112. The material of the second etching barrier layer 111 can be a material such as silicon nitride with high stress, and the through-hole dielectric layer 112 is silicon oxide. A second photoresist layer 115 is also provided on the through-hole etching stack film, and the second photoresist layer 115 is used to define the position of the through hole 1131. Through holes 1131 are formed between adjacent metal interconnection layers 109. The through holes 1131 also need to pass through the through-hole etching stack film, connect with the metal wire layer 1141, and over-etch the metal wire layer 1141, that is, over-etching of the through holes 1131, to ensure effective electrical connection between adjacent metal interconnection layers 109.

[0037] See also Figures 1 to 5 As shown, since the thickness of the metal silicide layer 105 and the metal wire layer 1141 is relatively small, the over-etching thickness of the contact hole 1081 and the through hole 1131 is even smaller. However, the optical method can only detect the overall depth of the contact hole 1081 or the through hole 1131. Due to the error between the thickness of each layer, the over-etching degree of the contact hole 1081 and the through hole 1131 cannot be accurately detected. If the over-etching thickness of the contact hole 1081 and the through hole 1131 is measured by a transmission electron microscope (TEM), it will damage the wafer and is not suitable for wafer production. The present application provides a measurement structure for a contact / through hole etching process, which can effectively and non-destructively monitor the over-etching degree of the contact hole / through hole, correct the errors generated during the etching process, and ensure the quality of the formed product.

[0038] See also Figures 6 to 9As shown, the measurement structure of the contact / through hole etching process provided by the present invention includes a first test pad 201 and a second test pad 202, wherein the first test pad 201 includes an etching stack film, the second test pad 202 includes a monitoring dielectric layer and an etching stack film, and the first test pad 201 is arranged on the insulating dielectric layer, and the second test pad 202 is arranged on the wafer silicon substrate 101. Wherein, the etching stack film includes an etching barrier layer and a contact hole / through hole dielectric layer arranged on the etching barrier layer. A first contact / through hole array is arranged on the first test pad 201, and a second contact / through hole array is arranged on the second test pad 202. The first contact / through hole array includes a plurality of first contacts / through holes 2011 arranged in an array, and the first contact / through hole 2011 passes through the etching stack film to the insulating dielectric layer, and the second contact / through hole array includes a plurality of second contacts / through holes 2021 arranged in an array, and the second contact / through hole 2021 passes through the etching stack film to the monitoring dielectric layer. The first contact / through hole 2011 and the second contact / through hole 2021 are etched synchronously, and the etching rate of the insulating dielectric layer in the first contact / through hole 2011 is much greater than the etching rate of the monitoring dielectric layer in the second contact / through hole 2021. Finally, the difference in depth between the first contact / through hole 2011 and the second contact / through hole 2021 is the contact / through hole over-etching monitoring result. Among them, the monitoring dielectric layer is the semiconductor layer over-etched by the contact hole 1081 or the through hole 1131, that is, the metal silicide layer 105 or the metal wire layer 1141. The insulating dielectric layer and the semiconductor layer in the etching stack film are specifically set according to the positions of the first test pad 201 and the second test pad 202.

[0039] See also Figures 1 to 7As shown, in one embodiment of the present invention, when the measurement structure is used to measure the contact hole 1081, the first test pad 201 is located on the shallow trench isolation structure 102, and the second test pad 202 is located on the active area 103. At this time, the monitoring dielectric layer is the metal silicide layer 105, and the insulating dielectric layer is the silicon oxide layer in the shallow trench isolation, that is, the shallow trench isolation structure 102. The etched stacked film is a contact hole etched stacked film. Among them, the contact hole etched stacked film includes a first etching barrier layer 106 and a contact hole dielectric layer 107. At this time, when the first test pad 201 and the second test pad 202 are etched synchronously, a first contact / through hole 2011 is formed on the first test pad 201, and a second contact / through hole 2021 is formed on the second test pad 202, the etching speeds of the etched stacked films on the two test pads are equal. When the over-etching is performed, when the metal silicide layer 105 in the second test pad 202 is slowly etched, the etching rate of the shallow trench isolation structure 102 in the first test pad 201 is much greater than the etching rate of the metal silicide layer 105, so the shallow trench isolation structure 102 in the first test pad 201 is etched faster. At this time, the difference between the depth of the first contact / via 2011 and the depth of the second contact / via 2021 is proportional to the over-etching level, so the difference between the depth of the first contact / via 2011 and the depth of the second contact / via 2021 can be used to obtain the contact / via over-etching monitoring result, that is, to monitor the over-etched thickness of the dielectric layer.

[0040] See also Figures 1 to 7As shown, in one embodiment of the present invention, the difference between the depth of the first contact / through hole 2011 and the depth of the second contact / through hole 2021 is the difference between the etching depth of the shallow trench isolation structure 102 in the first test pad 201 and the etching depth of the metal silicide layer 105 in the second test pad 202. In the present application, the monitoring dielectric layer is a conductive metal material. When the shallow trench isolation structure 102 and the metal silicide layer 105 are synchronously etched using the gas for etching the first etching barrier layer 106, the ratio of the etching rate of the insulating dielectric layer (shallow trench isolation structure 102) to the etching rate of the monitoring dielectric layer (metal silicide layer 105) is greater than 10, that is, the etching selectivity ratio of the insulating dielectric layer (shallow trench isolation structure 102) and the monitoring dielectric layer (metal silicide layer 105) is greater than 10. Therefore, relative to the etching depth of the shallow trench isolation structure 102 in the first test pad 201, the etching depth of the metal silicide layer 105 in the second test pad 202 is very small. When the etching depth of the metal silicide layer 105 increases, the difference between the depth of the first contact / via 2011 and the depth of the second contact / via 2021 also gradually increases. Specifically, when the etching depth of the metal silicide layer 105 is zero, the etching depth of the shallow trench isolation structure 102 is equal to zero, and the difference between the depth of the first contact / via 2011 and the depth of the second contact / via 2021 is equal to zero. As the etching depth of the metal silicide layer 105 gradually increases, the etching depth of the shallow trench isolation structure 102 also gradually increases, and the difference between the etching depth of the shallow trench isolation structure 102 and the etching depth of the metal silicide layer 105 is approximately equal to the etching depth of the shallow trench isolation structure 102, that is, the difference between the etching depth of the shallow trench isolation structure 102 and the etching depth of the metal silicide layer 105 also gradually increases. When the metal silicide layer 105 is completely etched, the etching depth of the shallow trench isolation structure 102 is the maximum, which is the first preset depth. At this time, the difference between the depth of the first contact / via 2011 and the depth of the second contact / via 2021 is the maximum, which is the first preset depth minus the thickness of the metal silicide layer 105. Therefore, the difference between the depth of the first contact / via 2011 and the depth of the second contact / via 2021 can be used as the contact / via over-etching monitoring result. When the metal silicide layer 105 in the second contact / via 2021 is etched, the shallow trench isolation structure 102 in the first contact / via 2011 is etched, and as the etching depth of the metal silicide layer 105 increases, the difference between the etching depth of the shallow trench isolation structure 102 and the etching depth of the metal silicide layer 105 gradually increases.

[0041] See also Figures 1 to 5 ,as well as Figure 8 and Fig. 9As shown, in another embodiment of the present invention, when the measurement structure is used to measure the through hole 1131, the first test pad 201 is located on the intermetallic dielectric layer 1142, that is, on the low-k silicon oxide layer deposited on the surface of the wafer silicon substrate 101, and the second test pad 202 is located on the metal wire layer 1141. At this time, the monitoring dielectric layer is the metal wire layer 1141, and the insulating dielectric layer is the intermetallic dielectric layer 1142, that is, the low-k insulating dielectric layer deposited on the surface of the wafer silicon substrate 101, that is, the low-k silicon oxide layer. The etched stacked film is a through-hole etched stacked film. Among them, the through-hole etched stacked film includes a second etching barrier layer 111 and a through-hole dielectric layer 112. At this time, when the through-hole dielectric layer 112 and the second etching barrier layer 111 in the first test pad 201 and the second test pad 202 are synchronously etched to form a first contact / through hole 2011 on the first test pad 201 and a second contact / through hole 2021 on the second test pad 202, the etching speeds of the etched stacked films on the two test holes are equal. When the metal wire layer 1141 and the intermetallic dielectric layer 1142 are overetched by using the gas for etching the second etching barrier layer 111, when the metal wire layer 1141 in the second test pad 202 is slowly etched, the etching rate of the intermetallic dielectric layer 1142 in the first test pad 201 is much greater than the etching rate of the metal wire layer 1141, so the intermetallic dielectric layer 1142 in the first test pad 201 is etched faster. At this time, the difference between the depth of the first contact / via 2011 and the depth of the second contact / via 2021 is proportional to the overetching level, so the difference between the depth of the first contact / via 2011 and the depth of the second contact / via 2021 can be used to obtain the contact / via overetching monitoring result, that is, to monitor the overetched thickness of the dielectric layer.

[0042] See also Figures 1 to 5 ,as well as Figure 8 and Fig. 9As shown, in another embodiment of the present invention, the difference between the depth of the first contact / through hole 2011 and the depth of the second contact / through hole 2021 is the difference between the etching depth of the intermetallic dielectric layer 1142 in the first test pad 201 and the etching depth of the metal wire layer 1141 in the second test pad 202. In the present application, the monitoring dielectric layer is a conductive metal material, and when the metal wire layer 1141 and the intermetallic dielectric layer 1142 are synchronously etched using the gas for etching the second etching barrier layer 111, the ratio of the etching rate of the insulating dielectric layer (intermetallic dielectric layer 1142) to the etching rate of the monitoring dielectric layer (metal wire layer 1141) is greater than 10, that is, the etching selectivity ratio of the insulating dielectric layer (intermetallic dielectric layer 1142) and the monitoring dielectric layer (metal wire layer 1141) is greater than 10. Therefore, relative to the etching depth of the intermetallic dielectric layer 1142 in the first test pad 201, the etching depth of the metal wire layer 1141 in the second test pad 202 is very small, so when the etching depth of the metal wire layer 1141 increases, the difference between the depth of the first contact / via 2011 and the depth of the second contact / via 2021 also gradually increases. Specifically, when the etching depth of the metal wire layer 1141 is zero, the depth of the intermetallic dielectric layer 1142 is equal to zero, and the difference between the depth of the first contact / via 2011 and the depth of the second contact / via 2021 is equal to zero. As the etching depth of the metal wire layer 1141 gradually increases, the etching depth of the intermetallic dielectric layer 1142 also gradually increases, and the difference between the etching depth of the intermetallic dielectric layer 1142 and the etching depth of the metal wire layer 1141 is approximately equal to the etching depth of the intermetallic dielectric layer 1142, that is, the difference between the etching depth of the intermetallic dielectric layer 1142 and the etching depth of the metal wire layer 1141 also gradually increases. When the metal wire layer 1141 is completely etched, the etching depth of the intermetallic dielectric layer 1142 is the maximum, which is the second preset depth. At this time, the difference between the depth of the first contact / via 2011 and the depth of the second contact / via 2021 is the maximum, which is the second preset depth minus the thickness of the metal wire layer 1141. Therefore, the difference between the depth of the second contact / via 2021 and the first contact / via 2011 can be used as the through-hole over-etching monitoring result. When the metal wire layer 1141 in the second contact / via 2021 is etched, the intermetallic dielectric layer 1142 in the first contact / via 2011 is etched, and as the etching depth of the metal wire layer 1141 increases, the difference between the etching depth of the intermetallic dielectric layer 1142 and the etching depth of the metal wire layer 1141 gradually increases.

[0043] See also Figures 6 to 9 As shown, in some embodiments, the first contact / via 2011 may also extend into the via dielectric layer 112. Both the via dielectric layer 112 and the intermetallic dielectric layer 1142 are low-k silicon oxide layers. Therefore, the via dielectric layer 112 can also be used as an insulating dielectric layer.

[0044] See also Figures 6 to 9 As shown, in the embodiment provided by the present invention, in order to ensure that the first test pad 201 and the second test pad 202 do not affect the formation of the semiconductor device in the integrated circuit, the first test pad 201 and the second test pad 202 are arranged on the scribing line. The size of the first test pad 201 and the second test pad 202 is equal to or greater than, for example, 50um×50um, and the spacing between the centers of the first test pad 201 and the second test pad 202 is, for example, 50um~1mm. At this time, it can be avoided that the spacing between the first test pad 201 and the second test pad 202 is too large, resulting in a large difference in the thickness of each film in the first test pad 201 and the second test pad 202, resulting in the difference between the depth of the first contact / through hole 2011 and the depth of the second contact / through hole 2021 cannot be used as a standard for measuring over-etching.

[0045] See also Figures 6 to 9 As shown, in the embodiment provided by the present invention, on the first test pad 201 and the second test pad 202, the number of the first contact / via 2011 and the second contact / via 2021 is set according to the requirements. Specifically, the first contact / via array includes n×m first contacts / vias 2011, and the second contact / via array includes n×m second contacts / vias 2021, wherein the values ​​of n and m are integers ranging from tens to tens of thousands, and n and m may be equal or unequal. The first contact / via array in the figure includes 3×3 first contacts / vias 2011, and the second contact / via array includes 3×3 second contacts / vias 2021, which is only a schematic diagram of the contact / via array.

[0046] See also Figures 6 to 9 As shown, in the embodiment provided by the present invention, when the measurement structure provided by the present application is used to monitor the over-etched thickness of the monitoring dielectric layer of the contact hole / through hole, the depth of the first contact / through hole 2011 in the first test pad and the second contact / through hole 2021 in the second test pad can be measured by a scattering measurement method (such as optical critical dimension OCD), and then the difference in depth between the second contact / through hole 2021 and the first contact / through hole 2011 is obtained, and the difference in depth between the second contact / through hole 2021 and the first contact / through hole 2011 is used to monitor the over-etched thickness of the monitoring dielectric layer of the contact hole / through hole.

[0047] See also Figures 6 to 9As shown, in the embodiment provided by the present invention, the gas for etching the contact hole dielectric layer 107 and the through hole dielectric layer 112, the gas for etching the first etching stopper layer 106 and the second etching stopper layer 111, and the etching gas for the monitoring dielectric layer and the insulating dielectric layer are not limited. Specifically, the etching gas for the contact hole dielectric layer 107, the through hole dielectric layer 112, the first etching stopper layer 106, the second etching stopper layer 111, the monitoring dielectric layer and the insulating dielectric layer can all be fluorine-containing gases, and the fluorine content can be adjusted according to the specific material of each semiconductor layer.

[0048] In summary, the present invention provides a measurement structure, monitoring method and semiconductor structure for a contact / through hole etching process, wherein the measurement structure for the contact / through hole etching process includes a first test pad and a second test pad, the first test pad includes an etching barrier layer and a contact hole / through hole dielectric layer, and the first test pad is provided with a first contact / through hole array. The second test pad includes a monitoring dielectric layer, an etching barrier layer and a contact hole / through hole dielectric layer, and the second test pad is provided with a second contact / through hole array. Wherein, the first test pad is arranged on an insulating dielectric layer, and the depth of the first contact / through hole array extends into the insulating dielectric layer. The second test pad is arranged on a wafer silicon substrate layer, and the depth of the second contact / through hole array extends to the monitoring dielectric layer, and the first test pad and the second test pad are arranged adjacent to each other. When using the measurement structure for the contact / through hole etching process provided by the present application to monitor the over-etched thickness of the monitoring dielectric layer of the contact hole / through hole, the depth of the contact / through hole in the first contact / through hole array in the first test pad is first optically measured, and then the depth of the contact / through hole in the second contact / through hole array in the second test pad is optically measured. The difference between the contact / through-hole depth of the first contact / through-hole array and the contact / through-hole depth of the second contact / through-hole array is obtained, and the thickness of the over-etched monitoring dielectric layer is measured based on the depth difference and the difference in etching rates between the monitoring dielectric layer and the insulating dielectric layer. It can avoid damage to semiconductor devices caused by measurement, and it can also avoid the over-etching depth being too small to measure, thereby efficiently and non-destructively obtaining the degree of contact / through-hole over-etching. The measurement structure, monitoring method and semiconductor structure of a contact / through-hole etching process provided in the present application can accurately monitor the thickness of contact / through-hole over-etching without destroying the semiconductor structure.

[0049] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A measurement structure for a contact / through hole etching process, wherein the measurement structure is arranged in a dicing path of a wafer, characterized in that: And the measurement structure includes: A first test pad, comprising an etch stop layer and a contact hole / through hole dielectric layer, wherein the first test pad is provided with a first contact / through hole array; and A second test pad, comprising a monitoring dielectric layer, an etching barrier layer and a contact hole / through hole dielectric layer, wherein the second test pad is provided with a second contact / through hole array; Among them, the first test pad is arranged on the insulating dielectric layer, and the depth of the first contact / through-hole array extends into the insulating dielectric layer; the second test pad is arranged on the wafer silicon substrate layer, and the depth of the second contact / through-hole array extends to the monitoring dielectric layer; the first test pad and the second test pad are arranged adjacent to each other.

2. The measurement structure according to claim 1, characterized in that: The monitoring medium layer is made of a conductive metal material, and an etching selectivity ratio between the insulating medium layer and the monitoring medium layer is greater than 10.

3. The measurement structure according to claim 1, characterized in that: When the measurement structure is used to measure a contact hole, the insulating dielectric layer is a silicon oxide layer in a shallow trench in a silicon substrate of a wafer.

4. The measurement structure according to claim 1, characterized in that: When the measurement structure is used to measure a contact hole, the monitoring medium layer is a metal silicide layer.

5. The measurement structure according to claim 1, characterized in that: When the measurement structure is used to measure a through hole, the monitoring medium layer is a metal wire layer.

6. The measurement structure according to claim 1, characterized in that: When the measurement structure is used to measure a through hole, the insulating dielectric layer is a low-k silicon oxide layer deposited on the surface of a wafer silicon substrate.

7. The measurement structure according to claim 1, characterized in that: The distance between the centers of the first test pad and the second test pad ranges from 50 um to 1 mm.

8. The measurement structure according to claim 1, characterized in that: The size of the first test pad and the second test pad is equal to or greater than 50 um×50 um.

9. A method for monitoring a measurement structure as claimed in claim 1, characterized in that: The measuring structure is used to monitor the over-etching thickness of the monitoring dielectric layer of the contact hole / through hole, and the monitoring method includes: optically measuring the depth of contacts / vias in the first array of contacts / vias in the first test pad; optically measuring the depth of contacts / vias in the second array of contacts / vias in the second test pad; The difference between the contact / via depth of the first contact / via array and the contact / via depth of the second contact / via array is obtained, and the over-etched thickness of the monitoring dielectric layer is obtained based on the depth difference and the etching rate difference between the monitoring dielectric layer and the insulating dielectric layer.

10. A semiconductor structure, characterized in that: A measurement structure for a contact / via etching process comprising any one of claims 1 to 8.

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