Capacitor structure with fin-shaped structure and manufacturing method thereof
By forming ion-doped regions in the substrate under the fin structure and setting a non-uniform doping distribution, the problem of fin structure being susceptible to erosion after the ion-doping and annealing steps is solved, and the quality of the capacitance structure and the yield of the production process are improved.
Patent Information
- Application Number
- CN202311514507.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-10-25
- Filing Date
- 2023-11-14
- Publication Date
- 2025-04-25
AI Technical Summary
In the prior art, fin structures are susceptible to erosion by specific doped ion species after the ion doping and annealing steps, resulting in a decrease in the quality of the capacitance structure and an increase in leakage current.
Ion-doped regions are formed in the substrate below the fin structure, and the doped ion species are set to be non-uniformly distributed to avoid direct doping of ions into the fin structure, thereby reducing the damage to the fin structure by the annealing step.
By setting the ion-doped region in the substrate below the fin structure, the damage of the doped ions on the fin structure is reduced, and the quality of the capacitance structure and the yield of the production process are improved.
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Figure CN119890196A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a capacitor structure with a fin-shaped structure and a manufacturing method thereof, which has a high manufacturing process yield. Background Art
[0002] In the current semiconductor integrated circuit manufacturing process, most of them still use traditional planar capacitors connected to a metal oxide semiconductor (MOS) transistor to form a memory element. The traditional planar capacitor is composed of a three-layer planar stacked structure consisting of a lower electrode plate, a capacitor dielectric layer and an upper electrode plate. During its production, it not only requires three photomasks to define the patterns of each layer respectively, but also because its planar stacked structure requires a large circuit design area (chip area) to meet the design capacitance requirements, so how to reduce the space required to define the capacitor structure on the die (that is, increase the capacitance density), improve the component integration, and reduce the number of photomasks used to reduce production costs, has become a research and development focus when making capacitor structures.
[0003] In order to increase the density of capacitors, the current technology integrates the fin structure into the capacitor structure to form a three-dimensional capacitor structure. Figure 1 , which shows a cross-sectional schematic diagram of a conventional three-dimensional capacitor structure. Figure 1 As shown, a substrate 10 is provided, and the substrate 10 includes a fin structure F, wherein the material of the fin structure F is the same as that of the substrate 10, such as silicon. Then, the fin structure F is ion doped to form a doping region 11 in the fin structure F to reduce the resistance of the fin structure F, so that the fin structure F can be used as the lower electrode of the capacitor formed subsequently. Subsequently, an insulating layer 12 (such as silicon oxide, which can be formed by a thermal oxidation process) and an upper electrode layer 14 are formed in sequence above the fin structure, wherein the upper electrode layer 14 can include a work function metal layer and a conductive layer, etc. Therefore, the upper electrode 14, the insulating layer 12 and the doped fin structure F (used as the lower electrode) can constitute a three-dimensional capacitor structure.
[0004] However, in the actual manufacturing process, after the ions are doped in the fin structure F, an annealing step is performed to make the doped ions diffuse evenly throughout the entire fin structure F. The applicant has found that some specific types of doped ions combined with the annealing step may cause damage to the fin structure F. Please refer to Figure 2 , which shows a cross-sectional schematic diagram of a conventional three-dimensional capacitor structure after an annealing step. Figure 2 As shown, if the ion species doped in the fin structure F is arsenic (As) or phosphorus (P), the fin structure F is easily corroded after the annealing step, which may cause the shape of the fin structure F to change (for example, Figure 2As shown, the top surface of the fin structure F is made sharper). This is not conducive to the quality of the capacitor structure and may increase the leakage current of the capacitor structure.
[0005] Therefore, it is necessary to study a capacitor structure that can solve the above problems. Summary of the invention
[0006] The present invention provides a capacitor structure with a fin structure, comprising a fin structure located on a substrate, a lower electrode layer, a high dielectric constant layer and an upper electrode layer stacked in sequence on the fin structure, and an ion doping region located in the substrate below the fin structure, and a top surface of the ion doping region is flush with a bottom surface of the fin structure.
[0007] The present invention further provides a method for forming a capacitor structure including a fin-shaped structure, comprising forming a fin-shaped structure located on a substrate, forming a lower electrode layer, a high dielectric constant layer and an upper electrode layer stacked in sequence on the fin-shaped structure, and forming an ion-doped region located in the substrate below the fin-shaped structure, and a top surface of the ion-doped region is flush with a bottom surface of the fin-shaped structure.
[0008] The present invention is characterized in that it provides a three-dimensional capacitor structure including a fin-shaped structure, wherein a three-layer structure including a lower electrode layer-dielectric layer-upper electrode layer is directly formed on the fin-shaped structure, thereby making a three-dimensional capacitor structure. In addition, in order to reduce the damage of ions to the fin-shaped structure, the ion doping region is set in the substrate below the fin-shaped structure, and the ion doping concentration in the fin-shaped structure is non-uniformly distributed (the closer to the top, the lower the ion concentration). The lower electrode of the capacitor of the present invention is connected to the lower electrode contact structure through the ion doping region and the epitaxial layer, and the upper electrode contact structure does not overlap with the lower electrode layer in the cross-sectional view, which can reduce the difficulty of the manufacturing process and improve the yield. BRIEF DESCRIPTION OF THE DRAWINGS
[0009] Figure 1 is a cross-sectional schematic diagram of an existing three-dimensional capacitor structure;
[0010] Figure 2 is a cross-sectional schematic diagram of a conventional three-dimensional capacitor structure after an annealing step;
[0011] Figure 3 A schematic top view of a capacitor structure including a fin-shaped structure and a transistor structure according to a first preferred embodiment of the present invention;
[0012] Figure 4 for Figure 3 A schematic diagram of the cross-sectional structure obtained along the section line A-A' and the section line B-B';
[0013] Figure 5 For continuation Figure 4A schematic diagram of a cross-sectional structure of a conductive layer and a contact structure is formed by continuing to form the structure;
[0014] Figure 6 It is a schematic cross-sectional structure diagram of another embodiment of the present invention.
[0015] Explanation of symbols
[0016] 10: Base
[0017] 11: Doping area
[0018] 12: Insulation layer
[0019] 14: Upper electrode layer
[0020] 16: Ion doping area
[0021] 18: Dielectric layer
[0022] 19: Gap wall
[0023] 20: Lower electrode layer
[0024] 22: Dielectric layer
[0025] 24: Upper electrode layer
[0026] 26: Conductive layer
[0027] CT1: Contact structure
[0028] CT2: Contact structure
[0029] F: Fin structure
[0030] G: Gate
[0031] MD: Bottom electrode contact structure
[0032] MP: Upper electrode contact structure
[0033] R1: Region
[0034] R2: Groove
[0035] STI: Shallow Trench Isolation DETAILED DESCRIPTION
[0036] In order to enable a person skilled in the art to further understand the present invention, the preferred embodiments of the present invention are listed below, and the components and intended effects of the present invention are described in detail with reference to the accompanying drawings.
[0037] For the convenience of explanation, the drawings of the present invention are only for illustration to make it easier to understand the present invention, and the detailed proportions can be adjusted according to the design requirements. The upper and lower relationships of the relative elements in the drawings described in the text should be understood by those skilled in the art to refer to the relative positions of the objects, so they can be flipped to present the same components, which should all fall within the scope of the disclosure of this specification, and will be explained here first.
[0038] Figure 3 A schematic top view of a capacitor structure including a fin structure and a transistor structure according to a first preferred embodiment of the present invention is shown. Figure 4 Draw Figure 3 The schematic diagram of the cross-sectional structure obtained along the section line A-A' and the section line B-B'. Figure 3 and Figure 4 As shown, the left half of the figure shows a top view and a cross-sectional view of a capacitor structure, while the right half shows a top view and a cross-sectional view of a transistor structure. In the present invention, the capacitor structure can be integrated into the manufacturing process of the transistor structure, that is, the two will have some similar or identical manufacturing processes. Therefore, the capacitor structure can be formed while forming the transistor structure.
[0039] It is worth noting that Figure 3 The capacitor structure and transistor structure are both located on the substrate 10. The two may be adjacent to each other or located in different regions far away from each other. Alternatively, in some embodiments, no transistor region may be formed. All of the above variations are within the scope of the present invention.
[0040] like Figure 3 and Figure 4 As shown, a substrate 10 includes a plurality of fin structures F, and a shallow trench isolation STI is located next to the fin structure F on the substrate 10. The material of the substrate 10 and the fin structure F is, for example, silicon, and the material of the shallow trench isolation STI is, for example, silicon oxide, but is not limited thereto. Next, a region R1 is defined on the substrate 10, and an ion doping step is performed in the region R1 to dope, for example, arsenic (As) or phosphorus (P) ions into the substrate 10, especially to dope ions into part of the fin structure F, but the ions are only doped into the region R1 of the capacitor structure (left half), and are not doped into the fin structure F in the transistor structure (right half). It is worth noting that, as Figure 4 As shown, in order to avoid the situation described in the prior art that arsenic (As) or phosphorus (P) ions will damage the fin structure F after the doping and annealing steps, the present embodiment controls the depth of the ion doping step so that the ion doping region 16 after the doping step is formed below the fin structure F, preferably in the substrate 10 below the fin structure F, and not in the fin structure F. More preferably, the top surface of the ion doping region 16 and the bottom surface of the fin structure F (i.e. Figure 4The top surface of the substrate 10 is aligned with the top surface of the substrate 10, and the doped ion species include arsenic (As) or phosphorus (P) ions.
[0041] In addition, after the fin structure F is formed on the substrate 10, a polysilicon gate (not shown) and a dielectric layer 18 are first formed to cover the substrate 10, and after the polysilicon gate is removed, a groove (i.e. Figure 3 The region R2 in the groove or the position of the gate G). Subsequently, a material layer required for the capacitor structure, such as a lower electrode, an insulating layer, and an upper electrode, will be formed in the groove.
[0042] In addition, after the polysilicon gate is completed, an epitaxial manufacturing process can be formed on the surface of the fin structure F, and an epitaxial layer such as silicon germanium (SiGe) or silicon phosphide (SiP) can be formed on the surface of the fin structure. The epitaxial layer formed here is used to connect the lower electrode and contact structure formed subsequently. Figure 3 From this perspective, the epitaxial layer should be formed on the surface of the fin structure except for the gate G, but it is not drawn for the sake of simplicity in the drawing.
[0043] A spacer 19 may be formed within the range of the groove R2 to cover the sidewall of the groove R2. The purpose of forming the spacer 19 is to protect the inner sidewall surface of the groove R2. Meanwhile, the lower electrode layer formed subsequently will cover the spacer 19. Therefore, if an appropriate material is selected for the spacer 19, the adhesion between the lower electrode layer and the spacer 19 can be improved. In the present embodiment, the material of the spacer 19 may include silicon oxide, silicon nitride or silicon oxynitride, but is not limited thereto.
[0044] Next, please continue to refer to Figure 3 and Figure 4, a lower electrode layer 20, a dielectric layer 22 and an upper electrode layer 24 are continuously formed in the groove R2 in the capacitor structure (left half), and a dielectric layer 22 and an upper electrode layer 24 are formed in the transistor structure (right half). The material of the lower electrode layer 20 and the upper electrode layer 24 is, for example, titanium nitride (TiN) or tantalum nitride (TaN), but is not limited thereto, and other types of metal layers or work function metal layers can also be used to make the lower electrode layer 20 and the upper electrode layer 24 of the present invention. The dielectric layer 22 includes, for example, a high dielectric constant layer, which may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or a dielectric material having a dielectric constant greater than 4, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconate (HfZrO4), oxide, HfZrO4), strontium bismuth tantalate (SrBi2Ta2O9, SBT), lead zirconate titanate (PbZrxTi1-xO3, PZT), barium strontium titanate (BaxSr1-xTiO3, BST), or a combination thereof.
[0045] In the present invention, the capacitor structure includes a lower electrode layer 20, a dielectric layer 22 and an upper electrode layer 24, so the three-layer structure constitutes a capacitor structure. As for the dielectric layer 22 included in the transistor structure, it can be used as a gate dielectric layer, and the upper electrode layer 24 can be used as a work function layer or a barrier layer of the gate formed subsequently. The lower electrode layer 20 is not included in the transistor structure.
[0046] It is worth noting that compared with Figure 1 or Figure 2In the conventional three-dimensional capacitor structure shown in FIG. 1 , the ion doping region 16 of this embodiment is formed in the substrate 10 below the fin structure F. Therefore, after the annealing step, the ion concentration decreases from the center of the ion doping region 16 to the outside and presents a Gaussian distribution. Only a small amount of ions will diffuse into the inside of the fin structure F. Therefore, it will not cause the Figure 2 In other words, in this embodiment, the ion doping depth is controlled during the doping step so that the ion doping region 16 is away from the top surface of the fin structure F, so that after the annealing step, the damage of the arsenic ions or phosphorus ions to the fin structure F can be reduced.
[0047] In addition, Figure 1 or Figure 2 In the conventional three-dimensional capacitor structure shown, the fin structure F body doped with ions is used as the lower electrode of the capacitor structure. In this embodiment, in order to prevent the fin structure F from being damaged by ions, ions are not doped into the complete fin structure, and an additional lower electrode layer 20 is formed to be used as the lower electrode of the capacitor structure. Therefore, in the structure of this embodiment, the upper part of the fin structure F still includes the lower electrode layer 20, the dielectric layer 22 and the upper electrode layer 24, instead of Figure 1 and Figure 2 In the structure shown, only the insulating layer 12 and the upper electrode 14 are located on the fin structure F.
[0048] besides, Figure 3 In the capacitor structure (left half), a lower electrode contact structure MD and an upper electrode contact structure MP are additionally formed, wherein the upper electrode contact structure MP is located within the range of the groove R2 (i.e., the original formation position of the polysilicon gate), and is used to electrically connect the upper electrode layer 24 of the capacitor structure, while the lower electrode contact structure MD is formed on the fin structure F, and is used to electrically connect the epitaxial layer and the ion doping region 16, and further electrically connected to the lower electrode layer 20. In other words, the upper electrode and the lower electrode of the capacitor structure are electrically connected to the contact structure MP and the contact structure MD, respectively. As for the transistor structure (right half), the contact structure CT1 is similar to the upper electrode contact structure MP, but it is used to connect the gate G of the transistor, and the contact structure CT2 is similar to the lower electrode contact structure MD, but it is used to connect the source / drain of the transistor.
[0049] Figure 5 Draw Continuation Figure 4 The structure of the conductive layer and the contact structure is further formed. Figure 5As shown, from the cross-sectional view, the conductive layer 26 is, for example, tungsten, which can be formed and fill the groove R2, and the conductive layer 26 can be used as the gate structure of the transistor part. In addition, the upper electrode contact structure MP is located directly above the upper electrode layer 24, but the dielectric layer 22 and the lower electrode layer 20 are not located directly below the upper electrode contact structure MP. As described above, the lower electrode layer 20 is electrically connected to the lower electrode contact structure MD through the ion doping region 16 and the epitaxial layer, so there is no need to form a contact structure above the capacitor structure to electrically connect the lower electrode layer 20. In other words, in this embodiment, the upper electrode contact structure MP (i.e., the contact structure electrically connected to the upper electrode layer 24) and the lower electrode layer 20 do not overlap each other in the cross-sectional view, which can avoid the contact structure MP from touching the lower electrode layer 20 when the upper electrode layer 24 is etched due to excessive etching. In this way, the stability and yield of the manufacturing process can be improved.
[0050] Figure 6 A schematic cross-sectional view of another embodiment of the present invention is shown, wherein most structures are similar to Figure 5 , so the repeated parts are not repeated. The characteristic of this embodiment is that after the upper electrode layer 24 and the conductive layer 26 are completed, a planarization step can be performed to remove the redundant material layer, and the upper electrode contact structure MP and the contact structure CT1 formed subsequently are directly in contact with the conductive layer 26. Because of the planarization step, the top surface of the conductive layer 26 of the capacitor structure (left half) and the transistor structure (right half) are aligned. This embodiment also falls within the scope of the present invention.
[0051] In summary, the present invention provides a capacitor structure with a fin structure, comprising a fin structure F located on a substrate 10, a lower electrode layer 20, a high dielectric constant layer (dielectric layer 22) and an upper electrode layer 24 stacked in sequence on the fin structure F, and an ion-doped region 16 located in the substrate 10 below the fin structure F, and a top surface of the ion-doped region 16 is flush with a bottom surface of the fin structure F.
[0052] The present invention further provides a method for forming a capacitor structure including a fin structure, comprising forming a fin structure F located on a substrate 10, forming a lower electrode layer 20, a high dielectric constant layer 22 and an upper electrode layer 24 stacked in sequence on the fin structure, and forming an ion doping region 16 located in the substrate 10 below the fin structure F, and a top surface of the ion doping region 16 is flush with a bottom surface of the fin structure F.
[0053] In some embodiments of the present invention, the concentration of the ion doping region 16 decreases from the center to the outside.
[0054] In some embodiments of the present invention, the concentration of the ion doping region 16 presents a Gaussian distribution.
[0055] In some embodiments of the present invention, a dielectric layer 18 is further included on the substrate 10 , and the dielectric layer 18 defines a recess R2 , and a portion of the fin structure F is located in the recess R2 .
[0056] In some embodiments of the present invention, the bottom electrode layer 20 at least covers a top surface of the dielectric layer 18, a top surface of the substrate 10, a top surface of the fin structure F, and a side wall (see Figure 4 ).
[0057] In some embodiments of the present invention, a spacer 19 is further included, which is located on a side wall of the groove R2 , and the bottom electrode layer 20 covers the spacer 19 .
[0058] In some embodiments of the present invention, from a cross-sectional view, the lower electrode layer 20 , the high dielectric constant layer 22 , and the upper electrode layer 24 have the same cross-sectional profile (all formed along the cross-sectional profile of the fin structure F).
[0059] In some embodiments of the present invention, an upper electrode contact structure MP is further included, which is electrically connected to the upper electrode layer 24 , wherein the lower electrode layer 20 is not located directly under the upper electrode contact structure MP.
[0060] In some embodiments of the present invention, the doping ions in the ion-doped region 16 include phosphorus ions and arsenic ions.
[0061] In some embodiments of the present invention, a lower electrode contact structure MD is further included on the fin structure F, and the lower electrode contact structure MD is electrically connected to the lower electrode layer 20 through the ion doping region 16 .
[0062] The present invention is characterized in that it provides a three-dimensional capacitor structure including a fin-shaped structure, wherein a three-layer structure including a lower electrode layer-dielectric layer-upper electrode layer is directly formed on the fin-shaped structure, thereby making a three-dimensional capacitor structure. In addition, in order to reduce the damage of ions to the fin-shaped structure, the ion doping region is set in the substrate below the fin-shaped structure, and the ion doping concentration in the fin-shaped structure is non-uniformly distributed (the closer to the top, the lower the ion concentration). The lower electrode of the capacitor of the present invention is connected to the lower electrode contact structure through the ion doping region and the epitaxial layer, and the upper electrode contact structure does not overlap with the lower electrode layer in the cross-sectional view, which can reduce the difficulty of the manufacturing process and improve the yield.
[0063] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.
Claims
1. A capacitor structure with a fin structure, comprising: Fin-like structures, located on the substrate; A lower electrode layer, a high dielectric constant layer and an upper electrode layer are sequentially stacked on the fin structure; as well as The ion doping region is located in the substrate below the fin structure, and the top surface of the ion doping region is flush with the bottom surface of the fin structure. 2 . The capacitor structure with a fin structure as claimed in claim 1 , wherein the concentration of the ion doping region decreases from the center to the outside. 3 . The capacitor structure with a fin structure as claimed in claim 1 , wherein the concentration of the ion doping region presents a Gaussian distribution. 4 . The capacitor structure with a fin-shaped structure as claimed in claim 1 , further comprising a dielectric layer located on the substrate, wherein the dielectric layer defines a groove, and a portion of the fin-shaped structure is located in the groove. 5 . The capacitor structure with a fin-shaped structure as claimed in claim 4 , wherein the lower electrode layer at least covers a top surface of the dielectric layer, a top surface of the substrate, and a top surface and sidewalls of the fin-shaped structure. 6 . The capacitor structure with a fin structure as claimed in claim 5 , further comprising a spacer located on a sidewall of the groove, and the lower electrode layer covers the spacer. 7 . The capacitor structure with a fin structure as claimed in claim 1 , wherein from a cross-sectional view, the lower electrode layer, the high dielectric constant layer and the upper electrode layer have the same cross-sectional profile. 8 . The capacitor structure with a fin structure as claimed in claim 1 , further comprising an upper electrode contact structure electrically connected to the upper electrode layer, wherein the lower electrode layer is not located directly below the upper contact structure. 9 . The capacitor structure with a fin structure as claimed in claim 1 , wherein the doping ions in the ion-doped region include phosphorus ions and arsenic ions. 10 . The capacitor structure with a fin structure as claimed in claim 1 , further comprising a lower electrode contact structure located on the fin structure, and the lower electrode contact structure is electrically connected to the lower electrode layer through the ion doping region.
11. A method for forming a capacitor structure including a fin-shaped structure, comprising: forming a fin-like structure located on a substrate; forming a lower electrode layer, a high dielectric constant layer and an upper electrode layer stacked sequentially on the fin structure; and An ion doping region is formed in the substrate below the fin structure, and a top surface of the ion doping region is flush with a bottom surface of the fin structure. 12 . The method for forming a capacitor structure with a fin structure as claimed in claim 11 , wherein the concentration of the ion doping region decreases from the center to the outside. 13 . The method for forming a capacitor structure with a fin structure as claimed in claim 11 , wherein a concentration of the ion doping region presents a Gaussian distribution. 14 . The method for forming a capacitor structure with a fin-shaped structure as claimed in claim 11 , further comprising forming a dielectric layer on the substrate, wherein the dielectric layer defines a groove, and a portion of the fin-shaped structure is located in the groove. 15 . The method for forming a capacitor structure with a fin-shaped structure as claimed in claim 14 , wherein the lower electrode layer at least covers a top surface of the dielectric layer, a top surface of the substrate, and a top surface and sidewalls of the fin-shaped structure. 16 . The method for forming a capacitor structure with a fin structure as claimed in claim 15 , further comprising forming a spacer located on a sidewall of the groove, wherein the lower electrode layer covers the spacer. 17 . The method for forming a capacitor structure with a fin structure as claimed in claim 11 , wherein from a cross-sectional view, the lower electrode layer, the high dielectric constant layer and the upper electrode layer have the same cross-sectional profile. 18 . The method for forming a capacitor structure with a fin structure as claimed in claim 11 , further comprising forming an upper electrode contact structure electrically connected to the upper electrode layer, wherein the lower electrode layer is not located directly below the upper contact structure. 19 . The method for forming a capacitor structure with a fin structure as claimed in claim 11 , wherein the doping ions in the ion doping region include phosphorus ions and arsenic ions. 20 . The method for forming a capacitor structure with a fin-shaped structure as claimed in claim 11 , further comprising forming a lower electrode contact structure on the fin-shaped structure, wherein the lower electrode contact structure is electrically connected to the lower electrode layer through the ion-doped region.