Driver hardware overcurrent protection circuit

Abstract

The embodiment of the invention provides a driver hardware overcurrent protection circuit, which belongs to the technical field of protection circuit design, and comprises an RS trigger circuit realized by a logic chip and a buffer circuit realized by a bus buffer chip U17, when system current Iout is high level and a system is powered on, the RS trigger circuit receives a falling edge pulse signal sent by the single-chip microcomputer and sends the falling edge pulse signal to the CLR, and the single-chip microcomputer sets an LOCK value to be high to enable the system to be normal and pulls down an enable signal PWMEN; when the current of the system is abnormal, the Iout is pulled down to a low level through a diode D49, and the enabling information PWMEN is pulled up at the same time; and the buffer circuit controls the states of a pin 1 and a pin 19 of the chip U17 according to a PWMEN signal generated by the RS trigger circuit. According to the invention, overcurrent protection can be effectively provided for driver hardware.

Description

Technical Field

[0001] The present invention relates to the technical field of protection circuit design, and in particular to a driver hardware overcurrent protection circuit. Background Art

[0002] The overcurrent condition of the driver means that the output current of the driver exceeds the rated range of normal working current during operation. This may be caused by many reasons, such as sudden load change, short circuit or internal fault of the driver.

[0003] When the load driven by the driver (such as a motor) is suddenly subjected to an external force, causing the motor's speed to drop sharply, the motor's back electromotive force will decrease. If this increased current exceeds the normal operating current range of the driver, an overcurrent condition will occur. If the load's power demand exceeds the maximum power that the driver can provide, an overcurrent condition will also occur.

[0004] When the output end of the driver is directly short-circuited due to line damage, connection errors, etc., the resistance is almost zero, and the current far exceeds the normal operating current. This is a typical short-circuit overcurrent. For example, on the circuit board of an electronic device, if the driver output line accidentally contacts the ground line, it will cause an external short-circuit overcurrent.

[0005] Damage to the electronic components inside the driver (such as power transistors, etc.) may also cause internal short circuits. For example, a short circuit between the collector and emitter of a power transistor will change the current path, causing an abnormal increase in current and triggering overcurrent.

[0006] Over time, the components inside the driver (such as capacitors, resistors, semiconductor devices, etc.) may age or become damaged. For example, the capacitance of the capacitor decreases or leakage may affect the voltage regulation function of the driver, which in turn causes the current to be unstable and may exceed the normal range. For another example, the performance of semiconductor devices (such as IGBTs) degrades and their on and off characteristics change, which may cause the current control to fail, thereby causing overcurrent.

[0007] Control circuit failure: The control circuit of the driver is responsible for regulating the output current and voltage. If the control circuit fails, such as control signal errors, feedback loop interruption, etc., it will also cause the output current to be out of control and overcurrent to occur. For example, in a driver using PWM (pulse width modulation) control, if the PWM signal generation circuit fails and produces an abnormal pulse width, the output current may increase abnormally.

[0008] The above problems become technical problems that need to be solved. Summary of the invention

[0009] In view of this, an embodiment of the present invention provides a driver hardware overcurrent protection circuit, which at least partially solves the problems existing in the prior art.

[0010] An embodiment of the present invention provides a driver hardware overcurrent protection circuit, comprising:

[0011] RS trigger circuit implemented by logic chip and buffer circuit implemented by bus buffer chip U17;

[0012] When the system current I_out is at a high level and the system is powered on, the RS trigger circuit receives a falling edge pulse signal from the single-chip microcomputer to CLR, and the single-chip microcomputer sets the LOCK value high to make the system normal and pulls down the enable signal PWM_EN;

[0013] When the system current is abnormal, I_out is pulled down to a low level through diode D49, and the enable information PWM_EN is pulled high at the same time;

[0014] The buffer circuit controls the states of pins 1 and 19 of chip U17 according to the PWM_EN signal generated by the RS trigger circuit. When PWM_EN is at a low level, in the buffer circuit, the output signal UT_PWM is directly connected to the input signal PU+, the output signal UB_PWM is directly connected to the input signal PU-, VT_PWM is directly connected to PV+, VB_PWM is directly connected to PV-, WT_PWM is directly connected to PW+, and WB_PWM is directly connected to PW-. When PWM_EN is at a high level, the drive signals PU+, PU-, PV+, PV-, PW+ and PW- are cut off to protect the subsequent power devices from damage.

[0015] According to a specific implementation of the embodiment of the present invention, the logic chip is a 74HC00 chip, and the specific connection method of 74HC00 is that I_out is connected to the first pin of 74HC00, D49 is connected between I_out and the first pin of 74HC00, the falling edge pulse signal emitted by the single-chip microcomputer is connected to the thirteenth pin of 74HC00, the LOCK signal of the single-chip microcomputer is connected to the tenth pin of 74HC00, and the PWM_EN signal is output from the eighth pin of 74HC00.

[0016] According to a specific implementation of the embodiment of the present invention, when the system current is normal, the 74HC00 keeps the PWM_EN signal at a low level when receiving a falling edge pulse signal from the single-chip microcomputer and the LOCK signal is at a high level.

[0017] According to a specific implementation of the embodiment of the present invention, the bus buffer chip U17 is a 74VHCV244FT chip, and pins 1 and 19 of the 74VHCV244FT receive a PWM_EN signal from 74HC00 to control the output state of the buffer circuit.

[0018] According to a specific implementation of an embodiment of the present invention, the 74VHCV244FT has multiple input and output pins inside. When PWM_EN is at a low level, the corresponding pins UT_PWM, UB_PWM, VT_PWM, VB_PWM, WT_PWM, and WB_PWM are respectively connected to PU+, PU-, PV+, PV-, PW+, and PW- signals.

[0019] According to a specific implementation of the embodiment of the present invention, when PWM_EN is at a high level, the 74VHCV244FT cuts off the driving signal connected to the subsequent power device to prevent the subsequent power device from being damaged.

[0020] According to a specific implementation of the embodiment of the present invention, the circuit further includes a plurality of capacitors and resistors for stabilizing the circuit.

[0021] According to a specific implementation of the embodiment of the present invention, the components in the circuit all operate under a specific voltage supply environment.

[0022] According to a specific implementation of an embodiment of the present invention, the signal transmission line between the RS trigger circuit and the buffer circuit has an anti-interference design to prevent external electromagnetic interference from affecting the normal transmission of the signal.

[0023] According to a specific implementation of the embodiment of the present invention, the driver of the circuit enters a hardware overcurrent protection mode within a preset time after an overcurrent occurs.

[0024] The solution of the present invention has the following beneficial effects:

[0025] 1. Improved security

[0026] During the operation of the driver, once an abnormal overcurrent occurs, the circuit can quickly enter the hardware overcurrent protection mode. By timely cutting off the drive signal or changing the level of the relevant control signal (such as the change of the PWM_EN signal mentioned in the article), it can prevent excessive current from damaging the subsequent power devices, avoid safety hazards such as overheating of power devices and electrical fires caused by circuit short circuits, and effectively ensure the safety of the entire equipment, the surrounding environment and personnel.

[0027] 2. Enhance circuit stability

[0028] Whether it is maintaining the appropriate signal level during normal operation (such as the PWM_EN signal is at a low level under normal logic to ensure normal operation of the system), or making accurate responses during abnormal overcurrent, it helps to maintain the stable operation of the entire driver circuit system. It avoids the adverse effects of system disorder caused by overcurrent and voltage and current fluctuations on other related circuit modules, allowing the entire system to work continuously and reliably.

[0029] 3. Protect key components

[0030] For the power devices of the subsequent stage, overcurrent is one of the main factors causing their damage. The overcurrent protection circuit of the present invention acts quickly after detecting the overcurrent anomaly, cuts off the driving signal, prevents the power devices from being subjected to excessive current for a long time, reduces the thermal stress, electrical stress and other damages caused by overcurrent to the power devices, thereby effectively extending the service life of these key power devices and reducing the maintenance and replacement costs of the equipment.

[0031] 4. Improve equipment reliability

[0032] Due to its fast and effective overcurrent protection mechanism, the driver can promptly protect itself and maintain the relative integrity of the overall function when faced with various situations that may cause overcurrent (such as load mutation, short circuit, internal component failure, etc.), reducing the probability of equipment failure and shutdown due to overcurrent, and improving the reliability of the equipment in actual application scenarios, so that it can better meet the requirements of industrial production, automation control and other fields for long-term stable operation of equipment.

[0033] 5. Optimize system response speed

[0034] By designing reasonable RS trigger circuits and buffer circuits, the circuit can quickly detect and respond to overcurrent conditions as soon as they occur. Compared with some traditional overcurrent protection methods, it can enter the protection mode more quickly and minimize the damage caused by overcurrent to the system. This fast response feature helps to improve the performance of the entire drive system. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0036] Figure 1 A schematic diagram of an RS trigger circuit provided by an embodiment of the present invention;

[0037] Figure 2 A schematic diagram of a buffer circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0038] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0039] The following describes the embodiments of the present disclosure through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0040] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein may be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present disclosure, it should be understood by those skilled in the art that an aspect described herein may be implemented independently of any other aspect, and two or more of these aspects may be combined in various ways. For example, any number of aspects described herein may be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein may be used to implement this device and / or practice this method.

[0041] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present disclosure. The drawings only show components related to the present disclosure rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0042] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects described may be practiced without these specific details.

[0043] See also Figure 1 and Figure 2 , the embodiment of the present disclosure provides a driver hardware overcurrent protection circuit, comprising:

[0044] RS trigger circuit implemented by logic chip and buffer circuit implemented by bus buffer chip U17;

[0045] When the system current I_out is at a high level and the system is powered on, the RS trigger circuit receives a falling edge pulse signal from the single-chip microcomputer to CLR, and the single-chip microcomputer sets the LOCK value high to make the system normal and pulls down the enable signal PWM_EN;

[0046] When the system current is abnormal, I_out is pulled down to a low level through diode D49, and the enable information PWM_EN is pulled high at the same time;

[0047] The buffer circuit controls the states of pins 1 and 19 of chip U17 according to the PWM_EN signal generated by the RS trigger circuit. When PWM_EN is at a low level, in the buffer circuit, the output signal UT_PWM is directly connected to the input signal PU+, the output signal UB_PWM is directly connected to the input signal PU-, VT_PWM is directly connected to PV+, VB_PWM is directly connected to PV-, WT_PWM is directly connected to PW+, and WB_PWM is directly connected to PW-. When PWM_EN is at a high level, the drive signals PU+, PU-, PV+, PV-, PW+ and PW- are cut off to protect the subsequent power devices from damage.

[0048] The RS trigger circuit is implemented by 74HC00, as follows:

[0049] Normal logic:

[0050] The system current I_out is at a high level;

[0051] When the system is powered on, the microcontroller sends (falling edge pulse signal) to CLR (pin 13 of U34, i.e. It is a falling edge pulse signal;

[0052] The microcontroller sets the LOCK (pin 10 of U34) value to high → the system is normal;

[0053] Then PWM_EN (pin 8 of U34) is pulled low;

[0054] Abnormal situation:

[0055] 1. When the system current is abnormal, that is, I_out is at a low level,

[0056] The buffer circuit is implemented by 74VHCV244FT. The PWM_EN signal generated by the RS trigger circuit is used to control the state of the low 1 pin and 19 pin of U17. The input of 74VHCV244FT When it is low level, Input An=Output Yn, When it is high level, the Input An signal is cut off.

[0057] When PWM_EN is at a low level, UT_PWM=PU+, UB_PWM=PU-, VT_PWM=PV+, VB_PWM=PV-, WT_PWM=PW+, WB_PWM=PW-; when PWM_EN is at a high level, the drive signal is cut off to protect the subsequent power devices from damage.

[0058] See also Figure 1 , Figure 1 The chip includes multiple chips, such as U34 and U17. U34 is a 74HC00 chip, which is a CMOS logic chip with four 2-input NAND gates. U17 is a 74VHCV244FT chip, which is a high-speed CMOS octal bus buffer used to enhance the driving capability of the signal.

[0059] Figure 1 There is a diode D49, which plays a rectifying or protective role in the circuit, and a transistor (such as Q1), which is used for amplification or switching in the circuit.

[0060] Figure 1 There are multiple resistors (such as R206) and capacitors (such as C164) in the circuit, which are used for voltage division, current limiting, filtering and other functions. For example, resistor R206 is used to limit current, and capacitor C164 is used for filtering.

[0061] There are multiple input and output ports in the diagram, labeled with signals such as "PMW_EN" and "LOCK". These signals are used to control different functions of the circuit. For example, the "PMW_EN" signal is used to control the pulse width modulation (PWM), and the "LOCK" signal is used to lock the circuit state.

[0062] This circuit is used for hardware overcurrent protection of the driver. When the system current is abnormal, through the coordinated work of the logic chip and related components, it can quickly enter the hardware overcurrent protection mode to avoid safety accidents.

[0063] For example, when the current is abnormal, the "PMW_EN" signal may be pulled high through the combination of diode D49 and logic chip U34, and then the driving signal may be cut off through buffer U17 to protect the subsequent power devices.

[0064] According to a specific implementation of the embodiment of the present invention, the logic chip is a 74HC00 chip, and the specific connection method of 74HC00 is that I_out is connected to the first pin of 74HC00, D49 is connected between I_out and the first pin of 74HC00, the falling edge pulse signal emitted by the single-chip microcomputer is connected to the thirteenth pin of 74HC00, the LOCK signal of the single-chip microcomputer is connected to the tenth pin of 74HC00, and the PWM_EN signal is output from the eighth pin of 74HC00.

[0065] According to a specific implementation of the embodiment of the present invention, when the system current is normal, the 74HC00 keeps the PWM_EN signal at a low level when receiving a falling edge pulse signal from the single-chip microcomputer and the LOCK signal is at a high level.

[0066] According to a specific implementation of the embodiment of the present invention, the bus buffer chip U17 is a 74VHCV244FT chip, and pins 1 and 19 of the 74VHCV244FT receive a PWM_EN signal from 74HC00 to control the output state of the buffer circuit.

[0067] According to a specific implementation of an embodiment of the present invention, the 74VHCV244FT has multiple input and output pins inside. When PWM_EN is at a low level, the corresponding pins UT_PWM, UB_PWM, VT_PWM, VB_PWM, WT_PWM, and WB_PWM are respectively connected to PU+, PU-, PV+, PV-, PW+, and PW- signals.

[0068] According to a specific implementation of the embodiment of the present invention, when PWM_EN is at a high level, the 74VHCV244FT cuts off the driving signal connected to the subsequent power device to prevent the subsequent power device from being damaged.

[0069] According to a specific implementation of the embodiment of the present invention, the circuit further includes a plurality of capacitors and resistors for stabilizing the circuit.

[0070] According to a specific implementation of the embodiment of the present invention, the components in the circuit all operate under a specific voltage supply environment.

[0071] According to a specific implementation of an embodiment of the present invention, the signal transmission line between the RS trigger circuit and the buffer circuit has an anti-interference design to prevent external electromagnetic interference from affecting the normal transmission of the signal.

[0072] According to a specific implementation of the embodiment of the present invention, the driver of the circuit enters a hardware overcurrent protection mode within a preset time after an overcurrent occurs.

[0073] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A driver hardware overcurrent protection circuit, characterized in that: include: RS trigger circuit implemented by logic chip and buffer circuit implemented by bus buffer chip U17; When the system current I_out is at a high level and the system is powered on, the RS trigger circuit receives a falling edge pulse signal from the single-chip microcomputer to CLR, and the single-chip microcomputer sets the LOCK value high to make the system normal and pulls down the enable signal PWM_EN; When the system current is abnormal, I_out is pulled down to a low level through diode D49, and the enable information PWM_EN is pulled high at the same time; The buffer circuit controls the states of pins 1 and 19 of chip U17 according to the PWM_EN signal generated by the RS trigger circuit. When PWM_EN is at a low level, in the buffer circuit, the output signal UT_PWM is directly connected to the input signal PU+, the output signal UB_PWM is directly connected to the input signal PU-, VT_PWM is directly connected to PV+, VB_PWM is directly connected to PV-, WT_PWM is directly connected to PW+, and WB_PWM is directly connected to PW-. When PWM_EN is at a high level, the drive signals PU+, PU-, PV+, PV-, PW+ and PW- are cut off to protect the subsequent power devices from damage.

2. The driver hardware overcurrent protection circuit according to claim 1, characterized in that: The logic chip is a 74HC00 chip. The specific connection method of 74HC00 is that I_out is connected to the first pin of 74HC00, D49 is connected between I_out and the first pin of 74HC00, the falling edge pulse signal emitted by the microcontroller is connected to the thirteenth pin of 74HC00, the LOCK signal of the microcontroller is connected to the tenth pin of 74HC00, and the PWM_EN signal is output from the eighth pin of 74HC00.

3. The driver hardware overcurrent protection circuit according to claim 2, characterized in that: When the system current is normal, the 74HC00 keeps the PWM_EN signal at a low level when receiving a falling edge pulse signal from the single-chip microcomputer and the LOCK signal is at a high level.

4. The driver hardware overcurrent protection circuit according to claim 3, characterized in that: The bus buffer chip U17 is a 74VHCV244FT chip, and pins 1 and 19 of the 74VHCV244FT receive the PWM_EN signal from 74HC00 to control the output state of the buffer circuit.

5. The driver hardware overcurrent protection circuit according to claim 4, characterized in that: The 74VHCV244FT has multiple input and output pins inside. When PWM_EN is at a low level, the corresponding pins UT_PWM, UB_PWM, VT_PWM, VB_PWM, WT_PWM, and WB_PWM are connected to PU+, PU-, PV+, PV-, PW+, and PW- signals respectively.

6. The driver hardware overcurrent protection circuit according to claim 5, characterized in that: When PWM_EN is at a high level, the 74VHCV244FT cuts off the driving signal connected to the subsequent power device to prevent the subsequent power device from being damaged.

7. The driver hardware overcurrent protection circuit according to claim 6, characterized in that: The circuit also includes multiple capacitors and resistors for circuit stability.

8. The driver hardware overcurrent protection circuit according to claim 7, characterized in that: The components in the circuit all work under a specific voltage supply environment.

9. The driver hardware overcurrent protection circuit according to claim 8, characterized in that: The signal transmission line between the RS trigger circuit and the buffer circuit has an anti-interference design to prevent external electromagnetic interference from affecting the normal transmission of the signal.

10. The driver hardware overcurrent protection circuit according to claim 9, characterized in that: The driver of the circuit enters a hardware overcurrent protection mode within a preset time after an overcurrent occurs.

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