Current source type converter and equivalent application condition test circuit

Abstract

The present disclosure relates to a current source type converter and an equivalent application condition test circuit. The current source type converter includes: a multilevel conversion unit, a total AC port, and a total DC port. The multilevel conversion unit includes a multilevel converter and a main converter, both of which have a first port, a second port, and a third port. The total DC port has a first end and a second end. Among them, the first port of the multilevel converter is connected to the first port of the main converter; the second port of the multilevel converter is connected to the first end of the total DC port; the third port of the multilevel converter is connected to the second end of the total DC port; the second port of the main converter is connected to the second port of the multilevel converter and the first end of the total DC port; the third port of the main converter is connected to the total AC port. The present disclosure can simultaneously improve the programmable performance of the current source and its arm level efficiency, and reduce the implementation difficulty.

Description

Technical Field

[0001] The present disclosure relates to the field of power electronics technology, and particularly to a current source type converter and an equivalent application condition test circuit. Background Art

[0002] Equivalent application condition test is to use a dedicated test circuit to reproduce the characteristic stresses of a device under test or a core device in the device under test in the application condition. Currently, the commonly used test circuit can be composed of a voltage source with high voltage and small current, a current source with low voltage and large current, and the device under test connected in parallel, where the device under test is, for example, a power semiconductor device or a converter valve assembly.

[0003] During the equivalent application condition test, in coordination with the control timing of each component, the voltage source can generate characteristic voltage stress when the device under test is blocked, and the current source can generate characteristic current stress when the device under test is conducting. However, there are significant differences between the characteristic stress waveforms of different application conditions. In order to improve the versatility of the test circuit and the accuracy of the equivalent application condition test results, how to effectively improve the programmable performance of the voltage source and the current source to generate characteristic stresses close to the target application condition remains to be further optimized. Summary of the Invention

[0004] Based on this, embodiments of the present disclosure provide a current source type converter and an equivalent application condition test circuit, which can effectively improve the bridge arm level efficiency of the current source type converter while improving the programmable performance of the current source, and reduce the implementation difficulty of a multi-level current source type converter.

[0005] To achieve the above object, in a first aspect, some embodiments of the present disclosure provide a current source type converter. The current source type converter includes: a multi-level conversion unit, a total AC port, and a total DC port. The multi-level conversion unit includes a multi-level converter and a main converter, and both the multi-level converter and the main converter have a first port, a second port, and a third port; the total DC port has a first end and a second end. Among them, the first port of the multi-level converter is connected to the first port of the main converter; the second port of the multi-level converter is connected to the first end of the total DC port; the third port of the multi-level converter is connected to the second end of the total DC port; the second port of the main converter is connected to the second port of the multi-level converter and the first end of the total DC port; the third port of the main converter is connected to the total AC port.

[0006] In some embodiments of the present disclosure, the multilevel converter includes: n sets of two-level converters and a first smoothing reactor. The n sets of two-level converters are connected in parallel between the first port and the second port of the multilevel converter, where n is a positive integer greater than or equal to 1. The first smoothing reactor is connected in series between the third port of the multilevel converter and the n sets of two-level converters. Among them, the two-level converter includes: a first arm and a second arm connected in series with a common cathode, and a second smoothing reactor connected in parallel at both ends of the second arm.

[0007] Optionally, the main converter includes: a three-phase converter formed by connecting six sets of third arms; among them, every two sets of third arms are connected in series to form a set of half-bridges, and three sets of half-bridges are connected in parallel.

[0008] In some embodiments of the present disclosure, the first arm, the second arm, and the third arm are all composed of reverse-blocking fully controlled power semiconductor devices connected in series. Or, in some other embodiments of the present disclosure, the first arm and the second arm are both composed of reverse-blocking fully controlled power semiconductor devices connected in series; the third arm is composed of reverse-blocking semi-controlled power semiconductor devices connected in series.

[0009] Optionally, the main converter includes: a single-phase converter formed by connecting four sets of fourth arms.

[0010] In some embodiments of the present disclosure, the inductance values of the second smoothing reactors in each two-level converter are the same. Or, in some other embodiments of the present disclosure, the inductance values of the second smoothing reactors in each two-level converter are arranged in a geometric progression of 1: 2: … : 2(n - 1). Or, in some other embodiments of the present disclosure, the inductance values of the second smoothing reactors in each two-level converter are arranged in a geometric progression of 1: 2: … : 2(n - 1), and the sum of the inductance values of the second smoothing reactors in each two-level converter is the same as the inductance value of the first smoothing reactor.

[0011] Optionally, the number of multilevel conversion units is m sets, where m is a positive integer greater than or equal to 2.

[0012] Correspondingly, in some embodiments of the present disclosure, the third ports of the main converters in each multilevel conversion unit are connected in parallel to the total AC port; the second ports of the multilevel converters in each multilevel conversion unit are connected in parallel to the first end of the total DC port; the third ports of the multilevel converters in each multilevel conversion unit are connected in parallel to the second end of the total DC port. Or, in some other embodiments of the present disclosure, the third ports of the main converters in each multilevel conversion unit are connected in parallel to the total AC port; the multilevel converters in each multilevel conversion unit are connected in series between the first end and the second end of the total DC port in sequence.

[0013] Optionally, the multilevel converter includes n groups of two-level converters connected in parallel between the first port, the second port, and the third port of the multilevel converter, where n is a positive integer greater than or equal to 1. Among them, the two-level converter includes: a first arm and a second arm connected in series with a common anode and a second smoothing reactor; the cathode of the first arm is connected to the first port of the multilevel converter, and the cathode of the second arm is connected to the second port of the multilevel converter; one end of the second smoothing reactor is connected between the first arm and the second arm, and the other end is connected to the third port of the multilevel converter.

[0014] Optionally, the multilevel converter includes: n groups of two-level converters connected in parallel between the first port, the second port, and the third port of the multilevel converter, where n is a positive integer greater than or equal to 1. Among them, the two-level converter includes: a first arm, a second arm, a coupling inductor, a buffer capacitor, and a fifth arm; one end of the first arm and one end of the second arm are connected and connected to the third port of the multilevel converter; the other end of the first arm is connected to one end of the first winding of the coupling inductor and the first electrode plate of the buffer capacitor; the other end of the second arm is connected to one end of the second winding of the coupling inductor and the second electrode plate of the buffer capacitor; the other ends of the first winding and the second winding are connected and connected to the first port of the multilevel converter and the anodic end of the fifth arm; the cathodic end of the fifth arm is connected to the second port of the multilevel converter.

[0015] In a second aspect, some embodiments of the present disclosure further provide an equivalent application condition test circuit, including a current source; the current source includes a current source type converter as described in any of the above embodiments.

[0016] The embodiments of the present disclosure may / at least have the following advantages:

[0017] In the embodiments of the present disclosure, the multilevel conversion unit of the current source type converter is provided with a multilevel converter and a main converter, and both the multilevel converter and the main converter have a first port, a second port, and a third port. At the same time, the first port of the multilevel converter is connected to the first port of the main converter, the second port of the multilevel converter is connected to the first end of the total DC port, the third port of the multilevel converter is connected to the second end of the total DC port, the second port of the main converter is connected to the second port of the multilevel converter and the first end of the total DC port, and the third port of the main converter is connected to the total AC port. Therefore, by designing the number of arms and the corresponding connection relationships in the multilevel converter and the main converter, the programmable performance of the current source can be effectively improved, the arm level efficiency of the current source type converter can be effectively improved, and the implementation difficulty of the multilevel current source type converter can be reduced.

[0018] Details of one or more embodiments of the present disclosure are set forth in the following drawings and description. Other features, objects, and advantages of the present disclosure will become apparent from the specification, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] To more clearly illustrate the technical solutions in the embodiments of the present disclosure or in the prior art, the following briefly introduces the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0020] Figure 1 Structural schematic diagram of a current source type converter provided in some embodiments;

[0021] Figure 2 Structural schematic diagram of a multilevel converter provided in some embodiments;

[0022] Figure 3 Structural schematic diagram of a two-level converter provided in some embodiments;

[0023] Figure 4 Structural schematic diagram of a main converter provided in some embodiments;

[0024] Figure 5 Structural schematic diagram of another main converter provided in some embodiments;

[0025] Figure 6 Structural schematic diagram of yet another main converter provided in some embodiments;

[0026] Figure 7 Structural schematic diagram of another current source type converter provided in some embodiments;

[0027] Figure 8 Structural schematic diagram of yet another current source type converter provided in some embodiments;

[0028] Figure 9 Structural schematic diagram of another multilevel converter provided in some embodiments;

[0029] Figure 10 Structural schematic diagram of another two-level converter provided in some embodiments;

[0030] Figure 11 Structural schematic diagram of yet another two-level converter provided in some embodiments;

[0031] Figure 12A comparison diagram of the arm - level efficiency between a multi - inductor multi - level current - source converter provided in some embodiments and a current - source converter in related technologies;

[0032] Figure 13 A comparison diagram of the arm - level efficiency between a multi - inductor - different - value multi - level current - source converter provided in some embodiments and a current - source converter in related technologies;

[0033] Figure 14 A comparison diagram of the arm - level efficiency between a magnetically - integrated multi - level current - source converter provided in some embodiments and a current - source converter in related technologies.

[0034] Explanation of reference numerals:

[0035] 1 - multi - level converter, 1’ - the m - th group of multi - level converters, 11 - the first port of the multi - level converter, 12 - the second port of the multi - level converter, 13 - the third port of the multi - level converter, 14 - two - level converter, 141 - the first arm, 142 - the second arm, 143 - the second smoothing reactor, 144 - the first port of the two - level converter, 145 - the second port of the two - level converter, 146 - the third port of the two - level converter, 147 - coupled inductor, 148 - buffer capacitor, 149 - the fifth arm, 15 - the first smoothing reactor, 2 - main converter, 2’ - the m - th group of main converters, 21 - the third arm, 22 - the fourth arm, 3 - total AC port, 4 - total DC port. Detailed implementation manners

[0036] To facilitate the understanding of the present disclosure, the present disclosure will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present disclosure is more thorough and comprehensive.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this disclosure belongs. The terms used in the specification of this disclosure herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0038] It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part.

[0039] It should be understood that when an element is considered to be "connected" to another element, it can be directly connected to the other element or connected to the other element through an intermediate element. In addition, in the following embodiments, "connection", if there is transmission of electrical signals or data between the connected objects, should be understood as "electrical connection", "communication connection", etc.

[0040] It should be understood that the singular forms of "a", "an" and "the" may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that terms such as "comprising" or "having" etc. specify the presence of the stated features, wholes, steps, operations, components, parts or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof. At the same time, when used herein, the term "and / or" includes any and all combinations of the related listed items.

[0041] For equivalent application condition tests, there are significant differences between the characteristic stress waveforms of different application conditions. In order to improve the versatility of the test circuit and the accuracy of the equivalent application condition test results, how to effectively improve the programmable performance of the voltage source and the current source to generate characteristic stresses close to the target application conditions remains to be further optimized.

[0042] In the related art, the voltage source has developed the function of programmable generation of arbitrary waveforms based on a modular multilevel converter. The principle is to quickly change the output discrete voltage levels of each module and superimpose them in series, so that the programmable performance of the voltage source can be improved by increasing the number of levels, and it can be ensured that the stress waveform generated by the voltage source is closer to the characteristic stress of the device under test in the application condition, thereby improving the versatility of the test circuit and the accuracy of the equivalent application condition test results.

[0043] However, the current source is limited by the topology structure of the existing current source type converter, with low modularity and difficulty in increasing the number of levels. At present, it does not have the function of programmable generation of arbitrary waveforms. However, due to the high unit floor area capacity of the current source type converter and its ability to effectively handle DC short-circuit faults without shutting down, it can have significant technical advantages in applications such as wind power transmission and offshore wind power networking. Therefore, how to optimize the programmable performance of the current source has become the current technical focus.

[0044] In the related art, the common topology unit of the current source type converter is the device series structure. For example, the bridge arm is directly composed of reverse-blocking fully controlled power semiconductor devices in series. Two bridge arms are connected in series to form a half-bridge, and three half-bridges are connected in parallel to form the power electronics part of the current source type converter. The two ends of each half-bridge are connected to the DC port through a smoothing reactor, and the midpoint of each half-bridge is connected to the AC port through an LC filter.

[0045] Accordingly, when the current source type converter operates in a steady state, the current amplitude of the smoothing reactor is approximately constant. Moreover, when the upper arm of the half-bridge conducts and the lower arm blocks, a positive current is injected into the corresponding phase AC port, and the current amplitude is the same as that of the smoothing reactor. When the lower arm of the half-bridge conducts and the upper arm blocks, a negative current is injected into the corresponding phase AC port, and the current amplitude is the same as that of the smoothing reactor. When both the upper and lower arms of the half-bridge conduct simultaneously, the smoothing reactor conducts current through the short-circuited half-bridge, and the current amplitude injected into the corresponding phase AC port is zero. Therefore, the current source type converter adopting the device series structure can only generate three levels at the AC port, with a small number of levels, low programmable performance, and high harmonic content in the output waveform. It is not suitable as the current source of the test circuit and is likely to affect or even harm the power quality of the load connected to the AC port.

[0046] It can be understood that in the related art, by connecting multiple groups of the aforementioned topology units in parallel or in series to form a current source type converter, the number of levels at the AC port of the current source type converter can be increased, thereby improving the programmable performance of the current source type converter.

[0047] Exemplarily, in the current source type converter with multiple groups of topology units connected in parallel, the bridge arm first forms a topology unit with a series-connected device and a smoothing reactor. The DC ports and AC ports of multiple groups of topology units are respectively connected in parallel to form a total DC current port and a total AC port. Accordingly, when the current source type converter with multiple groups of topology units connected in parallel operates in a steady state, the current amplitudes of the smoothing reactors of each group of topology units are approximately equal. When the upper arms of each group of topology units conduct, a positive current is injected into the corresponding phase AC port, and the current amplitude is, for example, nI dc , where n is the number of groups of topology units, and I dc is the current amplitude of the smoothing reactor of each group. When the lower arms of each group of topology units conduct, a negative current is injected into the corresponding phase AC port, and the current amplitude is, for example, nI dc . Therefore, by coordinating the switching states of each bridge arm, (2n + 1) levels can be generated at the corresponding phase AC port. Since each group of topology units has 6 bridge arms, the total number of bridge arms in the current source type converter is 6n, and the level efficiency of each bridge arm is (2n + 1) / 6n.

[0048] Exemplarily, in a current source type converter with multiple groups of topology units connected in series, the bridge arms first form topology units with devices connected in series directly. The DC ports of each group of topology units are connected in series with a smoothing reactor to form a total DC port, and the AC ports of each group of topology units are coupled and paralleled through a transformer to form a total AC port. Correspondingly, when the current source type converter with multiple groups of topology units connected in series operates in a steady state, the current amplitude of the smoothing reactor is approximately constant. And, similar to the current source type converter with multiple groups of topology units connected in parallel, when the upper bridge arms of each group of topology units are conducting, a positive current is injected into the corresponding phase AC port, and the current amplitude is, for example, nI dc , where n is the number of groups of topology units, and I dc is the current amplitude of the smoothing reactor for each group. When the lower bridge arms of each group of topology units are conducting, a negative current is injected into the corresponding phase AC port, and the current amplitude is, for example, nI dc . Therefore, by coordinating the switching states of each bridge arm, (2n + 1) levels can be generated on the AC port of the corresponding phase. Since each group of topology units has 6 bridge arms, the total number of bridge arms in the current source type converter is 6n, and the level efficiency of each bridge arm is (2n + 1) / 6n.

[0049] In summary, the bridge arm level efficiency of the current source type converter is the same whether multiple groups of topology units are connected in parallel or in series, both being (2n + 1) / 6n; that is, for every 2 increase in the number of levels at the AC port, the number of bridge arms increases by 6. It can be seen that the bridge arm level efficiency of the above current source type converter is relatively low. If the same number of levels needs to be generated, more bridge arms and switching devices are required, which will easily increase the implementation cost, control difficulty, and operating loss of the multilevel current source type converter significantly, reducing the technical advantages of the multilevel current source type converter and thus hindering its application in the test circuit and power processing for equivalent application condition tests.

[0050] Based on this, some embodiments of the present disclosure provide a current source type converter and an equivalent application condition test circuit, which can effectively improve the bridge arm level efficiency of the current source type converter while enhancing the current source programmable performance, and reduce the implementation difficulty of the multilevel current source type converter.

[0051] Please refer to Figure 1, the current source type converter provided by the embodiments of the present disclosure includes: a multilevel conversion unit, a total AC port 3, and a total DC port 4. Among them, the multilevel conversion unit includes a multilevel converter 1 and a main converter 2, and both the multilevel converter 1 and the main converter 2 have a first port, a second port, and a third port; the total DC port 4 has a first end and a second end. The first port of the multilevel converter 1 is connected to the first port of the main converter 2; the second port of the multilevel converter 1 is connected to the first end of the total DC port 4; the third port of the multilevel converter 1 is connected to the second end of the total DC port 4; the second port of the main converter 2 is connected to the second port of the multilevel converter 1 and the first end of the total DC port 4; the third port of the main converter 2 is connected to the total AC port 3.

[0052] It can be understood that the first port and the second port of the above-mentioned main converter 2 are its DC ports, and the multilevel converter 1 is connected in parallel to the DC ports of the main converter 2. The embodiments of the present disclosure can effectively improve the programmable performance of the current source by designing the number of bridge arms and the corresponding connection relationships in the multilevel converter 1 and the main converter 2, while effectively improving the bridge arm level efficiency of the current source type converter and reducing the implementation difficulty of the multilevel current source type converter.

[0053] In some embodiments, please refer to Figure 2 , the multilevel converter 1 includes: n groups of two-level converters 14 and a first smoothing reactor 15. The n groups of two-level converters 14 are connected in parallel between the first port 11 and the second port 12 of the multilevel converter 1, and n is a positive integer greater than or equal to 1. The first smoothing reactor 15 is connected in series between the third port 13 of the multilevel converter 1 and the n groups of two-level converters 14.

[0054] Exemplarily, please refer to Figure 3 , the two-level converter 14 includes: a first bridge arm 141 and a second bridge arm 142 connected in series with a common cathode, and a second smoothing reactor 143 connected in parallel at both ends of the second bridge arm 142.

[0055] Optionally, please refer to Figure 4 , the main converter 2 includes: a three-phase converter formed by connecting six groups of third bridge arms 21; among them, every two groups of third bridge arms 21 are connected in series to form a group of half bridges, and three groups of half bridges are connected in parallel. The three-phase converter adopts a device series structure.

[0056] It is worth mentioning that in some embodiments of the present disclosure, the above-mentioned first bridge arm 141, second bridge arm 142, and third bridge arm 21 are all composed of reverse-blocking fully controlled power semiconductor devices connected in series, and the number of series stages is greater than or equal to 1.

[0057] Optionally, the reverse-blocking fully-controlled power semiconductor device includes, but is not limited to, being composed of a reverse-blocking integrated gate-commutated thyristor (IGCT for short), a reverse-blocking insulated gate bipolar transistor (IGBT for short), and a reverse-conducting or asymmetric power semiconductor device in series with a diode.

[0058] Optionally, the inductance values of the second smoothing reactors 143 in each two-level converter 14 are the same.

[0059] Thus, when the current-source converter provided in this embodiment operates in a steady state, the current amplitudes of the first smoothing reactor 15 and the second smoothing reactor 143 are approximately constant. When the inductance values of the second smoothing reactors 143 of each two-level converter 14 are the same, the current amplitude of the first smoothing reactor 15 will be n times that of the second smoothing reactor 143.

[0060] In the above two-level converter 14, when the second arm 142 is blocked and the first arm 141 is conducting, a negative current with an amplitude of I dc is injected into the first port 11 of the multi-level converter 1, and the amplitude I dc is the current amplitude of the second smoothing reactor 143. When the second arm 142 is conducting, the second smoothing reactor 143 conducts current through the second arm 142, and the port current of the two-level converter 14 is zero.

[0061] In the above main converter 2, the current at the DC port of the main converter 2 is the current obtained by subtracting the port currents of all the two-level converters 14 from the current of the first smoothing reactor 15. Since n groups of two-level converters 14 can combine to produce (n + 1) current levels, the number of current levels at the DC port of this main converter 2 is (n + 1). Moreover, in a half-bridge of one phase of the main converter 2, when the first arm 141 is conducting, a positive current level is injected into the corresponding phase's AC port, and the possible number of levels is the same as the number of current levels at the DC port, which is (n + 1); when the second arm 142 is conducting, a negative current level is injected into the corresponding phase's AC port, and the possible number of levels is also (n + 1). Since the zero levels of the positive and negative current levels overlap, the total number of current levels at the total AC port 3 is (2n + 1). Thus, the current-source converter in this embodiment adopts a same-inductance reduction architecture. After calculation, the total number of bridge arms of the current-source converter in this embodiment is (2n + 6), and the bridge-arm level efficiency can be obtained as (2n + 1) / (2n + 6).

[0062] In some other embodiments of the present disclosure, the current source type converter may adopt a common inductance reduction type architecture and is used in cooperation with the main converter 2 composed of semi-controlled devices. For example, in the multilevel converter 1, the first arm 141 and the second arm 142 of the two-level converter 14 are both composed of reverse-blocking fully-controlled power semiconductor devices connected in series, and the number of series stages is greater than or equal to 1; while the third arm 21 in the main converter 2 is composed of reverse-blocking semi-controlled power semiconductor devices connected in series, and the number of series stages is greater than or equal to 1, as shown in, for example Figure 5 shown in

[0063] Optionally, the reverse-blocking semi-controlled power semiconductor device includes, but is not limited to, a thyristor.

[0064] As described above, when the current source type converter provided in this embodiment is in steady-state operation, the current amplitudes of the first smoothing reactor 15 and the second smoothing reactor 143 are approximately constant. When the inductance values of the second smoothing reactors 143 of each two-level converter 14 are the same, the current amplitude of the first smoothing reactor 15 will be n times that of the second smoothing reactor 143.

[0065] In the above two-level converter 14, when the second arm 142 is blocked and the first arm 141 is conducting, a negative current with an amplitude of I dc is injected into the first port 11 of the multilevel converter 1, and the amplitude I dc is the current amplitude of the second smoothing reactor 143. When the second arm 142 is conducting, the second smoothing reactor 143 conducts current through the second arm 142, and the port current of the two-level converter 14 is zero.

[0066] In the above-mentioned main converter 2, the current at the DC port of the main converter 2 is the current of the first smoothing reactor 15 minus the port currents of all the two-level converters 14. Since n groups of two-level converters 14 can combine to produce (n + 1) current levels, the number of current levels at the DC port of this main converter 2 is (n + 1). Moreover, in a half-bridge of one phase of the main converter 2, when the first bridge arm 141 is conducting, a positive current level is injected into the AC port of the corresponding phase, and the possible number of levels is the same as the number of current levels at the DC port, which is (n + 1); when the second bridge arm 142 is conducting, a negative current level is injected into the AC port of the corresponding phase, and the possible number of levels is also (n + 1). Since the zero levels of the positive and negative current levels overlap, the total number of current levels at the total AC port 3 is (2n + 1). It should be added that in the embodiments of the present disclosure, the main converter 2 uses semi-controlled power semiconductor devices to form the bridge arm. This bridge arm cannot be actively turned off, but can be passively turned off by reducing the current level at the DC port to zero. Thus, through calculation, the total number of bridge arms of the current source type converter in this embodiment is (2n + 6), and the bridge arm level efficiency can be obtained as (2n + 1) / (2n + 6), that is, the same as the bridge arm level efficiency in the previous embodiment. However, in this embodiment, the manufacturing cost and operating loss can be significantly reduced by using semi-controlled power semiconductor devices.

[0067] In some other embodiments of the present disclosure, please refer to Figure 6 , the main converter 2 includes: a single-phase converter formed by connecting four groups of fourth bridge arms 22. Thus, when the main converter 2 in this embodiment is working, it can make the opposite bridge arms conduct simultaneously or make the upper and lower bridge arms conduct simultaneously to be applicable to the application scenario of single-phase output. The total number of levels and the level efficiency that can be output in this embodiment are the same as those in the above-mentioned embodiment.

[0068] It is worth mentioning that in some embodiments of the present disclosure, the current source type converter can be formed by overall parallel connection or overall series-parallel connection of m groups of multilevel conversion units, where m is a positive integer greater than or equal to 2.

[0069] Optionally, the m groups of multilevel conversion units are overall parallel-connected. Please refer to Figure 7, the third ports of the main converters 2 (such as from the first group of main converters 2 to the mth group of main converters 2') in each multi-level conversion unit are connected in parallel to the total AC port 3; the second ports of the multi-level converters 1 (such as from the first group of multi-level converters 1 to the mth group of multi-level converters 1') in each multi-level conversion unit are connected in parallel to the first end of the total DC port 4; the third ports of the multi-level converters 1 (such as from the first group of multi-level converters 1 to the mth group of multi-level converters 1') in each multi-level conversion unit are connected in parallel to the second end of the total DC port 4. In this way, this embodiment can effectively increase the current output capacity, and its maximum output current can be increased to m times, and the corresponding number of current levels can be increased to m(2n + 1). In this way, through calculation, the total number of bridge arms of the current source type converter in this embodiment is m(2n + 6), and the bridge arm level efficiency can be obtained as (2n + 1) / (2n + 6), that is, the same as the bridge arm level efficiency in some of the foregoing embodiments.

[0070] Optionally, the m groups of multi-level conversion units are connected in series and parallel as a whole. Please refer to Figure 8 , the third ports of the main converters 2 (such as from the first group of main converters 2 to the mth group of main converters 2') in each multi-level conversion unit are connected in parallel to the total AC port 3; the multi-level converters 1 (such as from the first group of multi-level converters 1 to the mth group of multi-level converters 1') in each multi-level conversion unit are sequentially connected in series between the first end and the second end of the total DC port 4. In this way, this embodiment can effectively increase the DC voltage withstand capacity and the AC current output capacity. The maximum DC voltage of the current source type converter in this embodiment can be increased to m times, and the maximum AC output current of the current source type converter in this embodiment can be increased to m times, and the corresponding number of current levels can be increased to m(2n + 1). In this way, through calculation, the total number of bridge arms of the current source type converter in this embodiment is m(2n + 6), and the bridge arm level efficiency can be obtained as (2n + 1) / (2n + 6), that is, the same as the bridge arm level efficiency in some of the foregoing embodiments.

[0071] In some other embodiments of the present disclosure, the current source type converter can adopt a different inductance reduction architecture. Specifically, please combine Figure 2 and Figure 3 to understand that the inductance values of the second smoothing reactors 143 in each two-level converter 14 can be arranged in a geometric progression of 1: 2:... : 2(n - 1), and the sum of the inductance values of the second smoothing reactors 143 in each two-level converter 14 is the same as the inductance value of the first smoothing reactor 15. Thus, when the current source type converter provided in this embodiment is in steady-state operation, the current amplitude of the first smoothing reactor 15 is (2 n -1) times the minimum current amplitude in each second smoothing reactor 143.

[0072] In the above two-level converter 14, when the second arm 142 is blocked and the first arm 141 is conducting, a negative current with an amplitude of I is injected into the first port 11 of the multilevel converter 1. dc The amplitude I dc is the current amplitude of the second smoothing reactor 143. When the second arm 142 is conducting, the second smoothing reactor 143 conducts current through the second arm 142, and the port current of the two-level converter 14 is zero.

[0073] In the above main converter 2, the current at the DC port of the main converter 2 is the current of the first smoothing reactor 15 minus the port currents of all the two-level converters 14. Since n groups of two-level converters 14 can combine to produce 2 n current levels, the number of current levels at the DC port of this main converter 2 is 2 n . Also, in a half-bridge of one phase of the main converter 2, when the first arm 141 is conducting, a positive current level is injected into the corresponding phase's AC port, and the possible number of levels is the same as the number of current levels at the DC port, which is 2 n ; when the second arm 142 is conducting, a negative current level is injected into the corresponding phase's AC port, and the possible number of levels is also 2 n . Since the zero levels of the positive and negative current levels overlap, the total number of current levels at the total AC port 3 is (2 n+1 -1). Thus, through calculation, the total number of arms of the current-source converter in this embodiment is (2n + 6), and the arm level efficiency can be obtained as (2 n+1 -1) / (2n + 6).

[0074] In some other embodiments of the present disclosure, the current-source converter can adopt a structure of superimposing the same inductors. Specifically, please refer to Figure 9 , the multilevel converter 1 adopts a structure different from that in some of the foregoing embodiments. For example, the multilevel converter 1 includes: n groups of two-level converters 14 connected in parallel between the first port 11, the second port 12, and the third port 13 of the multilevel converter 1, where n is a positive integer greater than or equal to 1. That is, the two-level converter 14 is a three-terminal structure. The first ends of the n groups of two-level converters 14 are connected in parallel to the first port 11 of the multilevel converter 1, the second ends of the n groups of two-level converters 14 are connected in parallel to the second port 12 of the multilevel converter 1, and the third ends of the n groups of two-level converters 14 are connected in parallel to the third port 13 of the multilevel converter 1.

[0075] Exemplarily, please combine Figure 9 and Figure 10It is understood that the two-level converter 14 includes a first bridge arm 141 and a second bridge arm 142 connected in series with a common anode, and a second smoothing reactor 143. Among them, the cathode of the first bridge arm 141 (for example, the second port 145 of the two-level converter 14) is connected to the first port 11 of the multi-level converter 1, and the cathode of the second bridge arm 142 (for example, the third port 146 of the two-level converter 14) is connected to the second port 12 of the multi-level converter 1. One end of the second smoothing reactor 143 is connected between the first bridge arm 141 and the second bridge arm 142, and the other end (for example, the first port 144 of the two-level converter 14) is connected to the third port 13 of the multi-level converter 1.

[0076] On this basis, optionally, the main converter 2 adopts a three-phase converter.

[0077] Optionally, the first bridge arm 141, the second bridge arm 142, and the third bridge arm 21 are all composed of reverse-blocking fully controlled power semiconductor devices connected in series, and the number of series stages is greater than or equal to 1.

[0078] Optionally, the inductance values of the second smoothing reactors 143 of each two-level converter 14 are the same.

[0079] From the above, when the current source type converter provided in this embodiment is in steady-state operation, the current amplitudes of the second smoothing reactors 143 in each two-level converter 14 are approximately constant and basically the same.

[0080] In the above two-level converter 14, when the second bridge arm 142 is blocked and the first bridge arm 141 is conducting, a positive current with an amplitude of I is injected into the first port 11 of the multi-level converter 1. dc The amplitude I dc is the current amplitude of the second smoothing reactor 143. When the second bridge arm 142 is conducting, the second smoothing reactor 143 conducts current through the second bridge arm 142, and the port current of the two-level converter 14 is zero.

[0081] In the above-mentioned main converter 2, the current at the DC port of the main converter 2 is the sum of the port currents of all the two-level converters 14. Since n groups of two-level converters 14 can combine to produce (n + 1) current levels, the number of current levels at the DC port of this main converter 2 is (n + 1). Also, in one-phase half-bridge of the main converter 2, when the first arm 141 is conducting, a positive current level is injected into the AC port of the corresponding phase, and the possible number of levels is the same as the number of current levels at the DC port, which is (n + 1); when the second arm 142 is conducting, a negative current level is injected into the AC port of the corresponding phase, and the possible number of levels is also (n + 1). Since the zero levels of the positive and negative current levels overlap, the total number of current levels at the total AC port 3 is (2n + 1). Thus, through calculation, the total number of bridge arms of the current source converter in this embodiment is (2n + 6), and the bridge arm level efficiency can be obtained as (2n + 1) / (2n + 6).

[0082] In some other embodiments of the present disclosure, the current source converter may adopt a different inductance superposition type architecture. For example, please refer to Figure 9 , the multilevel converter 1 includes: n groups of two-level converters 14 connected in parallel between the first port 11, the second port 12, and the third port 13 of the multilevel converter 1, where n is a positive integer greater than or equal to 1. That is, the two-level converter 14 has a three-terminal structure, the first ends of the n groups of two-level converters 14 are connected in parallel to the first port 11 of the multilevel converter 1, the second ends of the n groups of two-level converters 14 are connected in parallel to the second port 12 of the multilevel converter 1, and the third ends of the n groups of two-level converters 14 are connected in parallel to the third port 13 of the multilevel converter 1.

[0083] On this basis, optionally, the main converter 2 adopts a three-phase converter.

[0084] Optionally, the first arm 141, the second arm 142, and the third arm 21 are all composed of reverse-blocking fully controlled power semiconductor devices connected in series, and the number of series stages is greater than or equal to 1.

[0085] Optionally, the inductance values of the second smoothing reactors 143 in each two-level converter 14 can be arranged in a geometric progression of 1: 2: … :2(n - 1).

[0086] From the above, when the current source converter provided in this embodiment is in steady-state operation, the current amplitudes of the second smoothing reactors 143 in each two-level converter 14 are approximately constant and their ratios are the same as the ratios of the corresponding inductance values.

[0087] In the above-mentioned two-level converter 14, when the second arm 142 is blocked and the first arm 141 is conducting, a positive current with an amplitude of I dc is injected into the first port 11 of the multilevel converter 1, and the amplitude I dcThat is the current amplitude of the second smoothing reactor 143. When the second arm 142 is conducting, the second smoothing reactor 143 conducts current through the second arm 142, and the port current of the two-level converter 14 is zero.

[0088] In the above-mentioned main converter 2, the current at the DC port of the main converter 2 is the sum of the port currents of all the two-level converters 14. Since n groups of two-level converters 14 can combine to produce 2 n kinds of current levels, the number of current levels at the DC port of this main converter 2 is 2 n . Moreover, in a half-bridge of one phase of the main converter 2, when the first arm 141 is conducting, a positive current level is injected into the AC port of the corresponding phase, and the possible number of levels is the same as the number of current levels at the DC port, which is 2 n ; when the second arm 142 is conducting, a negative current level is injected into the AC port of the corresponding phase, and the possible number of levels is also 2 n . Since the zero levels of the positive and negative current levels overlap, the total number of current levels at the total AC port 3 is (2 n+1 -1). Thus, through calculation, the total number of arms of the current-source converter in this embodiment is (2n + 6), and the arm level efficiency can be obtained as (2 n+1 -1) / (2n + 6).

[0089] In some other embodiments of the present disclosure, the current-source converter can also adopt a magnetic integration superposition architecture. For example, please refer to Figure 9 , the multilevel converter 1 includes: n groups of two-level converters 14 connected in parallel between the first port 11, the second port 12, and the third port 13 of the multilevel converter 1, where n is a positive integer greater than or equal to 1. That is, the two-level converter 14 has a three-terminal structure. The first ends of the n groups of two-level converters 14 are connected in parallel to the first port 11 of the multilevel converter 1, the second ends of the n groups of two-level converters 14 are connected in parallel to the second port 12 of the multilevel converter 1, and the third ends of the n groups of two-level converters 14 are connected in parallel to the third port 13 of the multilevel converter 1.

[0090] Exemplarily, please combine Figure 9 and Figure 11It is understood that the two-level converter 14 includes: a first bridge arm 141, a second bridge arm 142, a coupled inductor 147, a buffer capacitor 148, and a fifth bridge arm 149. Among them, one end of the first bridge arm 141 and one end of the second bridge arm 142 are connected to form the first port 144 of the two-level converter 14 and are connected to the third port 13 of the multi-level converter 1; the other end of the first bridge arm 141 is connected to one end of the first winding of the coupled inductor 147 and the first plate of the buffer capacitor 148; the other end of the second bridge arm 142 is connected to one end of the second winding of the coupled inductor 147 and the second plate of the buffer capacitor 148; the other ends of the first winding and the second winding of the coupled inductor 147 are connected to form the second port 145 of the two-level converter 14 and are connected to the first port 11 of the multi-level converter 1, as well as the anodic end of the fifth bridge arm 149; the cathodic end of the fifth bridge arm 149 (for example, the third port 146 of the two-level converter 14) is connected to the second port 12 of the multi-level converter 1.

[0091] On this basis, optionally, the main converter 2 adopts a three-phase converter.

[0092] Optionally, both the fifth bridge arm 149 and the third bridge arm 21 are composed of reverse-blocking fully-controlled power semiconductor devices connected in series, and the number of series stages is greater than or equal to 1.

[0093] Optionally, both the first bridge arm 141 and the second bridge arm 142 are composed of reverse-blocking fully-controlled power semiconductor devices or bidirectional fully-controlled power semiconductor devices connected in series, and the number of series stages is greater than or equal to 1. Among them, the bidirectional fully-controlled power semiconductor devices include, but are not limited to, bidirectional metal oxide semiconductor field effect transistors (Metal Oxide Semiconductor Field Effect Transistor, abbreviated as MOSFET), reverse-parallel connection of reverse-blocking devices or reverse-series connection of reverse-conducting devices, etc.

[0094] Optionally, the inductance values of the coupled inductors 147 of each two-level converter 14 are the same.

[0095] From the above, when the current source type converter provided in this embodiment is in steady-state operation, the current amplitudes of the coupled inductors 147 in each two-level converter 14 are approximately constant and basically the same.

[0096] In the above two-level converter 14, the first bridge arm 141 and the second bridge arm 142 can stabilize the total current amplitude of the coupled inductor 147 through switching actions. Thus, when the fifth bridge arm 149 is turned on, the coupled inductor 147 conducts freewheeling through the second bridge arm 142, and the output current of the second port 145 of the two-level converter 14 is zero. When the fifth bridge arm 149 is blocked, the coupled inductor 147 forcibly injects a positive current into the second port 145 of the two-level converter 14.

[0097] In the above-mentioned main converter 2, the current at the DC port of the main converter 2 is the sum of the port currents of all the two-level converters 14. Since n groups of two-level converters 14 can combine to produce (n + 1) current levels, the number of current levels at the DC port of this main converter 2 is (n + 1). Moreover, in one-phase half-bridge of the main converter 2, when the first bridge arm 141 is conducting, a positive current level is injected into the AC port of the corresponding phase, and the possible number of levels is the same as the number of current levels at the DC port, which is (n + 1); when the second bridge arm 142 is conducting, a negative current level is injected into the AC port of the corresponding phase, and the possible number of levels is also (n + 1). Since the zero levels of the positive and negative current levels overlap, the total number of current levels at the total AC port 3 is (2n + 1). Thus, through calculation, the total number of bridge arms of the current-source converter in this embodiment is (3n + 6), and the bridge-arm level efficiency can be obtained as (2n + 1) / (3n + 6).

[0098] In summary, compared with the change in the bridge-arm level efficiency of the current-source converter in the related art, each current-source converter provided in the embodiments of the present disclosure can effectively increase the bridge-arm level efficiency as the number of two-level converters increases. Figures 12 - 14 Exemplarily provided in it is a comparison chart of the bridge-arm level efficiency between the current-source converter provided in some embodiments of the present disclosure and the current-source converter in the related art, where Figure 12 is a comparison chart of the bridge-arm level efficiency between the same-inductance multi-level current-source converter provided in some embodiments of the present disclosure and the current-source converter in the related art Figure 13 is a comparison chart of the bridge-arm level efficiency between the different-inductance multi-level current-source converter provided in some embodiments of the present disclosure and the current-source converter in the related art Figure 14 is a comparison chart of the bridge-arm level efficiency between the magnetic-integration multi-level current-source converter provided in some embodiments of the present disclosure and the current-source converter in the related art.

[0099] Through analysis Figures 12 - 14 It can be seen that in each current-source converter provided in the embodiments of the present disclosure, as the number of two-level converters 14 (i.e., the n value) increases, the bridge-arm level efficiency increases synchronously. However, in the current-source converter provided in the related art, as the number of groups of topological units increases, its bridge-arm level efficiency decreases synchronously. Therefore, when the number of two-level converters 14 (i.e., the n value) in the current-source converter is greater than 1, the bridge-arm level efficiency of each current-source converter provided in the embodiments of the present disclosure is significantly better than that of the related art, having a better efficiency improvement effect.

[0100] Moreover, in each current source type converter provided in the embodiments of the present disclosure, not only can it have a high arm level efficiency, but it is also beneficial to use fewer arms and switching devices when generating the same number of levels, greatly reducing the implementation cost, control difficulty, and operating loss of the current source type converter, thereby further improving the power quality and control flexibility of the multilevel current source type converter, and further facilitating the generation of large current stresses of any shape on the device under test in the equivalent application condition test (i.e., it can have better current source programmable performance), so as to improve the equivalence and accuracy of the equivalent application condition test.

[0101] Some embodiments of the present disclosure also provide an equivalent application condition test circuit, including a current source; the current source includes the current source type converter described in any of the above embodiments. The equivalent application condition test circuit also has all the technical advantages of the foregoing current source type converter.

[0102] In addition, it can be understood that the current source type converter mentioned in the embodiments of the present disclosure can be applied not only to the above equivalent application condition test circuit, but also to any circuit, device, or equipment in the field of power electronics technology that requires the setting of a current source. The embodiments of the present disclosure do not make specific limitations in this regard.

[0103] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0104] The above embodiments only represent several implementation manners of the present disclosure, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present disclosure, several modifications and improvements can still be made, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure patent shall be subject to the appended claims.

Claims

1. A current source converter, characterized in that: include: A multi-level conversion unit, a total AC port and a total DC port; wherein, The multi-level conversion unit includes a multi-level converter and a main converter, and the multi-level converter and the main converter each have a first port, a second port and a third port; the total DC port has a first end and a second end; The first port of the multilevel converter is connected to the first port of the main converter; the second port of the multilevel converter is connected to the first end of the total DC port; the third port of the multilevel converter is connected to the second end of the total DC port; the second port of the main converter is connected to the second port of the multilevel converter and the first end of the total DC port; the third port of the main converter is connected to the total AC port; Wherein, the multi-level converter comprises: n a two-level converter connected in parallel between the first port and the second port of the multi-level converter, n is a positive integer greater than 1; and a first smoothing reactor connected in series to the third port of the multilevel converter and the n A two-level converter is provided between the two-level converters; the two-level converter comprises: a first bridge arm and a second bridge arm connected in series with a common cathode, and a second smoothing reactor connected in parallel to both ends of the second bridge arm; Alternatively, the multi-level converter comprises: n groups of two-level converters connected in parallel between the first port, the second port and the third port of the multi-level converter, where n is a positive integer greater than 1.

2. The current source converter according to claim 1, characterized in that: The main converter comprises: a three-phase converter formed by connecting six groups of third bridge arms; wherein, every two groups of the third bridge arms are connected in series to form a half bridge, and three groups of the half bridges are connected in parallel.

3. The current source converter according to claim 2, characterized in that: The first bridge arm, the second bridge arm and the third bridge arm are all composed of reverse resistance fully controlled power semiconductor devices connected in series; Alternatively, the first bridge arm and the second bridge arm are both composed of reverse-resistance fully-controlled power semiconductor devices connected in series; and the third bridge arm is composed of reverse-resistance half-controlled power semiconductor devices connected in series.

4. The current source converter according to claim 1, characterized in that: The main converter comprises: a single-phase converter formed by connecting four groups of fourth bridge arms.

5. The current source converter according to claim 1, characterized in that: The multi-level converter comprises: the n groups of two-level converters connected in parallel between the first port and the second port of the multi-level converter, and the n groups of two-level converters connected in series between the third port and the second port of the multi-level converter. n The first smoothing reactor is connected between two level converters; the two level converter comprises: the first bridge arm and the second bridge arm connected in series with a common cathode, and the second smoothing reactor connected in parallel to both ends of the second bridge arm; Wherein, the inductance value of the second smoothing reactor in each of the two-level converters is the same; Or, the inductance values ​​of the second smoothing reactors in each of the two-level converters are arranged in an equal proportion sequence of 1: 2: … : 2(n-1); Or, the inductance values ​​of the second smoothing reactors in each of the two-level converters are arranged in an equal proportion sequence of 1: 2: … : 2(n-1), and the sum of the inductance values ​​of the second smoothing reactors in each of the two-level converters is the same as the inductance value of the first smoothing reactor.

6. The current source converter according to claim 1, wherein: The number of the multi-level conversion units is m Group, m is a positive integer greater than or equal to 2; The third port of the main converter in each of the multi-level conversion units is connected in parallel to the total AC port; the second port of the multi-level converter in each of the multi-level conversion units is connected in parallel to the first end of the total DC port; the third port of the multi-level converter in each of the multi-level conversion units is connected in parallel to the second end of the total DC port; Alternatively, the third port of the main converter in each of the multi-level conversion units is connected in parallel to the total AC port; the multi-level converters in each of the multi-level conversion units are sequentially connected in series between the first end and the second end of the total DC port.

7. The current source converter according to claim 1, characterized in that: The multi-level converter comprises: the n groups of two-level converters connected in parallel between the first port, the second port and the third port of the multi-level converter, where n is a positive integer greater than 1; wherein the two-level converter comprises: A first bridge arm and a second bridge arm connected in series with a common anode; a cathode of the first bridge arm is connected to the first port of the multi-level converter, and a cathode of the second bridge arm is connected to the second port of the multi-level converter; A second smoothing reactor has one end connected between the first bridge arm and the second bridge arm, and the other end connected to the third port of the multi-level converter.

8. The current source converter according to claim 1, characterized in that: The multi-level converter comprises: n groups of two-level converters connected in parallel between the first port, the second port and the third port of the multi-level converter, where n is a positive integer greater than 1; wherein, The two-level converter includes: a first bridge arm, a second bridge arm, a coupled inductor, a buffer capacitor and a fifth bridge arm; one end of the first bridge arm and one end of the second bridge arm are connected and connected to the third port of the multi-level converter; the other end of the first bridge arm is connected to one end of the first winding in the coupled inductor and the first plate of the buffer capacitor; the other end of the second bridge arm is connected to one end of the second winding in the coupled inductor and the second plate of the buffer capacitor; the other end of the first winding and the other end of the second winding are connected and connected to the first port of the multi-level converter and the anode end of the fifth bridge arm; the cathode end of the fifth bridge arm is connected to the second port of the multi-level converter.

9. An equivalent application condition test circuit, characterized in that: Comprising a current source; the current source comprises a current source converter as described in any one of claims 1 to 8.

Images