An open-loop residual amplifier circuit for pipelined successive approximation ADCs

Abstract

This invention belongs to the field of integrated circuit technology, specifically relating to an open-loop residual amplifier circuit for pipelined successive approximation ADCs; it includes: a differential input circuit, a tail current circuit, a third PMOS transistor Mp3, a fourth PMOS transistor Mp4, a third NMOS transistor Mn3, and a fourth NMOS transistor Mn4; the third PMOS transistor Mp3, the fourth PMOS transistor Mp4, the third NMOS transistor Mn3, and the fourth NMOS transistor Mn4 are all connected to the differential input circuit; the tail current circuit is connected to the third NMOS transistor Mn3 and the fourth NMOS transistor Mn4; it does not require a very high open-loop gain, nor does it require a complex common-mode voltage detection circuit, resulting in a simple circuit structure and reduced circuit design difficulty; moreover, this invention is a dynamic circuit, which greatly reduces circuit power consumption and is suitable for low-power ADC design; this invention uses a push-pull input method, which greatly improves the input transconductance and has a large bandwidth, making it suitable for high-speed ADC design.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to an open-loop residual amplifier circuit applied to a pipelined successive approximation ADC. Background Technology

[0002] High-speed, high-precision analog-to-digital converters (ADCs) have seen rapid development in recent years. Single-channel ADCs with accuracies of 12 bits or higher and conversion speeds of hundreds of mega-samples per second are in high demand in various mixed-signal processing systems. Pipeline successive approximation ADCs (Pipeline SAR ADCs) are a popular architecture in ADC design in recent years. They combine the advantages of pipelined and successive approximation ADCs, leveraging the high speed and precision of pipelined ADCs while taking advantage of the low power consumption, small size, and ease of integration of successive approximation ADCs.

[0003] With the continuous advancement of CMOS technology, the performance of pipelined successive approximation ADCs is also constantly improving. However, the bottleneck hindering further performance enhancement is the residual amplifier (RA) between each stage of the sub-ADC. The main function of the residual amplifier is to accurately and linearly amplify the residual signal generated after quantization by the previous stage sub-ADC, for use in the next stage of quantization by the subsequent sub-ADC. Therefore, the gain accuracy, linearity, speed, and power consumption of the residual amplifier are the design challenges for highly accurate pipelined successive approximation ADCs.

[0004] Residual amplifiers used in pipelined successive approximation ADCs are mainly divided into open-loop and closed-loop structures. Overall, closed-loop residual amplifiers have the following problems:

[0005] 1) In the design of high-speed ADCs, advanced manufacturing processes are generally used to meet the sampling rate requirements. However, in advanced CMOS (Complementary Metal-Oxide-Semiconductor) manufacturing processes, the channel length of transistors is becoming smaller and smaller, and the intrinsic gain is becoming smaller and smaller. This makes it more difficult to design an operational amplifier with high open-loop gain. If a sufficiently high open-loop gain is not achieved, it will affect the closed-loop gain accuracy, linearity, and stability of the closed-loop residual amplifier.

[0006] 2) The common-mode instability of the operational amplifier output in a closed-loop residual amplifier can affect the circuit performance. More seriously, it may cause the transistor to enter the linear region, and the amplifier will not be able to perform amplification. Therefore, a CMFB (Commendation Feedback) circuit is needed to stabilize the common-mode voltage of the amplifier output, which increases the design difficulty of the circuit.

[0007] Based on the signal processing method, open-loop residual amplifiers are further classified into incompletely built-up open-loop amplifiers and fully built-up open-loop amplifiers. Incompletely built-up open-loop amplifiers have slower switching speeds and their accuracy is limited by the precision of the integration time control. Fully built-up open-loop amplifiers, on the other hand, do not require complex detection circuits and amplify the signal to the required gain to achieve stability. Summary of the Invention

[0008] To address the shortcomings of existing technologies, this invention proposes an open-loop residual amplifier circuit for pipelined successive approximation ADCs. The circuit includes: a differential input circuit, a tail current circuit, a third PMOS transistor Mp3, a fourth PMOS transistor Mp4, a third NMOS transistor Mn3, and a fourth NMOS transistor Mn4.

[0009] The third PMOS transistor Mp3, the fourth PMOS transistor Mp4, the third NMOS transistor Mn3, and the fourth NMOS transistor Mn4 are all connected to the differential input circuit; the tail current circuit is connected to the third NMOS transistor Mn3 and the fourth NMOS transistor Mn4.

[0010] Preferably, the differential input circuit includes a first NMOS transistor Mn1, a second NMOS transistor Mn2, a fifth NMOS transistor Mn5, a sixth NMOS transistor Mn6, a first PMOS transistor Mp1, a second PMOS transistor Mp2, a fifth PMOS transistor Mp5, and a sixth PMOS transistor Mp6; the gates of the second NMOS transistor Mn2, the fifth NMOS transistor Mn5, the second PMOS transistor Mp2, and the fifth PMOS transistor Mp5 are all connected to the first input signal VIP; the gates of the first NMOS transistor Mn1, the sixth NMOS transistor Mn6, the first PMOS transistor Mp1, and the sixth PMOS transistor Mp6 are all connected to the second input signal VIN; the source of the first PMOS transistor Mp1 is connected to the source of the fifth PMOS transistor Mp5 and the drain of the third PMOS transistor Mp3, and the drain of the first PMOS transistor Mp1 is connected to the third PMOS transistor Mp6. The gate of S-MOSFET Mp3, the drain of the first NMOS transistor Mn1, and the gate of the third NMOS transistor Mn3; the source of the second PMOS transistor Mp2 is connected to the source of the sixth PMOS transistor Mp6 and the drain of the fourth PMOS transistor Mp4, and the drain of the second PMOS transistor Mp2 is connected to the gate of the fourth PMOS transistor Mp4, the drain of the second NMOS transistor Mn2, and the gate of the fourth NMOS transistor Mn4; the source of the first NMOS transistor Mn1 is connected to the source of the fifth NMOS transistor Mn5 and the drain of the third PMOS transistor Mp3; the source of the second NMOS transistor Mn2 is connected to the source of the sixth NMOS transistor Mn6 and the drain of the fourth NMOS transistor Mn4; the drain of the fifth PMOS transistor Mp5 is connected to the drain of the fifth NMOS transistor Mn5, and the drain of the sixth PMOS transistor Mp6 is connected to the drain of the sixth PMOS transistor Mp6.

[0011] Furthermore, the drain of the fifth PMOS transistor Mp5 is connected to one end of the first capacitor via the first switch, and the drain of the sixth PMOS transistor Mp6 is connected to one end of the second capacitor via the second switch; the other ends of the first and second capacitors are both grounded.

[0012] Furthermore, the drain of the fifth PMOS transistor Mp5 is connected to one end of the resistor, and the drain of the sixth PMOS transistor Mp6 is connected to the other end of the resistor. The fifth PMOS transistor Mp5, the fifth NMOS transistor Mn5, the sixth PMOS transistor Mp6, the sixth PMOS transistor Mp6, and the resistor R1 form a push-pull output circuit.

[0013] Preferably, the tail current circuit includes a seventh PMOS transistor Mp7 and a seventh-type NMOS transistor Mn7; the source of the seventh PMOS transistor Mp7 is connected to the power supply VDD, and the drain of the seventh PMOS transistor Mp7 is connected to the drain of the seventh-type NMOS transistor Mn7, the source of the third NMOS transistor Mn3, and the source of the fourth NMOS transistor Mn4; the gates of the seventh PMOS transistor Mp7 and the seventh-type NMOS transistor Mn7 are both adjacent to the clock signal EN, and the source of the seventh-type NMOS transistor Mn7 is grounded.

[0014] Preferably, the source of the third PMOS transistor Mp3 and the source of the fourth PMOS transistor Mp4 are both connected to the power supply VDD.

[0015] The beneficial effects of this invention are as follows:

[0016] (1) The present invention uses an open-loop residual amplifier, and the open-loop gain is the amplification factor of the residual amplifier. It does not require a very high open-loop gain, which reduces the difficulty of circuit design.

[0017] (2) The differential input circuit structure of the present invention adopts the differential folded voltage follower (DFVF) structure, which enables the residual amplifier circuit to achieve high linearity when the input swing is large.

[0018] (3) This invention is a fully built residual amplifier that does not require complex timing control circuits.

[0019] (4) This invention is a dynamic circuit with a simple circuit structure, which greatly reduces the power consumption of the circuit and is suitable for low-power ADC design.

[0020] (5) The open-loop residual amplifier circuit proposed in this invention can improve the linearity of the circuit compared with the traditional open-loop residual amplifier.

[0021] (6) The present invention has a large bandwidth and is suitable for high-speed pipeline successive approximation ADCs. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the open-loop residual amplifier circuit structure applied to pipeline successive approximation ADC in this invention;

[0023] Figure 2 This is the timing diagram of the open-loop residual amplifier circuit used in the pipeline successive approximation ADC of this invention. Detailed Implementation

[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] This invention proposes an open-loop residual amplifier circuit for pipelined successive approximation ADCs. It employs an open-loop residual amplifier, where the open-loop gain is the same as the amplification factor of the residual amplifier. This eliminates the need for a very high open-loop gain, reducing the complexity of circuit design. Figure 1 As shown, the circuit includes: a differential input circuit, a tail current circuit, a third PMOS transistor Mp3, a fourth PMOS transistor Mp4, a third NMOS transistor Mn3, and a fourth NMOS transistor Mn4;

[0026] The third PMOS transistor Mp3, the fourth PMOS transistor Mp4, the third NMOS transistor Mn3, and the fourth NMOS transistor Mn4 are all connected to the differential input circuit; the tail current circuit is connected to the third NMOS transistor Mn3 and the fourth NMOS transistor Mn4.

[0027] In this embodiment, the differential input circuit includes a first NMOS transistor Mn1, a second NMOS transistor Mn2, a fifth NMOS transistor Mn5, a sixth NMOS transistor Mn6, a first PMOS transistor Mp1, a second PMOS transistor Mp2, a fifth PMOS transistor Mp5, and a sixth PMOS transistor Mp6; the gates of the second NMOS transistor Mn2, the fifth NMOS transistor Mn5, the second PMOS transistor Mp2, and the fifth PMOS transistor Mp5 are all connected to the first input signal VIP; the gates of the first NMOS transistor Mn1, the sixth NMOS transistor Mn6, the first PMOS transistor Mp1, and the sixth PMOS transistor Mp6 are all connected to the second input signal VIN; the source of the first PMOS transistor Mp1 is connected to the source of the fifth PMOS transistor Mp5 and the drain of the third PMOS transistor Mp3, and the drain of the first PMOS transistor Mp1 is connected to the third PMOS transistor Mp6. The gate of MOS transistor Mp3, the drain of the first NMOS transistor Mn1, and the gate of the third NMOS transistor Mn3; the source of the second PMOS transistor Mp2 is connected to the source of the sixth PMOS transistor Mp6 and the drain of the fourth PMOS transistor Mp4, and the drain of the second PMOS transistor Mp2 is connected to the gate of the fourth PMOS transistor Mp4, the drain of the second NMOS transistor Mn2, and the gate of the fourth NMOS transistor Mn4; the source of the first NMOS transistor Mn1 is connected to the source of the fifth NMOS transistor Mn5 and the drain of the third PMOS transistor Mp3; the source of the second NMOS transistor Mn2 is connected to the source of the sixth NMOS transistor Mn6 and the drain of the fourth NMOS transistor Mn4; the drain of the fifth PMOS transistor Mp5 is connected to the drain of the fifth NMOS transistor Mn5, and the drain of the sixth PMOS transistor Mp6 is connected to the drain of the sixth PMOS transistor Mp6.

[0028] In this circuit, both N-type and P-type MOSFETs are input simultaneously, which increases the input transconductance and thus the bandwidth of the amplifier.

[0029] Furthermore, the drain of the fifth PMOS transistor Mp5 is connected to one end of the first capacitor via the first switch, and the drain of the sixth PMOS transistor Mp6 is connected to one end of the second capacitor via the second switch; the other ends of the first and second capacitors are both grounded.

[0030] Furthermore, the drain of the fifth PMOS transistor Mp5 is connected to one end of the resistor, and the drain of the sixth PMOS transistor Mp6 is connected to the other end of the resistor. The fifth PMOS transistor Mp5, the fifth NMOS transistor Mn5, the sixth PMOS transistor Mp6, the sixth PMOS transistor Mp6, and the resistor R1 form a push-pull output circuit.

[0031] In this circuit, a first resistor is connected in parallel between the two output terminals. Adjusting the resistance value of the first resistor can adjust the output amplification factor to achieve the required amplification factor.

[0032] The tail current circuit includes a seventh PMOS transistor Mp7 and a seventh-type NMOS transistor Mn7; the source of the seventh PMOS transistor Mp7 is connected to the power supply VDD, and the drain of the seventh PMOS transistor Mp7 is connected to the drain of the seventh-type NMOS transistor Mn7, the source of the third NMOS transistor Mn3, and the source of the fourth NMOS transistor Mn4; the gates of the seventh PMOS transistor Mp7 and the seventh-type NMOS transistor Mn7 are both adjacent to the clock signal EN, and the source of the seventh-type NMOS transistor Mn7 is grounded.

[0033] The path of the tail current circuit is controlled by the EN clock. When the EN clock signal is high, the circuit works normally. When the EN clock signal is low, the current in the circuit is almost zero. This forms a dynamic open-loop residual amplifier, which greatly reduces the average power consumption of the amplifier.

[0034] In this invention, the connection of the first and third NMOS transistors forms a Flipped Voltage Follower (FVF), providing a current output with good linearity. Adding a fifth NMOS transistor constitutes a Differential Flipped Voltage Follower (DFVF), improving nonlinearity. The connection in the upper left corner converts current into voltage output, thus achieving a voltage output with good linearity. Combined with the right half, this forms a fully differential output circuit. The gate of Mn5 is connected to VIP, forming a differential input pair with Mn1. The source of Mn5 is connected to the source of Mn1, and the drain of Mn5 is connected to the load capacitor CL via a switch. Further addition of a PMOS transistor, connected in the same way as the NMOS transistors, completes impedance matching between the NMOS and PMOS transistors. Both the NMOS and PMOS transistors act as a differential pair, with the input signal simultaneously input through the differential pair, achieving a higher transconductance and thus increasing the bandwidth of the circuit proposed in this invention. A resistor R1 is connected in parallel to the two output ports to adjust the load resistance value, achieving the required open-loop gain and bandwidth. Switch S1 is connected to the negative output terminal on one end and to the upper stage board of the next-stage load capacitor on the other. Switch S2 is connected to the positive output terminal on one end and to the upper stage board of the next-stage load capacitor on the other. The CLK clock controls the switching on and off, forming a non-overlapping clock with the EN clock. When the CLK clock reaches its rising edge first, switches S1 and S2 turn on, connecting the load capacitor CL to the output of the open-loop residual amplifier. When the EN clock reaches its rising edge, the tail current source circuit turns on, and the entire open-loop residual amplifier begins operation, stabilizing and amplifying the margin signal generated after quantization by the previous Sub-ADC. When the CLK clock reaches its falling edge first, switches S1 and S2 turn off, locking the charge on the upper stage board of the load capacitor. When the EN clock reaches its falling edge, the open-loop residual amplifier stops operating. This reduces the power consumption of the open-loop residual amplifier within one operating cycle.

[0035] like Figure 2 As shown, the CLK clock needs to reach a high level before the EN clock. Switches S1 and S2 need to be closed first, and the load capacitor needs to be connected before the amplifier can work normally. After the signal is amplified, switches S1 and S2 need to be opened first before the amplifier stops working. In this way, the amplifier will not affect the subsequent circuit when it stops working.

[0036] In summary, this invention proposes an open-loop residual amplifier circuit for pipelined successive approximation ADCs. It employs a fully built-up open-loop residual amplifier, where the open-loop gain is the same as the residual amplifier's gain. This eliminates the need for very high open-loop gain and complex common-mode voltage detection circuits, reducing circuit design complexity. Furthermore, the dynamic circuit of this invention features a simple structure, significantly reducing power consumption and making it suitable for low-power ADC designs. The push-pull input method greatly improves input transconductance and provides a large bandwidth, making it suitable for high-speed ADC designs.

[0037] The above-described embodiments further illustrate the purpose, technical solution, and advantages of the present invention. It should be understood that the above-described embodiments are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made to the present invention within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An open-loop residual amplifier circuit for use in pipelined successive approximation ADCs, characterized in that, include: Differential input circuit, tail current circuit, third PMOS transistor Mp3, fourth PMOS transistor Mp4, third NMOS transistor Mn3 and fourth NMOS transistor Mn4; The third PMOS transistor Mp3, the fourth PMOS transistor Mp4, the third NMOS transistor Mn3, and the fourth NMOS transistor Mn4 are all connected to the differential input circuit; the tail current circuit is connected to the third NMOS transistor Mn3 and the fourth NMOS transistor Mn4. The differential input circuit includes a first NMOS transistor Mn1, a second NMOS transistor Mn2, a fifth NMOS transistor Mn5, a sixth NMOS transistor Mn6, a first PMOS transistor Mp1, a second PMOS transistor Mp2, a fifth PMOS transistor Mp5, and a sixth PMOS transistor Mp6; the gates of the second NMOS transistor Mn2, the fifth NMOS transistor Mn5, the second PMOS transistor Mp2, and the fifth PMOS transistor Mp5 are all connected to the first input signal VIP; the gates of the first NMOS transistor Mn1, the sixth NMOS transistor Mn6, the first PMOS transistor Mp1, and the sixth PMOS transistor Mp6 are all connected to the second input signal VIN; the source of the first PMOS transistor Mp1 is connected to the source of the fifth PMOS transistor Mp5 and the third PMOS transistor Mp6. The drain of transistor Mp3 is connected to the gate of the third PMOS transistor Mp3, the drain of the first NMOS transistor Mn1, and the gate of the third NMOS transistor Mn3; the source of the second PMOS transistor Mp2 is connected to the source of the sixth PMOS transistor Mp6 and the drain of the fourth PMOS transistor Mp4; the drain of the second PMOS transistor Mp2 is connected to the gate of the fourth PMOS transistor Mp4, the drain of the second NMOS transistor Mn2, and the gate of the fourth NMOS transistor Mn4; the source of the first NMOS transistor Mn1 is connected to the source of the fifth NMOS transistor Mn5 and the drain of the third PMOS transistor Mp3; the source of the second NMOS transistor Mn2 is connected to the source of the sixth NMOS transistor Mn6 and the drain of the fourth NMOS transistor Mn4. The drain of the fifth PMOS transistor Mp5 is connected to the drain of the fifth NMOS transistor Mn5, and the drain of the sixth PMOS transistor Mp6 is connected to the drain of the sixth PMOS transistor Mp6. The drain of the fifth PMOS transistor Mp5 is also connected to one end of the first capacitor through the first switch, and the drain of the sixth PMOS transistor Mp6 is also connected to one end of the second capacitor through the second switch; the other ends of the first and second capacitors are both grounded. The drain of the fifth PMOS transistor Mp5 is connected to one end of the resistor, and the drain of the sixth PMOS transistor Mp6 is connected to the other end of the resistor. The fifth PMOS transistor Mp5, the fifth NMOS transistor Mn5, the sixth PMOS transistor Mp6, the sixth PMOS transistor Mp6, and the resistor together form a push-pull output circuit. The source of the third PMOS transistor Mp3 and the source of the fourth PMOS transistor Mp4 are both connected to the power supply VDD.

2. The open-loop residual amplifier circuit for pipelined successive approximation ADCs according to claim 1, characterized in that, The tail current circuit includes a seventh PMOS transistor Mp7 and a seventh-type NMOS transistor Mn7; the source of the seventh PMOS transistor Mp7 is connected to the power supply VDD, and the drain of the seventh PMOS transistor Mp7 is connected to the drain of the seventh-type NMOS transistor Mn7, the source of the third NMOS transistor Mn3, and the source of the fourth NMOS transistor Mn4. The gate of the seventh PMOS transistor Mp7 and the gate of the seventh type NMOS transistor Mn7 are both connected to the clock signal EN, and the source of the seventh type NMOS transistor Mn7 is grounded.

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