Rail-to-rail input and output source follower circuit and instrumentation amplifier

Abstract

The invention provides a rail-to-rail input and output source follower circuit and an instrumentation amplifier. The rail-to-rail input and output source follower circuit comprises a first following unit, a second following unit and a third following unit, wherein the first following unit at least comprises a first common drain source follower, a first flip source follower and a first compensation circuit; the second following unit at least comprises a second common drain source follower, a second flip source follower and a second compensation circuit. According to the invention, low output impedance under low power consumption is realized by using the turnover source follower, and close following between an input signal and an output signal is realized by combining the cascaded common drain source follower and the turnover source follower, so that a level transfer effect is formed; and meanwhile, rail-to-rail input and output are realized by utilizing the symmetrical arrangement of the first following unit and the second following unit and matching with the design of the compensating circuit.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a rail-to-rail input and output source follower circuit and an instrumentation amplifier. Background Art

[0002] In the process of analyzing and processing weak low-frequency external signals, it is necessary to use an instrument amplifier with low-frequency noise to amplify them. Currently, the commonly used low-frequency noise removal technologies include chopping and self-alignment, both of which perform discrete processing on the signal. After amplification, there are glitches with a certain time domain width and voltage amplitude in the time domain curve of the signal. In order to remove the glitches, a filter must be used in the last stage of the instrument amplifier circuit to filter them out. The pre-filter circuit must have a very low output impedance to ensure that the cascade filter does not affect the gain of the instrument amplifier.

[0003] According to the above requirements, it is of great significance to study a source follower circuit structure with low output impedance and rail-to-rail input and output. Summary of the invention

[0004] The purpose of the embodiments of the present disclosure is to provide a rail-to-rail input and output source follower circuit and an instrumentation amplifier to solve the problem of the instrumentation amplifier in the prior art requiring a low output impedance, rail-to-rail input and output source follower.

[0005] The embodiment of the present disclosure adopts the following technical solution: a rail-to-rail input and output source follower circuit, comprising at least: an input node, an output node, a first follower unit and a second follower unit; wherein the input node is used to receive an input signal, and the output node is used to provide an output signal; the first follower unit comprises at least a first common-drain source follower, a first flip source follower and a first compensation circuit, wherein the first common-drain source follower is used to reduce the level value of the input signal; the first flip source follower is used to raise the level value and then output it, so that the level value of the output signal is the same as the level value of the input signal; the first compensation circuit is used to compensate the first flip source follower; the second follower unit comprises at least a second common-drain source follower, a second flip source follower and a second compensation circuit, wherein the second common-drain source follower is used to raise the level value of the input signal; the second flip source follower is used to lower the level value and then output it, so that the level value of the output signal is the same as the level value of the input signal; the second compensation circuit is used to compensate the second flip source follower.

[0006] In some embodiments, when the input signal is a positive power rail input, the first follower unit is in an operating state and the second follower unit is in a disconnected state; when the input signal is a negative power rail input, the first follower unit is in a disconnected state and the second follower unit is in an operating state.

[0007] In some embodiments, the first common-drain-source follower includes a first transistor M1 and a second transistor M2, the gate of the first transistor M1 is connected to the input node, the source of the first transistor M1 leads to the output end of the first common-drain-source follower and is connected to the drain of the second transistor M2, the drain of the first transistor M1 is connected to a first operating voltage, and the source of the second transistor M2 is connected to a second operating voltage; the second common-drain-source follower includes a fourteenth transistor M14 and a fifteenth transistor M15, the gate of the fourteenth transistor M14 is connected to the input node, the source of the fourteenth transistor M14 leads to the output end of the second common-drain-source follower and is connected to the drain of the fifteenth transistor M15, the drain of the fourteenth transistor M14 is connected to the second operating voltage, and the source of the fifteenth transistor M15 is connected to the first operating voltage.

[0008] In some embodiments, the first transistor M1 and the second transistor M2 are N-type transistors, and the fourteenth transistor M14 and the fifteenth transistor M15 are P-type transistors.

[0009] In some embodiments, the first flip source follower at least includes: a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6 and a seventh transistor M7, wherein the gate of the third transistor M3 is connected to the output end of the first common drain source follower, the source of the third transistor M3 leads to the output end of the first flip source follower and is connected to the drain of the fourth transistor M4, the drain of the third transistor M3 is connected to the drain of the sixth transistor M6, the source of the sixth transistor M6 is connected to the second working voltage, the source of the fourth transistor M4 and the source of the seventh transistor M7 are connected to the first working voltage, the gate of the fourth transistor M4 is connected to the drain of the seventh transistor M7 and the drain of the fifth transistor M5, and is connected to the first bias voltage Vpin, the source of the fifth transistor M5 is connected to the drain of the sixth transistor M6, and the gates of the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 are respectively connected to their respective bias voltages; the second flip source follower at least includes: a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6 and a seventh transistor M7, wherein the gate of the third transistor M3 is connected to the output end of the first common drain source follower, the source of the third transistor M3 is connected to the drain of the sixth transistor M6, the gates of the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 are respectively connected to their respective bias voltages; a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18, a nineteenth transistor M19 and a twentieth transistor M20, wherein the gate of the seventeenth transistor M17 is connected to the output end of the second common drain source follower, the source of the seventeenth transistor M17 leads to the output end of the second flip source follower and is connected to the drain of the eighteenth transistor M18, the drain of the seventeenth transistor M17 is connected to the drain of the sixteenth transistor M16, and the source of the sixteenth transistor M16 is connected to the first working Voltage, the source of the eighteenth transistor M18 and the source of the twentieth transistor M20 are connected to the second operating voltage, the gate of the eighteenth transistor M18 is connected to the drain of the twentieth transistor M20 and the drain of the nineteenth transistor M19, and is connected to the second bias voltage Vnin, the source of the nineteenth transistor M19 is connected to the drain of the seventeenth transistor M17, and the gates of the sixteenth transistor M16, the nineteenth transistor M19 and the twentieth transistor M20 are respectively connected to their own bias voltages.

[0010] In some embodiments, the third transistor M3, the fourth transistor M4, the seventh transistor M7, the sixteenth transistor M16 and the nineteenth transistor M19 are all P-type transistors, and the fifth transistor M5, the sixth transistor M6, the seventeenth transistor M17, the eighteenth transistor M18 and the twentieth transistor M20 are all N-type transistors.

[0011] In some embodiments, the first compensation circuit at least includes: an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, and a thirteenth transistor M13, wherein the gate of the eighth transistor M8 is connected to the input node, the source of the eighth transistor M8 is connected to the second working voltage, the drain of the eighth transistor M8 is connected to the drain of the eleventh transistor M11 and the gate and drain of the ninth transistor M9, the source of the eleventh transistor M11 is connected to the first working voltage, and the source of the ninth transistor M9 is connected to the gate and drain of the eleventh transistor M11. The source of the tenth transistor M10 and the source of the tenth transistor M10 are connected to the second working voltage, the gate of the tenth transistor M10 is connected to the gate of the ninth transistor M9, the drain of the tenth transistor M10 is connected to the drain and gate of the twelfth transistor M12, the sources of the twelfth transistor M12 and the thirteenth transistor M13 are connected to the first working voltage, the gate of the thirteenth transistor M13 is connected to the gate of the twelfth transistor M12, and the drain of the thirteenth transistor M13 is connected to the first bias voltage Vpin; the second compensation circuit at least includes: a twenty-first transistor M21, a twenty-second transistor M22, a twenty-third transistor M23, a twenty-fourth transistor M24, a twenty-fifth transistor M25 and a twenty-sixth transistor M26; wherein the gate of the twenty-first transistor M21 is connected to the input node, the source of the twenty-first transistor M21 is connected to the first operating voltage, the drain of the twenty-first transistor M21 is connected to the drain of the twenty-second transistor M22 and the drain and gate of the twenty-third transistor M23, the source of the twenty-second transistor M22 is connected to the second operating voltage, and the source of the twenty-third transistor M23 is connected to the second operating voltage. The source and the source of the twenty-fourth transistor M24 are both connected to the first operating voltage, the gate of the twenty-fourth transistor M24 is connected to the gate of the twenty-third transistor M23, the drain of the twenty-fourth transistor M24 is connected to the drain and gate of the twenty-fifth transistor M25, the source of the twenty-fifth transistor M25 and the source of the twenty-sixth transistor M26 are both connected to the second operating voltage, the gate of the twenty-sixth transistor M26 is connected to the gate of the twenty-fifth transistor M25, and the drain of the twenty-sixth transistor M26 is connected to the second bias voltage Vnin.

[0012] In some embodiments, the sources of the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the twenty-second transistor M22, the twenty-fifth transistor M25 and the twenty-sixth transistor M26 are all N-type transistors; the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, the twenty-first transistor M21, the twenty-third transistor M23 and the twenty-fourth transistor M24 are all P-type transistors.

[0013] In some embodiments, the method further includes: a common-mode feedback unit, wherein the common-mode feedback unit is used to provide the first bias voltage Vpin and the second bias voltage Vnin to the first inverted source follower and the second inverted source follower.

[0014] The embodiment of the present disclosure further provides an instrument amplifier, which comprises at least: a signal amplification circuit, a source follower circuit as described above, and a filter circuit connected in sequence.

[0015] The beneficial effects of the embodiments of the present disclosure are: using a flip-type source follower to achieve low output impedance under low power consumption, and combining a cascaded common-drain source follower and a flip-type source follower to achieve close following between the input signal and the output signal, forming a level transfer effect, and at the same time using the symmetrical setting of the first follower unit and the second follower unit in conjunction with the design of the compensation circuit to achieve rail-to-rail input and output. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate one or more embodiments of this specification or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0017] Figure 1 It is a structural block diagram of a source follower circuit with rail-to-rail input and output in the first embodiment of the present disclosure;

[0018] Figure 2 It is a circuit structure principle diagram of a source follower circuit with rail-to-rail input and output in the first embodiment of the present disclosure;

[0019] Figure 3 is a circuit structure schematic diagram of a common-mode feedback unit in the first embodiment of the present disclosure;

[0020] Figure 4 Schematic diagram of the structure of the instrument amplifier in the second embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] In order to enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the following will be combined with the drawings in one or more embodiments of this specification to clearly and completely describe the technical solutions in one or more embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on one or more embodiments of this specification, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this document.

[0022] In the process of analyzing and processing weak low-frequency external signals, it is necessary to use an instrument amplifier with low-frequency noise to amplify them. Currently, the commonly used low-frequency noise removal technologies include chopping and self-alignment, both of which perform discrete processing on the signal. The time domain curve of the amplified signal has glitches with a certain time domain width and voltage amplitude. In order to remove the glitches, a filter must be used in the last stage of the instrument amplifier circuit to filter them out. The front stage circuit of the filter must have a very low output impedance to ensure that the cascade filter does not affect the gain of the instrument amplifier. According to the above requirements, the front stage of the filter and the back stage of the signal amplification module must use a source follower circuit structure with low output impedance.

[0023] In order to solve the above problems, the first embodiment of the present disclosure provides a source follower circuit with rail-to-rail input and output, and its structural block diagram is as follows: Figure 1 As shown, it mainly includes an input node for accessing an input signal Vin, an output node for providing an output signal Vout, and a first follower unit 10 and a second follower unit 20 connected between the input node and the output node; wherein the first follower unit 10 mainly includes a first common-drain source follower 11, a first flip source follower 12 and a first compensation circuit 13, the first common-drain source follower 11 is used to reduce the level value of the input signal Vin; the first flip source follower 12 is used to raise the level value and then output it, so that the level value of the output signal Vout is equal to The level value of the input signal Vin is the same; the first compensation circuit 13 is used to compensate the first inverted source follower 12; similarly, the second follower unit 20 at least includes a second common drain source follower 21, a second inverted source follower 22 and a second compensation circuit 23, the second common drain source follower 21 is used to raise the level value of the input signal Vin; the second inverted source follower 22 is used to reduce the level value and then output it, so that the level value of the output signal Vout is the same as the level value of the input signal Vin; the second compensation circuit 23 is used to compensate the second inverted source follower 22.

[0024] For the first follower unit 10 and the second follower unit 20 of the present embodiment, the two are actually symmetrical circuits with the same connection structure, and the difference is that the types of transistors used in the first follower unit 10 and the second follower unit 20 are opposite, so that the two are used to process input signals with different polarities when they are in working state. In particular, in the process of realizing rail-to-rail output, when the input signal is a positive power rail or a negative power rail, only one side of the first follower unit 10 and the second follower unit 20 is in a normal working state and the other side is turned off, thereby realizing the voltage following function, and when the input signal is between the positive power rail and the negative power rail, the two follower units work simultaneously.

[0025] Figure 2 FIG. 2 shows a schematic diagram of the circuit structure of a source follower circuit with rail-to-rail input and output in this embodiment, and uses dotted boxes to mark the specific circuits of the first follower unit 10 and the second follower unit 20. Figure 2 As shown, the first common drain source follower includes a first transistor M1 and a second transistor M2, wherein the gate of the first transistor M1 is connected to the input node to access the input signal Vin, the source of the first transistor M1 leads to the output end of the first common drain source follower and is connected to the drain of the second transistor M2, the drain of the first transistor M1 is connected to the first working voltage VDD, and the source of the second transistor M2 is connected to the second working voltage VSS to reduce the level value of the input signal Vin. Corresponding to the design of the first common drain source follower in the first follower unit 10, the second common drain source follower in the second follower unit 20 mainly includes a fourteenth transistor M14 and a fifteenth transistor M15, the gate of the fourteenth transistor M14 is connected to the input node, the source of the fourteenth transistor M14 leads to the output end of the second common drain source follower and is connected to the drain of the fifteenth transistor M15, the drain of the fourteenth transistor M14 is connected to the second working voltage, and the source of the fifteenth transistor M15 is connected to the first working voltage to achieve the function of raising the level value of the input signal Vin.

[0026] In such Figure 2 In the example shown, the first transistor M1 and the second transistor M2 are N-type transistors, and the fourteenth transistor M14 and the fifteenth transistor M15 are P-type transistors. In a specific implementation, the first transistor M1 and the second transistor M2 can also be set as P-type transistors, and the fourteenth transistor M14 and the fifteenth transistor M15 can be set as N-type transistors, as long as the transistors at the same position in the first common drain source follower and the second common drain source follower are of opposite types.

[0027] Further Figure 2As shown, the first inverted source follower at least includes: a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6 and a seventh transistor M7, wherein the gate of the third transistor M3 is connected to the output end of the first common-drain source follower, the source of the third transistor M3 leads to the output end of the first inverted source follower and is connected to the drain of the fourth transistor M4, the drain of the third transistor M3 is connected to the drain of the sixth transistor M6, the source of the sixth transistor M6 is connected to the second working voltage VSS, the source of the fourth transistor M4 and the source of the seventh transistor M7 are connected to the first working voltage VDD, the gate of the fourth transistor M4 is connected to the drain of the seventh transistor M7 and the drain of the fifth transistor M5, and is connected to the first bias voltage Vpin, the source of the fifth transistor M5 is connected to the drain of the sixth transistor M6, the gate of the fifth transistor M5, the gate of the sixth transistor M6 and the gate of the seventh transistor M7 are respectively connected to their own bias voltages, which are vb3, Vp and vb1 respectively. Corresponding to the design of the first flip source follower in the first follower unit 10, the second flip source follower in the second follower unit 20 at least includes: a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18, a nineteenth transistor M19 and a twentieth transistor M20, wherein the gate of the seventeenth transistor M17 is connected to the output end of the second common drain source follower, the source of the seventeenth transistor M17 leads to the output end of the second flip source follower and is connected to the drain of the eighteenth transistor M18, the drain of the seventeenth transistor M17 is connected to the drain of the sixteenth transistor M16, and the drain of the tenth transistor M20 is connected to the drain of the sixteenth transistor M16. The source of the sixth transistor M16 is connected to the first operating voltage VDD, the source of the eighteenth transistor M18 and the source of the twentieth transistor M20 are connected to the second operating voltage VSS, the gate of the eighteenth transistor M18 is connected to the drain of the twentieth transistor M20 and the drain of the nineteenth transistor M19, and is connected to the second bias voltage Vnin, the source of the nineteenth transistor M19 is connected to the drain of the seventeenth transistor M17, the gate of the sixteenth transistor M16, the gate of the nineteenth transistor M19 and the gate of the twentieth transistor M20 are respectively connected to their respective bias voltages, which are Vn, vb4 and vb2 respectively.

[0028] In such Figure 2 In the example shown, the third transistor M3, the fourth transistor M4, the seventh transistor M7, the sixteenth transistor M16 and the nineteenth transistor M19 are all P-type transistors, and the fifth transistor M5, the sixth transistor M6, the seventeenth transistor M17, the eighteenth transistor M18 and the twentieth transistor M20 are all N-type transistors. Similar to the first common-drain source follower and the second common-drain source follower, the transistor types at the same position in the first flip source follower and the second flip source follower can be opposite.

[0029] Further Figure 2 As shown, the first compensation circuit at least includes: an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12 and a thirteenth transistor M13, wherein the gate of the eighth transistor M8 is connected to the input node, the source of the eighth transistor M8 is connected to the second operating voltage VSS, the drain of the eighth transistor M8 is connected to the drain of the eleventh transistor and the gate and drain of the ninth transistor M9, the source of the eleventh transistor M11 is connected to the first operating voltage VDD, the source of the ninth transistor M9 and the source of the tenth transistor M10 are both connected to the second operating voltage VSS, the gate of the tenth transistor M10 is connected to the gate of the ninth transistor M9, the drain of the tenth transistor M10 is connected to the drain and gate of the twelfth transistor M12, the sources of the twelfth transistor M12 and the thirteenth transistor M13 are both connected to the first operating voltage VDD, the gate of the thirteenth transistor M13 is connected to the gate of the twelfth transistor M12, and the drain of the thirteenth transistor M13 is connected to the first bias voltage Vpin. Corresponding to the design of the first compensation circuit in the first follower unit 10, the second compensation circuit in the second follower unit 20 at least includes: a twenty-first transistor M21, a twenty-second transistor M22, a twenty-third transistor M23, a twenty-fourth transistor M24, a twenty-fifth transistor M25 and a twenty-sixth transistor M26; wherein the gate of the twenty-first transistor M21 is connected to the input node, the source of the twenty-first transistor M21 is connected to the first operating voltage VDD, the drain of the twenty-first transistor M21 is connected to the drain of the twenty-second transistor M22 and the drain and gate of the twenty-third transistor M23, and the twenty-second transistor M22 is connected to the input node. The source of the twenty-third transistor M23 and the source of the twenty-fourth transistor M24 are both connected to the first operating voltage VDD, the gate of the twenty-fourth transistor M24 is connected to the gate of the twenty-third transistor M23, the drain of the twenty-fourth transistor M24 is connected to the drain and gate of the twenty-fifth transistor M25, the source of the twenty-fifth transistor M25 and the source of the twenty-sixth transistor M26 are both connected to the second operating voltage VSS, the gate of the twenty-sixth transistor M26 is connected to the gate of the twenty-fifth transistor M25, and the drain of the twenty-sixth transistor M26 is connected to the second bias voltage Vnin.

[0030] In such Figure 2In the example shown, the sources of the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the twenty-second transistor M22, the twenty-fifth transistor M25 and the twenty-sixth transistor M26 are all N-type transistors; the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, the twenty-first transistor M21, the twenty-third transistor M23 and the twenty-fourth transistor M24 are all P-type transistors. Similar to the first common drain source follower and the second common drain source follower, the types of transistors at the same position in the first compensation circuit and the second compensation circuit can be opposite.

[0031] Combine the following Figure 2 The working principle of the source follower of this embodiment is explained. Corresponding to the first follower unit 10, the first common drain source follower mainly realizes the function of lowering the level, and the first flip source follower connected thereto can realize the raising of the level value, so that the output level can be consistent with the input level. At the same time, the first flip source follower composed of M3, M4, M5, M6, and M7 uses the signal path composed of M3, M5, M6, and M7 to form a feedback branch from the M4 gate to the M4 drain signal path. The feedback branch and the M4 gate to the M4 drain signal path construct a voltage and current negative feedback, thereby reducing the impedance of the M4 drain, that is, the small signal impedance of the output end. The second follower unit 20 combines the cascaded second common drain source follower and the second flip source follower to achieve low output impedance. The principle is similar to that of the first follower unit, and will not be repeated here.

[0032] When the source follower of the present embodiment realizes rail-to-rail output, when the input signal is a positive power rail, the input tube M1 of the first common-drain source follower of the first follower unit and the input tube M3 of the first flip source follower are normally turned on, while the input tube M14 of the second common-drain source follower of the second follower unit and the input tube M17 of the second flip source follower are forced to be turned off. At this time, the first follower unit can be used alone to realize the voltage following function; when the input signal is a negative power rail, it is opposite to the case of outputting a positive power rail. At this time, the input tube M1 of the first common-drain source follower of the first follower unit and the input tube M3 of the first flip source follower are forced to be turned off, while the input tube M14 of the second common-drain source follower of the second follower unit and the input tube M17 of the second flip source follower are in a normally turned-on state. At this time, the second follower unit can be used alone to realize the voltage following function; when the input signal is between the positive and negative power rails, the first follower unit and the second follower unit work simultaneously.

[0033] It should be understood that, corresponding to the first follower unit, M5 and M7 provide a branch that bears the bias current of M6. When the input is not a negative power rail, the branch is equivalent to the wire between the gate of M4 and the drain of M3 in the traditional flip structure, and the flip loop works normally at this time; when the negative power rail is input, the first follower unit will be in a disconnected state only when there is no bias current flowing into the branch M3, and it will not affect the normal operation of the second follower unit; if the compensation circuit is not set, the bias current of M6 is higher than that of M5 and M7. When the input is a negative power rail, part of the current of M6 will flow into M7, and the other part will flow into M3, resulting in The first flip source follower is always in the on state, so the first compensation circuit is set in this embodiment. When the input is a negative power rail, M8 is turned off, and the current of M11 flows into M9, and then M10, M12 and M13 mirror the current and pass it to the drain of M7. This embodiment further sets the sum of the current and the current of M7 to be the same as the current of M6. At this time, the current of M6 is the same as the current of M5, and no current will flow into M3. The first flip source drain follower is turned off, that is, the first follower unit is turned off. When the input signal is not a negative power rail, M8 is turned on, and the current of M11 flows into M8. The above-mentioned mirror current disappears, and the first follower unit is turned on normally. Similarly, when the input signal is a positive power rail, the principle of the second compensation circuit compensating the second flip source follower is the same as the first compensation circuit, and it will not be repeated here.

[0034] In addition, in some embodiments, a series structure of a resistor Rn and a capacitor Cn is connected in parallel at both ends of the source and drain of M13 to degrade the main pole of the transfer function in the flip loop and provide a left zero point to ensure the stability of the flip closed loop so that it can have a certain degree of driving capacitance. Similarly, a series structure of a resistor Rp and a capacitor Cp is connected in parallel at both ends of the source and drain of M26, and its function is similar to that of the series structure of a resistor Rn and a capacitor Cn, which will not be described in detail here.

[0035] In some embodiments, due to the introduction of the M5, M7, M19 and M20 branches, in order to avoid the circuit from entering other degenerate points, a common-mode feedback unit CMFB can also be set in the source follower to provide a static operating point for the first flip source follower and the second flip source follower. Specifically, the first bias voltage Vpin input to the gate of M4 in the first follower unit and the second bias voltage Vnin input to the gate of M18 in the second follower unit are used as inputs of the common-mode feedback unit, and the output of the common-mode feedback unit is the bias voltage Vp input to the gate of M6 and the bias voltage Vn input to the gate of M16, so as to fix the gate voltages of M7, M6, M18 and M16 in the first flip source follower and the second flip source follower.

[0036] Figure 3 FIG. 2 shows a circuit structure schematic diagram of the common mode feedback unit CMFB. Figure 3 As shown, the circuit structure composed of the twenty-seventh transistor M27, the twenty-eighth transistor M28, the twenty-ninth transistor M29, the thirtieth transistor M30, the thirty-first transistor M31, the thirty-second transistor M32, the thirty-third transistor M33 and the resistor R0 and the resistor R1 is used to obtain the common mode level of the first bias voltage Vpin and the second bias voltage Vnin, and the common mode level is output by the source of M30 and M31; the OTA circuit composed of the thirty-fourth transistor M34, the thirty-fifth transistor M35, the thirty-sixth transistor M36, the thirty-seventh transistor M37 and the thirty-eighth transistor M38 is used to amplify the difference between the obtained common mode level and the reference level vb6 and output it to Vp, and Vp outputs Vn which is inverted with Vp through the common source amplifier composed of the forty-third transistor M43 and the forty-first transistor M41. From this, it can be analyzed that the phase from Vpin to Vp through the CMFB module is the same, and the phase from Vp to Vpin through M6 is inverted, so that the entire common mode feedback loop is negative feedback, and the signal path from Vnin to Vn is the same. The capacitor Ccp, the thirty-ninth transistor M39 and the fortieth transistor M40 form a miller compensation bridged between Vp and Vpin to provide a left zero point to stabilize the loop. The capacitor Ccn, the forty-second transistor M42 and the forty-fourth transistor M44 function in the same way.

[0037] This embodiment utilizes a flip-type source follower to achieve low output impedance at low power consumption, and combines a cascaded common-drain source follower and a flip-type source follower to achieve close following between the input signal and the output signal, forming a level transfer effect. At the same time, the symmetrical setting of the first follower unit and the second follower unit is combined with the design of a compensation circuit to achieve rail-to-rail input and output.

[0038] The second embodiment of the present disclosure provides an instrument amplifier, and its structural diagram is as follows: Figure 4 As shown, it mainly includes a signal amplification circuit 100, a source follower circuit 200 provided in the first embodiment of the present disclosure, and a filter circuit 300 which are connected in sequence, so that the output impedance of the amplified signal is reduced, and rail-to-rail input and output can be performed, so that the filtered result is more accurate.

[0039] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A rail-to-rail input and output source follower circuit, characterized in that: At least: An input node, an output node, a first follower unit and a second follower unit; wherein, The input node is used to receive an input signal, and the output node is used to provide an output signal; The first follower unit at least includes a first common-drain source follower, a first flip source follower and a first compensation circuit, wherein the first common-drain source follower is used to reduce the level value of the input signal; The first inverted source follower is used to raise the level value and then output it, so that the level value of the output signal is the same as the level value of the input signal; the first compensation circuit is used to compensate the first inverted source follower; The second follower unit at least includes a second common-drain source follower, a second inverted source follower and a second compensation circuit. The second common-drain source follower is used to raise the level value of the input signal; the second inverted source follower is used to reduce the level value and then output it so that the level value of the output signal is the same as the level value of the input signal; the second compensation circuit is used to compensate the second inverted source follower.

2. The source follower circuit according to claim 1, characterized in that: When the input signal is a positive power rail input, the first follower unit is in a working state, and the second follower unit is in a disconnected state; In the case where the input signal is a negative power rail input, the first follower unit is in a disconnected state, and the second follower unit is in an operational state.

3. The source follower circuit according to claim 1, characterized in that: The first common-drain source follower includes a first transistor M1 and a second transistor M2, the gate of the first transistor M1 is connected to the input node, the source of the first transistor M1 leads to the output end of the first common-drain source follower and is connected to the drain of the second transistor M2, the drain of the first transistor M1 is connected to a first operating voltage, and the source of the second transistor M2 is connected to a second operating voltage; The second common-drain-source follower includes a fourteenth transistor M14 and a fifteenth transistor M15, the gate of the fourteenth transistor M14 is connected to the input node, the source of the fourteenth transistor M14 leads to the output end of the second common-drain-source follower and is connected to the drain of the fifteenth transistor M15, the drain of the fourteenth transistor M14 is connected to the second operating voltage, and the source of the fifteenth transistor M15 is connected to the first operating voltage.

4. The source follower circuit according to claim 3, characterized in that: The first transistor M1 and the second transistor M2 are N-type transistors, and the fourteenth transistor M14 and the fifteenth transistor M15 are P-type transistors.

5. The source follower circuit according to claim 3, characterized in that: The first inverted source follower at least includes: a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6 and a seventh transistor M7, wherein the gate of the third transistor M3 is connected to the output end of the first common-drain source follower, the source of the third transistor M3 leads to the output end of the first inverted source follower and is connected to the drain of the fourth transistor M4, the drain of the third transistor M3 is connected to the drain of the sixth transistor M6, the source of the sixth transistor M6 is connected to the second working voltage, the source of the fourth transistor M4 and the source of the seventh transistor M7 are connected to the first working voltage, the gate of the fourth transistor M4 is connected to the drain of the seventh transistor M7 and the drain of the fifth transistor M5, and is connected to the first bias voltage Vpin, the source of the fifth transistor M5 is connected to the drain of the sixth transistor M6, and the gate of the fifth transistor M5, the gate of the sixth transistor M6 and the gate of the seventh transistor M7 are respectively connected to their respective bias voltages; The second flip source follower at least includes: a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18, a nineteenth transistor M19 and a twentieth transistor M20, wherein the gate of the seventeenth transistor M17 is connected to the output end of the second common drain source follower, the source of the seventeenth transistor M17 leads to the output end of the second flip source follower and is connected to the drain of the eighteenth transistor M18, the drain of the seventeenth transistor M17 is connected to the drain of the sixteenth transistor M16, and the source of the sixteenth transistor M16 is connected to the drain of the sixteenth transistor M16. The first operating voltage is connected, the source of the eighteenth transistor M18 and the source of the twentieth transistor M20 are connected to the second operating voltage, the gate of the eighteenth transistor M18 is connected to the drain of the twentieth transistor M20 and the drain of the nineteenth transistor M19, and is connected to the second bias voltage Vnin, the source of the nineteenth transistor M19 is connected to the drain of the seventeenth transistor M17, and the gate of the sixteenth transistor M16, the gate of the nineteenth transistor M19 and the gate of the twentieth transistor M20 are respectively connected to their own bias voltages.

6. The source follower circuit according to claim 5, characterized in that: The third transistor M3, the fourth transistor M4, the seventh transistor M7, the sixteenth transistor M16 and the nineteenth transistor M19 are all P-type transistors, and the fifth transistor M5, the sixth transistor M6, the seventeenth transistor M17, the eighteenth transistor M18 and the twentieth transistor M20 are all N-type transistors.

7. The source follower circuit according to claim 5, characterized in that: The first compensation circuit at least includes: an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12 and a thirteenth transistor M13, wherein the gate of the eighth transistor M8 is connected to the input node, the source of the eighth transistor M8 is connected to the second working voltage, the drain of the eighth transistor M8 is connected to the drain of the eleventh transistor M11 and the gate and drain of the ninth transistor M9, the source of the eleventh transistor M11 is connected to the first working voltage, and the ninth transistor M9 is connected to the gate and drain of the eleventh transistor M11. The source of the transistor M9 and the source of the tenth transistor M10 are both connected to the second working voltage, the gate of the tenth transistor M10 is connected to the gate of the ninth transistor M9, the drain of the tenth transistor M10 is connected to the drain and gate of the twelfth transistor M12, the sources of the twelfth transistor M12 and the thirteenth transistor M13 are both connected to the first working voltage, the gate of the thirteenth transistor M13 is connected to the gate of the twelfth transistor M12, and the drain of the thirteenth transistor M13 is connected to the first bias voltage Vpin; The second compensation circuit at least includes: a twenty-first transistor M21, a twenty-second transistor M22, a twenty-third transistor M23, a twenty-fourth transistor M24, a twenty-fifth transistor M25 and a twenty-sixth transistor M26; wherein the gate of the twenty-first transistor M21 is connected to the input node, the source of the twenty-first transistor M21 is connected to the first working voltage, the drain of the twenty-first transistor M21 is connected to the drain of the twenty-second transistor M22 and the drain and gate of the twenty-third transistor M23, the source of the twenty-second transistor M22 is connected to the second working voltage, and the The source of the twenty-third transistor M23 and the source of the twenty-fourth transistor M24 are both connected to the first operating voltage, the gate of the twenty-fourth transistor M24 is connected to the gate of the twenty-third transistor M23, the drain of the twenty-fourth transistor M24 is connected to the drain and gate of the twenty-fifth transistor M25, the source of the twenty-fifth transistor M25 and the source of the twenty-sixth transistor M26 are both connected to the second operating voltage, the gate of the twenty-sixth transistor M26 is connected to the gate of the twenty-fifth transistor M25, and the drain of the twenty-sixth transistor M26 is connected to the second bias voltage Vnin.

8. The source follower circuit according to claim 7, characterized in that: The sources of the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the twenty-second transistor M22, the twenty-fifth transistor M25 and the twenty-sixth transistor M26 are all N-type transistors; The eleventh transistor M11 , the twelfth transistor M12 , the thirteenth transistor M13 , the twenty-first transistor M21 , the twenty-third transistor M23 , and the twenty-fourth transistor M24 are all P-type transistors.

9. The source follower circuit according to any one of claims 5 to 8, characterized in that: Also includes: A common-mode feedback unit, wherein the common-mode feedback unit is used to provide the first bias voltage Vpin and the second bias voltage Vnin to the first inverted source follower and the second inverted source follower.

10. An instrumentation amplifier, characterized in that: At least: A signal amplifier circuit, a source follower circuit as claimed in any one of claims 1 to 9, and a filter circuit are connected in sequence.

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