Switched capacitor circuit, signal receiving chip and Ethernet transceiver

Abstract

The invention discloses a switched capacitor circuit, a signal receiving chip and an Ethernet transceiver. The switched capacitor circuit comprises a first group of capacitors, a second group of capacitors, a third group of capacitors, a fully differential operational amplifier and a switch assembly. According to the technical scheme, on one hand, the switched capacitor circuit is controlled under the external clock signal to achieve the alternating process of the sampling phase state and the amplification phase state, a negative feedback loop is formed in the amplification phase state, and the frequency response and amplitude balance of the signal are ensured through the negative feedback loop. And on the other hand, compared with a traditional linear equalizer, the transfer function of the switched capacitor circuit in the technical scheme is only related to the capacitance ratio theoretically and is not easily influenced by process deviation, power supply voltage or temperature change, so that stable equalization frequency range and equalization strength are achieved, the stability of equalization capability is ensured, and the service life of the equalizer is prolonged. And the method is applied to an Ethernet receiving channel to omit CTLE, so that the structural design can be simplified.

Description

Technical Field

[0001] The present invention relates to the technical field of signal processing, and in particular to a switched capacitor circuit, a signal receiving chip and an Ethernet transceiver. Background Art

[0002] Ethernet transceivers are widely used in modern high-speed data communications, which mainly use twisted pair cables as the transmission medium. However, due to the skin effect of twisted pair cables, the signal will suffer frequency-related losses during transmission. This channel loss characteristic causes the attenuation of high-frequency components to be significantly higher than that of low-frequency components, which aggravates signal distortion and further causes inter-symbol-interference (ISI). The ISI problem not only affects the integrity of the signal, but also poses challenges to the clock and data recovery (CDR) and data correctness at the receiving end, thereby significantly increasing the bit error rate (BER), reducing the reliability of the receiver, and correspondingly limiting the data transmission frequency and transmission distance of the Ethernet transceiver.

[0003] Traditional receiving signal processing methods usually include multiple steps: echo cancellation, automatic gain control (AGC) and continuous time linear equalizer (CTLE) of the input signal. The signal after linear equalization is then quantized by an analog-to-digital converter (ADC). However, the performance of the linear equalizer is greatly affected by process deviations, voltage fluctuations and temperature changes (PVT for short), and it is difficult to maintain consistent equalization capabilities under different PVT conditions. This consistency problem has an adverse effect on the signal quality in high-speed signal transmission, further exacerbating the complexity of signal processing.

[0004] Therefore, the signal transmission process in the related art has technical problems such as inter-symbol interference caused by channel attenuation and insufficient stability of linear equalization due to the influence of chip process angle deviation, voltage and temperature. Summary of the invention

[0005] The main purpose of the present invention is to propose a switched capacitor circuit, a signal receiving chip and an Ethernet transceiver, aiming to at least solve the technical problem of insufficient stability of balancing capability caused by chip process angle deviation, voltage and temperature in the related art.

[0006] To achieve the above object, the technical solution of the present invention is as follows:

[0007] According to a first aspect of the present invention, there is provided a switched capacitor circuit, comprising a first group of capacitors, a second group of capacitors, a third group of capacitors, a fully differential operational amplifier and a switch component; the first end of the first group of capacitors is used to be electrically connected to a differential input port, the second end of the first group of capacitors is electrically connected to the first end of the second group of capacitors, the first end of the third group of capacitors and the input end of the fully differential operational amplifier respectively, and the output end of the fully differential operational amplifier is electrically connected to the second end of the second group of capacitors and the second end of the third group of capacitors at the same time; wherein the differential input port is used to input a differential input signal;

[0008] When the switch capacitor circuit is in a sampling phase state, the switch component is used to control the differential input signal output by the differential input port to be transmitted to the first group of capacitors, and the first group of capacitors is used to store the differential input signal;

[0009] When the switched capacitor circuit is in the amplification phase state, the switch component is used to control the second group of capacitors, the third group of capacitors and the fully differential operational amplifier to form a negative feedback loop, and transmit the differential input signal to the fully differential operational amplifier. The fully differential operational amplifier is used to amplify the differential input signal and output the obtained differential amplified signal.

[0010] A second aspect of the present invention provides a signal receiving chip, the signal receiving chip comprising a chip body and the switch capacitor circuit as described in the first aspect.

[0011] According to a third aspect of the present invention, an Ethernet transceiver is provided. The Ethernet transceiver comprises a transceiver body and the signal receiving chip as described in the first aspect.

[0012] The switch capacitor circuit, signal receiving chip and Ethernet transceiver of the present invention, on the one hand, through the first group of capacitors, the second group of capacitors, the third group of capacitors, the fully differential operational amplifier and the switch component, under the control of the external clock signal, the switch capacitor circuit realizes the alternating process of the sampling phase state and the amplification phase state, and forms a negative feedback loop when in the amplification phase state, and ensures the frequency response and amplitude balance of the signal through the negative feedback loop. On the other hand, compared with the traditional linear equalizer, the transfer function of the switch capacitor circuit of the present technical solution is theoretically only related to the capacitance ratio, and is not easily affected by process deviations, power supply voltage or temperature changes, ensuring a stable equalization effect, and can also improve the receiver architecture and save the CTLE circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0014] Figure 1 It is a structural diagram of a receiving architecture in the related art;

[0015] Figure 2 A schematic diagram of a receiving architecture formed by a switched capacitor circuit provided in an embodiment of the present application;

[0016] Figure 3 A circuit connection diagram of a switched capacitor circuit provided in an embodiment of the present application;

[0017] Figure 4 A schematic diagram of various switch states when the switched capacitor circuit provided in an embodiment of the present application is in a sampling phase state;

[0018] Figure 5 A schematic diagram of each switch state when the switched capacitor circuit provided by the embodiment of the present application is in an amplifying phase state;

[0019] Figure 6 A circuit connection diagram of a fully differential operational amplifier in a switched capacitor circuit provided in an embodiment of the present application;

[0020] Figure 7 A schematic diagram of an equivalent circuit of a switched capacitor circuit provided in an embodiment of the present application when in a sampling phase state;

[0021] Figure 8 A schematic diagram of an equivalent circuit of a switched capacitor circuit provided in an embodiment of the present application when in an amplifying phase state;

[0022] Fig. 9 This is an amplitude-frequency scanning curve of the switched capacitor circuit provided in an embodiment of the present application when the sampling frequency is 125 MHZ.

[0023] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0024] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0025] It should be noted that related terms such as "first", "second", etc. can be used to describe various components, but these terms do not limit the components. These terms are only used to distinguish one component from another component. For example, without departing from the scope of the present invention, a first component can be referred to as a second component, and the second component can also be referred to as a first component similarly. The term "and / or" refers to any one or more combinations of related items and description items.

[0026] In the related art, Ethernet transceivers use twisted pair cables as transmission media. Due to the skin effect, there is a frequency-related loss when the signal is transmitted in the twisted pair cables. Therefore, the twisted pair cables are a typical channel with frequency selective characteristics. This channel loss causes the attenuation of the high-frequency components of the signal to be greater than the attenuation of the low-frequency components, resulting in serious inter-symbol interference (ISI) of the signal received by the receiver, making it difficult to recover the clock data (CDR) and causing a high bit error rate, making it very difficult for the receiver to correctly receive the signal, thereby greatly limiting the data transmission frequency and transmission distance.

[0027] Signal equalization technology is usually used to solve the above problems. Figure 1 , which shows the related received signal processing method, first of all, the signal ( Figure 1 VIN in the Figure 1 ECC in ), automatic gain control ( Figure 1 AGC in ) and continuous-time linear equalization ( Figure 1 CTLE), and then feed the equalized signal to the analog-to-digital converter ( Figure 1 The main problem with linear equalization is that it is greatly affected by chip process angle deviation, voltage and temperature, and it is difficult to ensure the consistency of equalization capability under PVT.

[0028] See also Figure 1 and Figure 2 And for comparison, because the switched capacitor circuit with signal balancing capability proposed in the embodiment of the present application ( Figure 2 It is based on the principle of switched capacitors and can replace the sample-and-hold circuit ( Figure 1 The SH in the circuit is integrated into the analog-to-digital converter ADC. Based on its more stable equalization performance and the fact that the conventional linear equalizer can be omitted, the technical problems in the related art such as inter-symbol interference caused by channel attenuation in the signal transmission process and insufficient stability of the equalization capability caused by the influence of chip process angle deviation, voltage and temperature due to linear equalization can be solved.

[0029] See also Figure 3The switched capacitor circuit of the embodiment of the present application includes a first group of capacitors (C1a, C1b), a second group of capacitors (C2a, C2b), a third group of capacitors (C3a, C3b), a fully differential operational amplifier OP and a switch component.

[0030] The specific circuit connection relationship is: the first end of the first group of capacitors is used to be electrically connected to the differential input port, the second end of the first group of capacitors is electrically connected to the first end of the second group of capacitors, the first end of the third group of capacitors, and the input end of the fully differential operational amplifier OP respectively, and the output end of the fully differential operational amplifier OP is electrically connected to the second end of the second group of capacitors and the second end of the third group of capacitors at the same time.

[0031] Among them, the differential input port includes a positive electrode and a negative electrode, the positive electrode is used to input the positive input signal Vin+ of the differential input signal, and the negative electrode is used to input the reverse input signal Vin- of the differential input signal. The potential difference between the positive input signal Vin+ and the reverse input signal Vin- is the differential input signal, that is, the differential input port is used to input the differential input signal.

[0032] When the switched capacitor circuit is in a sampling phase state, the switch component receives a preset sampling phase control signal to control the differential input signal output by the differential input port to be transmitted to the first group of capacitors, and the first group of capacitors is used to store the differential input signal;

[0033] When the switch capacitor circuit is in the amplification phase state, the switch component controls the second group of capacitors, the third group of capacitors and the fully differential operational amplifier to form a negative feedback loop by receiving a preset amplification phase control signal, and transmits the differential input signal to the fully differential operational amplifier, which amplifies the differential input signal and outputs the obtained differential amplified signal. Among them, the negative feedback closed loop is centered on the fully differential operational amplifier OP, and the negative feedback closed loop is used to stabilize the output voltage, so that the output signals Von and Vop are balanced, ensuring the accuracy of the differential amplified signal. That is, the negative feedback loop can not only stabilize the DC reference of the output signal, but also balance the fluctuation of the op amp output, further improving the symmetry and anti-interference ability of the differential output signal.

[0034] Among them, the working process of the switched capacitor circuit includes two main working states: sampling phase state and amplification phase state. In each stage, different switch combinations are used to control the charging and discharging paths of each capacitor, thereby realizing signal sampling and amplification. Through the alternating operation of the above two working states, the circuit realizes the sampling and amplification of the input signal, and at the same time uses a negative feedback closed-loop system to maintain the DC stability of the system. This design ensures that the circuit can achieve stable signal amplification and output under different signal environments.

[0035] In the embodiment of the present application, the circuit adopts a fully differential structure, with input signals Vin+ and Vin- at the input end, and output signals Vop and Von at the output end. The advantage is that the common-mode signal (i.e., the same noise or interference that both input ends are subjected to) can be suppressed. In the fully differential structure, the inputs of signals Vin+ and Vin- will be amplified respectively, and two output signals Vop and Von with opposite phases will be generated. Therefore, any common-mode interference (such as noise, temperature drift, etc.) superimposed on the input end will offset each other during the differential operation process, thereby enhancing the anti-interference ability of the system, thereby providing balancing ability, even if the circuit can effectively suppress the common-mode interference of the input signal, thereby improving the accuracy and anti-interference performance of signal processing. In addition, compared with the traditional linear equalizer, the transfer function of the switch capacitor circuit of the present technical solution is theoretically only related to the capacitance ratio, and is not easily affected by process deviation, power supply voltage or temperature changes, ensuring a stable balancing effect, that is, improving the stability of the balancing ability.

[0036] It should be noted that for the Gigabit Ethernet chip, its receiving channel ADC realizes the quantization of the continuous analog signal. The switched capacitor circuit with signal equalization capability proposed in the embodiment of the present application is essentially a discretization process under the action of the sampling clock, so the switched capacitor circuit of the embodiment of the present application can be compatible with the analog-to-digital converter and replace the original SH circuit (in the analog-to-digital converter). The advantage of this implementation is that the area and power consumption of the analog-to-digital converter of the new structure will not change significantly, and the invention solves the problem that CTLE varies greatly with PVT, and CTLE can be omitted in the new receiving architecture, simplifying the design of the receiving architecture.

[0037] It should be further explained that when the circuit is in the sampling phase, the circuit mainly completes the acquisition and charge storage of the input signal. The focus of this stage is to "capture" the instantaneous characteristics of the input signal to provide a basis for the subsequent processing of the amplification phase. By accurately controlling the closing and opening of the switch component, the charge of the signal can be collected at a specific moment, that is, the input signal of certain frequency components (target frequency) can be "selectively sampled" and stored based on the first group of capacitors. Since the capacitor can "remember" the amount of charge of the signal, even after the sampling phase ends, this information remains on the capacitor, waiting for the subsequent amplification phase processing. For example, by adjusting the clock frequency, the circuit can be more sensitive to high-frequency signal components and relatively insensitive to low-frequency components, thereby achieving selective response in frequency. And, when the circuit is in the amplification phase, the circuit uses the charge previously stored in the first group of capacitors to amplify the signal. In this state, the response of different frequency components is adjusted by adjusting the ratio of the first group of capacitors, the second group of capacitors, and the third group of capacitors. For example, the first group of capacitors with larger capacitance values ​​and the second and third groups of capacitors with smaller capacitance values ​​can increase the circuit's response to high-frequency components, while the first group of capacitors with smaller capacitance values ​​and the second and third groups of capacitors with larger capacitance values ​​can enhance the amplification effect of low-frequency components. Therefore, by setting the capacitance ratio, the circuit can selectively amplify signals in a specific frequency band, while appropriately attenuating signals in other frequency bands, thereby achieving a balanced signal effect.

[0038] In an optional implementation manner of the present embodiment, the switch component includes an input sampling switch device (S1a, S1b), a reference voltage switch device (S2a, S2b), a common mode voltage switch device (S3a, S3b), an amplifier input switching switch device (S4a, S4b, S4c, S4d), a holding capacitor charge and discharge switch device (S5a, S5b, S5c, S5d), an output common mode voltage switch device (S6a, S6b) and a sampling and holding switch device (S7a, S7b).

[0039] The electrical connection relationship of each switch device is as follows: the input sampling switch device is electrically connected between the differential input port and the first end of the first group of capacitors, the reference voltage switch device is electrically connected between the reference voltage input terminal and the first end of the first group of capacitors, the common mode voltage switch device is electrically connected between the common mode voltage input port and the second end of the third group of capacitors, the amplifier input end switching switch device is electrically connected between the first end of the second group of capacitors and the input end of the fully differential operational amplifier, the holding capacitor charge and discharge switch device is electrically connected between the first end of the second group of capacitors and the input end of the fully differential operational amplifier, the output common mode voltage switch device is electrically connected between the second end of the third group of capacitors and the output end of the fully differential operational amplifier, and the sampling and holding switch device is electrically connected between the second end of the first group of capacitors and the input end of the fully differential operational amplifier.

[0040] Specifically, each switch device plays the following role: input sampling switch device, sample and hold switch device, and common mode voltage switch device are used for sampling phase state to realize sampling of input signal, and loading of reference voltage and common mode voltage. Reference voltage switch device, amplifier input switching switch device, holding capacitor charge and discharge switch device, and output common mode voltage switch device are used for amplification phase state to realize differential signal amplification, feedback control, and loading of output common mode voltage. That is, through the coordinated work of the above switch devices, the circuit can realize stable signal processing, suppress common mode interference, and ensure the accuracy and balance of the output signal in the sampling phase and amplification phase states.

[0041] In an optional implementation manner of this embodiment, the first group of capacitors includes a first capacitor C1a and a second capacitor C1b with equal capacitance values, the input sampling switch device includes a first input sampling switch S1a and a second input sampling switch S1b, the reference voltage switch device includes a first reference voltage switch S2a and a second reference voltage switch S2b, and the sampling and holding switch device includes a first sampling and holding switch S7a and a second sampling and holding switch S7b.

[0042] Specifically, the corresponding circuit connection relationship is as follows: the first end of the first capacitor C1a is electrically connected to the first end of the first input sampling switch S1a and the first end of the first reference voltage switch S2a respectively, the second end of the first input sampling switch S1a is used to be electrically connected to the positive electrode of the differential input port, the second end of the first capacitor C1a is simultaneously electrically connected to the first end of the first sampling and holding switch S7a, the first end of the holding capacitor charge and discharge switch device S5, the first end of the amplifier input end switching switch device S4, the first end of the third group of capacitors, and the input end of the fully differential operational amplifier OP, the first end of the second capacitor C1b is electrically connected to the second input sampling ... first capacitor C1b is electrically connected to the second input sampling switch S7a, the first end of the first sampling and holding switch S7a, the first end of the first sampling and holding switch S7a, the first end of the first sampling and holding switch S7a, the first end of the first sampling and holding switch S7a, the first end of the first sampling and holding switch S7a, the first end of the first sampling and holding switch S7a, the first end of the first sampling and holding switch S7a, The first end of the sampling switch S1b is electrically connected to the first end of the second reference voltage switch S2b, the second end of the second input sampling switch S1b is used to be electrically connected to the negative electrode of the differential input port, the second end of the first reference voltage switch S2a is electrically connected to the common mode voltage input port and the second end of the second reference voltage switch S2b at the same time, the second end of the second capacitor C1b is electrically connected to the first end of the second sampling and holding switch S7b, the input end of the fully differential operational amplifier OP, and the first end of the third group of capacitors, respectively, and the second end of the first sampling and holding switch S7a is electrically connected to the reference voltage input port and the second end of the second sampling and holding switch S7b at the same time. The reference voltage input port is used to input the reference voltage Vb.

[0043] Specifically, in this circuit, since the capacitance values ​​of the first capacitor C1a and the second capacitor C1b are equal, in the differential input signal sampling stage (the circuit is in the sampling phase state), these two capacitors can symmetrically store the forward input signal (Vin+) and the reverse input signal (Vin-). This ensures that the sampled differential signal has symmetry, that is, the circuit's response to the differential input signal is completely symmetrical, which helps to suppress common-mode noise and avoid errors introduced due to capacitor imbalance. In addition, in this circuit, the role of the input reference voltage Vb is to provide a stable level reference for sampling and amplification of the differential signal, ensuring the reliability and stability of the input signal and the output signal.

[0044] In an optional implementation manner of the present embodiment, the second group of capacitors includes a third capacitor C2a and a fourth capacitor C2b with equal capacitance values, the amplifier input end switching switch device S4 includes a first amplifier input end switching switch S4a, a second amplifier input end switching switch S4b, a third amplifier input end switching switch S4c and a fourth amplifier input end switching switch S4d, the holding capacitor charge and discharge switch device S5 includes a first holding capacitor charge and discharge switch S5a, a second holding capacitor charge and discharge switch S5b, a third holding capacitor charge and discharge switch S5c and a fourth holding capacitor charge and discharge switch S5d, the first end of the third capacitor C2a is respectively electrically connected to the first end of the first amplifier input end switching switch S4a and the first end of the first holding capacitor charge and discharge switch S5a, the second end of the first holding capacitor charge and discharge switch S5a is respectively electrically connected to the negative input end of the fully differential operational amplifier, the first end of the second amplifier input end switching switch S4b, the second end of the second capacitor C1b, the first end of the second sampling and holding switch S7b, and the first end of the third group of capacitors, the second end of the first amplifier input end switching switch S4a is respectively electrically connected to the first capacitor C1a The second end of the first sampling and holding switch S7a, the first end of the second holding capacitor charge and discharge switch S5b, the first end of the third group of capacitors, and the positive input end of the fully differential operational amplifier OP are electrically connected; the first end of the fourth capacitor C2b is respectively electrically connected to the second end of the second holding capacitor charge and discharge switch S5b, the second end of the second amplifier input end switching switch S4b, the first end of the fourth holding capacitor charge and discharge switch S5d, and the first end of the fourth amplifier input end switching switch S4d; the second end of the fourth holding capacitor charge and discharge switch S5d is respectively electrically connected to the negative output end of the fully differential operational amplifier OP and the first end of the third amplifier input end switching switch S4c; the second end of the fourth amplifier input end switching switch S4d is respectively electrically connected to the positive output end of the fully differential operational amplifier and the first end of the third holding capacitor charge and discharge switch S5c; the second end of the third capacitor C2a is respectively electrically connected to the second end of the third holding capacitor charge and discharge switch S5c and the first end of the third amplifier input end switching switch S4c; the second end of the third amplifier input end switching switch S4c is respectively electrically connected to the negative output end of the fully differential operational amplifier.

[0045] Specifically, in this circuit, first, the capacitance values ​​of the third capacitor C2a and the fourth capacitor C2b in the second group of capacitors are equal, ensuring the symmetrical storage and transmission of the signal at the differential input. This configuration enables the circuit to have good symmetry for the differential signal, can suppress the asymmetric error in signal processing, and ensure the gain accuracy of the amplifier. Secondly, by maintaining the capacitor charge and discharge switch device S5 and the amplifier input switching switch device S4, the circuit can be efficiently switched between the sampling phase and the amplification phase. Again, through the negative feedback mechanism, the circuit can accurately control the amplitude and frequency response of the output signal to achieve stable amplification of the differential signal. In general, the design of this embodiment achieves a high-precision differential amplification effect by optimizing the capacitance value, switch configuration and negative feedback path, with excellent signal symmetry, noise immunity and stability.

[0046] In an optional implementation of the present embodiment, the third group of capacitors includes a fifth capacitor C3a and a sixth capacitor C3b with equal capacitance values, the common mode voltage switch device S3 includes a first common mode voltage switch S3a and a second common mode voltage switch S3b, and the output common mode voltage switch device S6 includes a first output common mode voltage switch S6a and a second output common mode voltage switch S6b.

[0047] The corresponding circuit connection relationship is as follows: the first end of the fifth capacitor C3a is respectively electrically connected to the second end of the first amplifier input terminal switching switch S4a, and is respectively electrically connected to the second end of the first capacitor C1a, the first end of the first sampling and holding switch S7a, the first end of the second holding capacitor charging and discharging switch S5b, the positive input terminal of the fully differential operational amplifier OP, and the first end of the sixth capacitor C3b; the second end of the fifth capacitor C3a is respectively electrically connected to the first end of the first common mode voltage switch C3a and the first end of the first output common mode voltage switch S6a; the second end of the first common mode voltage switch C3a is used to be electrically connected to the common mode voltage input port; the second end of the first output common mode voltage switch S6a is respectively electrically connected to the second end of the third amplifier input terminal switching switch S4c, the negative output terminal of the fully differential operational amplifier, and the fourth holding capacitor charging and discharging switch The second end of S5d is electrically connected, the first end of the sixth capacitor C3b is electrically connected to the second end of the first holding capacitor charge and discharge switch S5a, the negative input end of the fully differential operational amplifier OP, the first end of the second amplifier input end switching switch S4b, the second end of the second capacitor C1b, and the first end of the second sampling and holding switch S7b, the second end of the sixth capacitor C3b is electrically connected to the first end of the second output common mode voltage switch S6b and the first end of the second common mode voltage switch S3b, the second end of the second common mode voltage switch S3b is used to be electrically connected to the common mode voltage input port, and the second end of the second output common mode voltage switch S6b is electrically connected to the second end of the fourth amplifier input end switching switch S4d, the positive output end of the fully differential operational amplifier OP, and the first end of the third holding capacitor charge and discharge switch S5c. Among them, the common mode voltage input port is used to input the common mode voltage Vm.

[0048] Specifically, in this circuit, through the fifth capacitor C3a and the sixth capacitor C3b with equal capacitance values ​​in the third group of capacitors and their symmetrical design, a consistent common mode voltage can be maintained at the input and output ends. This configuration effectively suppresses common mode noise, improves the anti-interference ability of the circuit, and makes the circuit process positive and negative differential signals more balanced, thereby ensuring the symmetry and amplification accuracy of the differential signal. In addition, by inputting the common mode voltage Vm, a stable common mode level is provided for the input and output ends, thereby suppressing common mode noise and improving the symmetry and stability of the signal during signal processing.

[0049] See also Figure 4 , Figure 4 The diagram shows the closed or open state of each switch when the switched capacitor circuit is in the sampling phase.

[0050] When the switched capacitor circuit is in the sampling phase state, the first input sampling switch S1a, the second input sampling switch S1b, the first common mode voltage switch S3a, the second common mode voltage switch S3b, the first sampling and holding switch S7a and the second sampling and holding switch S7b are simultaneously in a closed state based on the closing control signal, the first reference voltage switch S2a, the second reference voltage switch S2b, the first amplifier input terminal switching switch S4a, the second amplifier input terminal switching switch S4b, the third amplifier input terminal switching switch S4c, the fourth amplifier input terminal switching switch S4d, the first holding capacitor charging and discharging switch S5a, the second holding capacitor charging and discharging switch S5b, the third holding capacitor charging and discharging switch S5c, the fourth holding capacitor charging and discharging switch S5d, the first output common mode voltage switch S6a and the second output common mode voltage switch S6b are simultaneously in a disconnected state based on the disconnection control signal, and the differential input signal output by the differential input port is controlled to be transmitted to the first group of capacitors so that it stores the differential input signal.

[0051] Specifically, when it is necessary to control the switch capacitor circuit to be in a sampling phase state, a sampling phase control signal is transmitted to the switch through an external clock circuit, that is, some switches will simultaneously receive a closing control signal to execute a closing state, and some switches will simultaneously receive an opening control signal to execute an opening state, so that the differential input signal output by the differential input port is ultimately transmitted to the first group of capacitors, so that the first group of capacitors stores the differential input signal.

[0052] See also Figure 5 , Figure 5 It shows the closed or open state of each switch when the switched capacitor circuit is in the amplification phase.

[0053] When the switched capacitor circuit is in the amplifying phase state, the first reference voltage switch S2a, the second reference voltage switch S2b, the first holding capacitor charge and discharge switch S5a, the second holding capacitor charge and discharge switch S5b, the third holding capacitor charge and discharge switch S5c, the fourth holding capacitor charge and discharge switch S5d, the first output common mode voltage switch S6a, and the second output common mode voltage switch S6b are simultaneously in a closed state based on the closing control signal, and the first input sampling switch S1a, the second input sampling switch S1b, the first common mode voltage switch S3a, the second common mode voltage switch S3b, the first amplifier input terminal switching switch S4a, the second amplifier input terminal switching switch S4b, the third amplifier input terminal switching switch S4c, the fourth amplifier input terminal switching switch S4d, the first sampling and holding switch S7a and the second sampling and holding switch S7b are simultaneously in a disconnected state based on the disconnection control signal, and the differential input signal is controlled to be transmitted to the fully differential operational amplifier OP, and the fully differential operational amplifier OP is used to amplify the differential input signal and output the obtained differential amplified signal.

[0054] Specifically, when it is necessary to control the switched capacitor circuit to be in an amplifying phase state, a phase control signal is transmitted to the switch through an external clock circuit, that is, some switches will simultaneously receive a closing control signal to execute a closing state, and some switches will simultaneously receive a disconnecting control signal to execute a disconnecting state, so that the second group of capacitors, the third group of capacitors and the fully differential operational amplifier OP finally form a negative feedback loop, and the fully differential operational amplifier OP amplifies the differential input signal and outputs the obtained differential amplified signal, that is, Von and Vop begin to change until they are finally established to satisfy the law of conservation of charge.

[0055] See also Figure 6 , which shows a circuit connection relationship of a fully differential operational amplifier in an embodiment of the present application. The fully differential operational amplifier includes a differential amplifier stage circuit and a common source amplifier stage circuit; the input end of the differential amplifier stage circuit is electrically connected to the second end of the first group of capacitors, the first end of the second group of capacitors, and the first end of the third group of capacitors, respectively; the output end of the differential amplifier stage circuit is electrically connected to the input end of the common source amplifier stage circuit through the compensation capacitor Cc; and the output end of the common source amplifier stage circuit is electrically connected to the second end of the second group of capacitors and the second end of the third group of capacitors at the same time.

[0056] Specifically, the differential amplifier stage circuit adopts a sleeve-type common source and common gate (Cascode) structure, and the common source amplifier stage circuit uses a current source as a load to provide a fully differential output. The common mode feedback circuit (CMFB) is omitted in the fully differential operational amplifier, and the Miller compensation technology is adopted to improve the stability and bandwidth of the system. Among them, the differential amplifier stage circuit is mainly composed of transistors such as M1, M2, M3, and M4, and the input signal is differentially amplified through M1 and M2 respectively. M3 and M4 adopt a common source and common gate structure to increase the output impedance, thereby improving the gain. The common source amplifier stage is composed of M9 and M10, etc., and provides differential output voltages Vo+ and Vo- through the current source ISS2 as a load. At the same time, Miller compensation in the Current-Buffer mode is adopted. The compensation capacitor Cc is connected between the source (nodes A and B) of the common source and common gate structure of the first stage and the input end of the output stage. This compensation method effectively pushes the zero point of the system to a higher frequency position, increases the bandwidth of the circuit, and improves the phase margin of the system, which is beneficial to the stability of the circuit.

[0057] See also Figure 7 and Figure 8 , the equivalent circuit when the circuit is in the sampling phase state is as follows Figure 7 As shown, the equivalent circuit diagram when the circuit is in the amplification phase Figure 8 shown.

[0058] Specifically, the relationship between the differential amplified signal and the differential input signal is: Among them, V odn Represents the nth differential output signal, V idn Represents the differential input signal at the nth sampling time, V od(n-1) Represents the n-1th differential output signal, C A Represents the capacitance value of the first capacitor, C b Represents the capacitance value of the third capacitor, C c represents the capacitance value of the fifth capacitor.

[0059] If the capacitor C A =12Cu (Cu represents the unit capacitance of capacitor), C b =4Cu,C c =8Cu, substitute into the above formula to get:

[0060] From the above relationship between the differential amplified signal and the differential signal, it can be seen that the nth differential output signal is not only related to the sampling signal, but also to the size of the previous differential output.

[0061] When the sampling frequency Fs = 125MHz, the frequency response of the transfer function is as follows: Fig. 9 As shown, in essence, the input signal is balanced to a certain extent, and the highest gain point is at Fs / 2, that is, 62.5MHz. The equalization effect of high-frequency signals can be clearly seen from the curve. As long as the operational amplifier is properly designed, it can be seen that the coefficient of the above transfer function is only related to the capacitance ratio and has nothing to do with the absolute value, so a consistent signal equalization effect under PVT can be obtained. That is to say, it is proved that: compared with the traditional linear equalizer, the transfer function of the switching capacitor circuit of the present technical solution is theoretically only related to the capacitance ratio, and is not easily affected by process deviations, power supply voltage or temperature changes, ensuring a stable equalization effect, that is, improving the stability of the equalization capability.

[0062] The embodiment of the present application further provides a signal receiving chip, which includes a chip body and a switch capacitor circuit as described in the above embodiment.

[0063] The embodiment of the present application further provides an Ethernet transceiver, which includes a transceiver body and a signal receiving chip as described in the above embodiment.

[0064] Through the switch capacitor circuit, signal receiving chip and Ethernet transceiver provided by the embodiment of the present application, on the one hand, through the first group of capacitors, the second group of capacitors, the third group of capacitors, the fully differential operational amplifier and the switch component, the switch capacitor circuit is controlled under the external clock signal to realize the alternating process of the sampling phase state and the amplification phase state, and a negative feedback loop is formed when in the amplification phase state, that is, the frequency response and amplitude balance of the signal are ensured. On the other hand, compared with the traditional linear equalizer, the transfer function of the switch capacitor circuit of the present technical solution is theoretically only related to the capacitance ratio, and is not easily affected by process deviations, power supply voltage or temperature changes, ensuring a stable equalization effect, that is, improving the stability of the equalization capability, and can also improve the receiver architecture and eliminate the CTLE circuit.

[0065] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0066] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A switched capacitor circuit, characterized in that: The switch capacitor circuit includes a first group of capacitors, a second group of capacitors, a third group of capacitors, a fully differential operational amplifier and a switch component; The first end of the first group of capacitors is used to be electrically connected to the differential input port, the second end of the first group of capacitors is electrically connected to the first end of the second group of capacitors, the first end of the third group of capacitors, and the input end of the fully differential operational amplifier respectively, and the output end of the fully differential operational amplifier is electrically connected to the second end of the second group of capacitors and the second end of the third group of capacitors at the same time; wherein the differential input port is used to input a differential input signal; When the switch capacitor circuit is in a sampling phase state, the switch component is used to control the differential input signal output by the differential input port to be transmitted to the first group of capacitors, and the first group of capacitors is used to store the differential input signal; When the switched capacitor circuit is in the amplification phase state, the switch component is used to control the second group of capacitors, the third group of capacitors and the fully differential operational amplifier to form a negative feedback loop, and transmit the differential input signal to the fully differential operational amplifier. The fully differential operational amplifier is used to amplify the differential input signal and output the obtained differential amplified signal.

2. The switched capacitor circuit according to claim 1, wherein: The switch assembly includes an input sampling switch device, a reference voltage switch device, a common mode voltage switch device, an amplifier input terminal switching switch device, a holding capacitor charge and discharge switch device, an output common mode voltage switch device and a sampling and holding switch device; The input sampling switch device is electrically connected between the differential input port and the first end of the first group of capacitors, the reference voltage switch device is electrically connected between the reference voltage input terminal and the first end of the first group of capacitors, the common mode voltage switch device is electrically connected between the common mode voltage input port and the second end of the third group of capacitors, the amplifier input end switching switch device is electrically connected between the first end of the second group of capacitors and the input end of the fully differential operational amplifier, the holding capacitor charge and discharge switch device is electrically connected between the first end of the second group of capacitors and the input end of the fully differential operational amplifier, the output common mode voltage switch device is electrically connected between the second end of the third group of capacitors and the output end of the fully differential operational amplifier, and the sampling and holding switch device is electrically connected between the second end of the first group of capacitors and the input end of the fully differential operational amplifier.

3. The switched capacitor circuit according to claim 2, wherein: The first group of capacitors includes a first capacitor and a second capacitor with equal capacitance values, the input sampling switch device includes a first input sampling switch and a second input sampling switch, the reference voltage switch device includes a first reference voltage switch and a second reference voltage switch, and the sample-and-hold switch device includes a first sample-and-hold switch and a second sample-and-hold switch; The first end of the first capacitor is electrically connected to the first end of the first input sampling switch and the first end of the first reference voltage switch respectively, the second end of the first input sampling switch is used to be electrically connected to the positive electrode of the differential input port, the second end of the first capacitor is electrically connected to the first end of the first sampling and holding switch, the first end of the capacitor charging and discharging switch device, the first end of the amplifier input switching switch device, the first end of the third group of capacitors, and the input end of the fully differential operational amplifier at the same time, the first end of the second capacitor is electrically connected to the first end of the second input sampling switch and the first end of the second reference voltage switch respectively, the second end of the second input sampling switch is used to be electrically connected to the negative electrode of the differential input port, the second end of the first reference voltage switch is electrically connected to the common mode voltage input port and the second end of the second reference voltage switch at the same time, the second end of the second capacitor is electrically connected to the first end of the second sampling and holding switch, the input end of the fully differential operational amplifier, and the first end of the third group of capacitors respectively, and the second end of the first sampling and holding switch is electrically connected to the reference voltage input port and the second end of the second sampling and holding switch at the same time.

4. The switched capacitor circuit according to claim 3, wherein: The second group of capacitors includes a third capacitor and a fourth capacitor with equal capacitance values, the amplifier input end switching switch device includes a first amplifier input end switching switch, a second amplifier input end switching switch, a third amplifier input end switching switch and a fourth amplifier input end switching switch, and the holding capacitor charge and discharge switch device includes a first holding capacitor charge and discharge switch, a second holding capacitor charge and discharge switch, a third holding capacitor charge and discharge switch and a fourth holding capacitor charge and discharge switch; The first end of the third capacitor is electrically connected to the first end of the first amplifier input switching switch and the first end of the first holding capacitor charge and discharge switch, respectively; the second end of the first holding capacitor charge and discharge switch is electrically connected to the negative input end of the fully differential operational amplifier, the first end of the second amplifier input switching switch, the second end of the second capacitor, the first end of the second sampling and holding switch, and the first end of the third group of capacitors, respectively; the second end of the first amplifier input switching switch is electrically connected to the second end of the first capacitor, the first end of the first sampling and holding switch, the first end of the second holding capacitor charge and discharge switch, the first end of the third group of capacitors, and the positive input end of the fully differential operational amplifier, respectively. The first end of the fourth capacitor is electrically connected to the second end of the second holding capacitor charge and discharge switch, the second end of the second amplifier input switching switch, the first end of the fourth holding capacitor charge and discharge switch, and the first end of the fourth amplifier input switching switch, respectively; the second end of the fourth holding capacitor charge and discharge switch is electrically connected to the negative output end of the fully differential operational amplifier and the first end of the third amplifier input switching switch, respectively; the second end of the fourth amplifier input switching switch is electrically connected to the positive output end of the fully differential operational amplifier and the first end of the third holding capacitor charge and discharge switch, respectively; the second end of the third capacitor is electrically connected to the second end of the third holding capacitor charge and discharge switch and the first end of the third amplifier input switching switch, respectively; and the second end of the third amplifier input switching switch is electrically connected to the negative output end of the fully differential operational amplifier.

5. The switched capacitor circuit according to claim 4, wherein: The third group of capacitors includes a fifth capacitor and a sixth capacitor with equal capacitance values, the common mode voltage switch device includes a first common mode voltage switch and a second common mode voltage switch, and the output common mode voltage switch device includes a first output common mode voltage switch and a second output common mode voltage switch; The first end of the fifth capacitor is respectively electrically connected to the second end of the first amplifier input switching switch, the second end of the first capacitor, the first end of the first sampling and holding switch, the first end of the second holding capacitor charge and discharge switch, the positive input terminal of the fully differential operational amplifier, and the first end of the sixth capacitor. The second end of the fifth capacitor is respectively electrically connected to the first end of the first common mode voltage switch and the first end of the first output common mode voltage switch. The second end of the first common mode voltage switch is used to be electrically connected to the common mode voltage input port. The second end of the first output common mode voltage switch is respectively electrically connected to the second end of the third amplifier input switching switch, the negative output terminal of the fully differential operational amplifier, and the fourth holding capacitor charge and discharge switch. The second end is electrically connected to the first end of the sixth capacitor, the first end of the sixth capacitor is respectively electrically connected to the second end of the first holding capacitor charge and discharge switch, the negative input end of the fully differential operational amplifier, the first end of the second amplifier input end switching switch, the second end of the second capacitor, and the first end of the second sampling and holding switch, the second end of the sixth capacitor is respectively electrically connected to the first end of the second output common mode voltage switch and the first end of the second common mode voltage switch, the second end of the second common mode voltage switch is used to be electrically connected to the common mode voltage input port, and the second end of the second output common mode voltage switch is respectively electrically connected to the second end of the fourth amplifier input end switching switch, the positive output end of the fully differential operational amplifier, and the first end of the third holding capacitor charge and discharge switch.

6. The switched capacitor circuit according to claim 5, characterized in that: When the switch capacitor circuit is in a sampling phase state, the first input sampling switch, the second input sampling switch, the first common mode voltage switch, the second common mode voltage switch, the first sample and hold switch, and the second sample and hold switch are simultaneously in a closed state based on a closed control signal, and the first reference voltage switch, the second amplifier input end switching switch, the third amplifier input end switching switch, the fourth amplifier input end switching switch, the first holding capacitor charge and discharge switch, the second holding capacitor charge and discharge switch, the third holding capacitor charge and discharge switch, the fourth holding capacitor charge and discharge switch, the first output common mode voltage switch, and the second output common mode voltage switch are simultaneously in a disconnected state based on a disconnection control signal, and the differential input signal output by the differential input port is controlled to be transmitted to the first group of capacitors to store the differential input signal; When the switch capacitor circuit is in the amplification phase state, the first reference voltage switch, the second reference voltage switch, the first holding capacitor charge and discharge switch, the second holding capacitor charge and discharge switch, the third holding capacitor charge and discharge switch, the fourth holding capacitor charge and discharge switch, the first output common mode voltage switch and the second output common mode voltage switch are simultaneously in a closed state based on a closed control signal, and the first input sampling switch, the second input sampling switch, the first common mode voltage switch, the second common mode voltage switch, the first amplifier input terminal switching switch, the second amplifier input terminal switching switch, the third amplifier input terminal switching switch, the fourth amplifier input terminal switching switch, the first sampling and holding switch and the second sampling and holding switch are simultaneously in a disconnected state based on a disconnection control signal, controlling the differential input signal to be transmitted to the fully differential operational amplifier, and the fully differential operational amplifier is used to amplify the differential input signal and output the obtained differential amplified signal.

7. The switched capacitor circuit according to claim 1, wherein: The relationship between the differential amplified signal and the differential input signal is: Among them, V odn Represents the nth differential output signal, V idn Represents the differential input signal at the nth sampling time, V od(n-1) Represents the n-1th differential output signal, C A Represents the capacitance value of the first capacitor, C b Represents the capacitance value of the third capacitor, C c represents the capacitance value of the fifth capacitor.

8. The switched capacitor circuit according to claim 1, wherein: The fully differential operational amplifier comprises a differential amplifier stage circuit and a common source amplifier stage circuit; The input end of the differential amplifier stage circuit is electrically connected to the second end of the first group of capacitors, the first end of the second group of capacitors, and the first end of the third group of capacitors, respectively; the output end of the differential amplifier stage circuit is electrically connected to the input end of the common source amplifier stage circuit via a compensation capacitor; and the output end of the common source amplifier stage circuit is electrically connected to the second end of the second group of capacitors and the second end of the third group of capacitors at the same time.

9. A signal receiving chip, characterized in that: The signal receiving chip comprises a chip body and a switched capacitor circuit as claimed in any one of claims 1 to 8.

10. An Ethernet transceiver, characterized in that: The Ethernet transceiver comprises a transceiver body and the signal receiving chip as claimed in claim 9.

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