Positive voltage controlled monolithic phase shifter chip

Abstract

The invention relates to the technical field of microelectronics, semiconductors and communication, and discloses a positive voltage controlled monolithic phase shifter chip, which comprises a radio frequency input blocking capacitor C1, a radio frequency output blocking capacitor C2, a 5.625-degree phase shifting unit, a 11.25-degree phase shifting unit, a 22.5-degree phase shifting unit, a 45-degree phase shifting unit, a 90-degree phase shifting unit and a 180-degree phase shifting unit which are connected in sequence, and the single-chip phase shifter chip adopts positive voltage control. The single-chip phase shifter chip can be controlled by positive voltage, and the problem that a traditional single-chip phase shifter cannot be controlled by positive voltage is solved.

Description

Technical Field

[0001] The invention relates to the fields of microelectronics, semiconductors and communication technology, and in particular to a positive voltage controlled single-chip phase shifter chip. Background Art

[0002] GaAs pseudo-matched high electron mobility transistor (pHEMT) devices have the characteristics of high operating frequency, low noise, greater current handling capability and better temperature stability, and are widely used in the field of RF monolithic chips.

[0003] In the field of traditional GaAs monolithic phase shifters, because the pHEMT transistors used are depletion-type transistors (D tubes), they can only be turned on and off by 0V and negative voltages. In practical applications, negative voltages generally need to be converted through positive voltages, which brings a certain degree of inconvenience in practical applications. Summary of the invention

[0004] Based on this, it is necessary to address the technical problem that the conventional GaAs monolithic phase shifter in the prior art cannot be controlled by positive voltage, and propose a positive voltage controlled monolithic phase shifter chip, the positive voltage controlled monolithic phase shifter chip comprising: an RF input DC blocking capacitor C1, an RF output DC blocking capacitor C2, a 5.625° phase shift unit, an 11.25° phase shift unit, a 22.5° phase shift unit, a 45° phase shift unit, a 90° phase shift unit, and a 180° phase shift unit;

[0005] The RF input end is connected to the first end of the RF input DC blocking capacitor C1, the second end of the RF input DC blocking capacitor C1 is connected to the RF input end of the 90° phase shift unit, the RF output end of the 90° phase shift unit is connected to the RF input end of the 11.25° phase shift unit, the RF output end of the 11.25° phase shift unit is connected to the RF input end of the 45° phase shift unit, the RF output end of the 45° phase shift unit is connected to the RF input end of the 5.625° phase shift unit, the RF output end of the 5.625° phase shift unit is connected to the RF input end of the 22.5° phase shift unit, the RF output end of the 22.5° phase shift unit is connected to the RF input end of the 180° phase shift unit, the RF output end of the 180° phase shift unit is connected to the first end of the RF output DC blocking capacitor C2, and the second end of the RF output DC blocking capacitor C2 is connected to the RF output end, wherein the monolithic phase shifter chip adopts positive voltage control.

[0006] In one embodiment, the 45° phase shift unit, the 90° phase shift unit, and the 180° phase shift unit all adopt a positive voltage controlled high-low pass switch network phase shift structure, and the positive voltage controlled high-low pass switch network phase shift structure includes pHEMT transistors Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, gate resistors R1, R2, R3, R4, R5, R6, R7, R8, inductors L1, L2, L3, and capacitors C1, C2, C3, C4, C5, C6, C7;

[0007] The source of the pHEMT transistor Q1 serves as the RF input terminal of the positive voltage controlled high-low pass switch network phase shift structure, and the source of the pHEMT transistor Q4 serves as the RF output terminal of the positive voltage controlled high-low pass switch network phase shift structure; the gate of the pHEMT transistor Q1 is connected to the first end of the gate resistor R1, the second end of the gate resistor R1 is connected to the control terminal 1, and the drain of the pHEMT transistor Q1 is respectively connected to the source of the pHEMT transistor Q2 and the first end of the capacitor C2;

[0008] The gate of the pHEMT transistor Q2 is connected to the first end of the gate resistor R2, the second end of the gate resistor R2 is connected to the control terminal 2, the drain of the pHEMT transistor Q2 is connected to the first end of the capacitor C1, and the second end of the capacitor C1 is grounded;

[0009] The second end of the capacitor C2 is connected to the second end of the capacitor C3 and the first end of the inductor L1 respectively, the second end of the inductor L1 is grounded, and the first end of the capacitor C3 is connected to the source of the pHEMT transistor Q3 and to the drain of the pHEMT transistor Q4;

[0010] The gate of the pHEMT transistor Q3 is connected to the first end of the gate resistor R3, the second end of the gate resistor R3 is connected to the second end of the gate resistor R2, the drain of the pHEMT transistor Q3 is connected to the first end of the capacitor C4, and the second end of the capacitor C4 is grounded;

[0011] The gate of pHEMT transistor Q4 is connected to the first end of gate resistor R4, the second end of gate resistor R4 is connected to the second end of gate resistor R1, and the source of pHEMT transistor Q4 is connected to the source of pHEMT transistor Q5;

[0012] The gate of the pHEMT transistor Q5 is connected to the first end of the gate resistor R5, the second end of the gate resistor R5 is connected to the second end of the gate resistor R2, and the drain of the pHEMT transistor Q5 is connected to the first end of the inductor L2 and the source of the pHEMT transistor Q6 respectively;

[0013] The gate of the pHEMT transistor Q6 is connected to the first end of the gate resistor R6, the second end of the gate resistor R6 is connected to the second end of the gate resistor R1, the drain of the pHEMT transistor Q6 is connected to the first end of the capacitor C5; the second end of the capacitor C5 is grounded;

[0014] The second end of the inductor L2 is respectively connected to the second end of the inductor L3 and the first end of the capacitor C6, the second end of the capacitor C6 is grounded, and the first end of the inductor L3 is respectively connected to the source of the pHEMT transistor Q7 and the drain of the pHEMT transistor Q8;

[0015] The gate of the pHEMT transistor Q7 is connected to the first end of the gate resistor R7, the second end of the gate resistor R7 is connected to the second end of the gate resistor R1, the drain of the pHEMT transistor Q7 is connected to the first end of the capacitor C7, and the second end of the capacitor C7 is grounded;

[0016] The gate of pHEMT transistor Q8 is connected to the first end of gate resistor R8 , the second end of gate resistor R8 is connected to the second end of gate resistor R2 , and the source of pHEMT transistor Q8 is connected to the source of pHEMT transistor Q1 .

[0017] In one embodiment, the 11.25° phase shift unit and the 22.5° phase shift unit both adopt a positive voltage controlled simplified T-type phase shift structure, and the positive voltage controlled simplified T-type phase shift structure includes pHEMT transistors Q9, Q10, Q11, gate resistors R9, R10, R11, four inductors L4, L5, L6, L7 and a capacitor C8;

[0018] The source of the pHEMT transistor Q9 serves as the RF input terminal of the positive voltage controlled simplified T-type phase shift structure, and the drain of the pHEMT transistor Q9 serves as the RF output terminal of the positive voltage controlled simplified T-type phase shift structure;

[0019] The gate of the pHEMT transistor Q9 is connected to the first end of the gate resistor R9, the second end of the gate resistor R9 is connected to the control terminal 3, the source of the pHEMT transistor Q9 is connected to the first end of the inductor L4, the drain of the pHEMT transistor Q9 is connected to the first end of the inductor L5, and the second end of the inductor L4 and the second end of the inductor L5 are connected to the first end of the inductor L6 respectively;

[0020] The second end of the inductor L6 is connected to the source of the pHEMT transistor Q10, the gate of the pHEMT transistor Q10 is connected to the first end of the gate resistor R10, the second end of the gate resistor R10 is connected to the second end of the gate resistor R9, and the drain of the pHEMT transistor Q10 is respectively connected to the source of the pHEMT transistor Q11 and the first end of the inductor L7;

[0021] The gate of pHEMT transistor Q11 is connected to the first end of gate resistor R11, the second end of gate resistor R11 is connected to control terminal 4, the drain of pHEMT transistor Q11 is respectively connected to the second end of inductor L7 and the first end of capacitor C8, and the second end of capacitor C8 is grounded.

[0022] In one embodiment, the 5.625° phase shift unit adopts an all-pass phase shift structure, and the all-pass phase shift structure includes a pHEMT transistor Q12, a pHEMT transistor Q13, a gate resistor R12, a gate resistor R13, an inductor L8, an inductor L9, an inductor L10, and a capacitor C9;

[0023] The gate of the pHEMT transistor Q12 is connected to the first end of the gate resistor R12, the second end of the gate resistor R12 is connected to the control terminal 5, the source of the pHEMT transistor Q12 is connected to the first end of the inductor L8, and the second end of the inductor L8 is respectively connected to the drain of the pHEMT transistor Q12 and the source of the pHEMT transistor Q13;

[0024] The gate of the pHEMT transistor Q13 is connected to the first end of the gate resistor R13, the second end of the gate resistor R13 is connected to the control terminal 6, the source of the pHEMT transistor Q13 is connected to the first end of the inductor L9, the second end of the inductor L9 is connected to the first end of the capacitor C9, the second end of the capacitor C9 is connected to the first end of the inductor L10, and the second end of the inductor L10 is connected to the drain of the pHEMT transistor Q13;

[0025] The source of pHEMT transistor Q12 serves as the RF input terminal of the all-pass phase-shift structure, the drain of pHEMT transistor Q12 is connected to the source of pHEMT transistor Q13, and the drain of pHEMT transistor Q13 serves as the RF output terminal of the all-pass phase-shift structure.

[0026] The positive voltage controlled monolithic phase shifter chip proposed in the present invention comprises an RF input DC blocking capacitor C1, an RF output DC blocking capacitor C2, a 5.625° phase shift unit, an 11.25° phase shift unit, a 22.5° phase shift unit, a 45° phase shift unit, a 90° phase shift unit, and a 180° phase shift unit; the RF input end is connected to the first end of the RF input DC blocking capacitor C1, the second end of the RF input DC blocking capacitor C1 is connected to the RF input end of the 90° phase shift unit, the RF output end of the 90° phase shift unit is connected to the RF input end of the 11.25° phase shift unit, and the 11.25° phase shift unit is connected to the RF input end of the 180° phase shift unit. The RF output end of the unit is connected to the RF input end of the 45° phase shift unit, the RF output end of the 45° phase shift unit is connected to the RF input end of the 5.625° phase shift unit, the RF output end of the 5.625° phase shift unit is connected to the RF input end of the 22.5° phase shift unit, the RF output end of the 22.5° phase shift unit is connected to the RF input end of the 180° phase shift unit, the RF output end of the 180° phase shift unit is connected to the first end of the RF output DC isolation capacitor C2, the second end of the RF output DC isolation capacitor C2 is connected to the RF output end, wherein the monolithic phase shifter chip adopts positive voltage control. The monolithic phase shifter chip of the present invention can be controlled by positive voltage, which solves the problem that the traditional monolithic phase shifter cannot be controlled by positive voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0028] in:

[0029] Figure 1 Schematic diagram of the circuit structure of a positive voltage controlled monolithic phase shifter chip in one embodiment;

[0030] Figure 2 A positive voltage controlled high-low pass switch network phase shifting structure in a positive voltage controlled monolithic phase shifter chip in one embodiment;

[0031] Figure 3 A simplified T-type phase shift structure for positive pressure control in a single-chip phase shifter chip for positive pressure control in one embodiment;

[0032] Figure 4 The full-pass phase shift structure in a positive voltage controlled monolithic phase shifter chip in one embodiment. DETAILED DESCRIPTION

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by technicians in the technical field of the present application; the terms used in the specification of the application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application; the terms "including" and "having" and any variations thereof in the specification and claims of the present application and the above-mentioned drawings are intended to cover non-exclusive inclusions. The terms "first", "second", etc. in the specification and claims of the present application or the above-mentioned drawings are used to distinguish different objects, not to describe a specific order.

[0034] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0035] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0036] See also Figure 1 As shown, Figure 1 A circuit diagram of a positive voltage controlled monolithic phase shifter chip provided by an embodiment of the present invention, comprising: an RF input DC blocking capacitor C1, an RF output DC blocking capacitor C2, a 5.625° phase shift unit, a 11.25° phase shift unit, a 22.5° phase shift unit, a 45° phase shift unit, a 90° phase shift unit, and a 180° phase shift unit;

[0037] The RF input end is connected to the first end of the RF input DC blocking capacitor C1, the second end of the RF input DC blocking capacitor C1 is connected to the RF input end of the 90° phase shift unit, the RF output end of the 90° phase shift unit is connected to the RF input end of the 11.25° phase shift unit, the RF output end of the 11.25° phase shift unit is connected to the RF input end of the 45° phase shift unit, the RF output end of the 45° phase shift unit is connected to the RF input end of the 5.625° phase shift unit, the RF output end of the 5.625° phase shift unit is connected to the RF input end of the 22.5° phase shift unit, the RF output end of the 22.5° phase shift unit is connected to the RF input end of the 180° phase shift unit, the RF output end of the 180° phase shift unit is connected to the first end of the RF output DC blocking capacitor C2, and the second end of the RF output DC blocking capacitor C2 is connected to the RF output end, wherein the monolithic phase shifter chip adopts positive voltage control.

[0038] In one embodiment, please refer to Figure 2 As shown, Figure 2 It is a positive voltage controlled high-low pass switch network phase shift structure. The 45° phase shift unit, the 90° phase shift unit and the 180° phase shift unit all adopt a positive voltage controlled high-low pass switch network phase shift structure. The positive voltage controlled high-low pass switch network phase shift structure includes pHEMT transistors Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, gate resistors R1, R2, R3, R4, R5, R6, R7, R8, inductors L1, L2, L3, capacitors C1, C2, C3, C4, C5, C6, C7; the source of the pHEMT transistor Q1 is used as the RF input terminal of the positive voltage controlled high-low pass switch network phase shift structure, and the source of the pHEMT transistor Q4 is used as the RF output terminal of the positive voltage controlled high-low pass switch network phase shift structure; the gate of the pHEMT transistor Q1 is connected to the first end of the gate resistor R1, the second end of the gate resistor R1 is connected to the control terminal 1, and the drain of the pHEMT transistor Q1 is respectively connected to the source of the pHEMT transistor Q2 and the first end of the capacitor C2;

[0039] The gate of the pHEMT transistor Q2 is connected to the first end of the gate resistor R2, the second end of the gate resistor R2 is connected to the control terminal 2, the drain of the pHEMT transistor Q2 is connected to the first end of the capacitor C1, and the second end of the capacitor C1 is grounded; the second end of the capacitor C2 is respectively connected to the second end of the capacitor C3 and the first end of the inductor L1, the second end of the inductor L1 is grounded, the first end of the capacitor C3 is connected to the source of the pHEMT transistor Q3 and to the drain of the pHEMT transistor Q4; the gate of the pHEMT transistor Q3 is connected to the first end of the gate resistor R3, the second end of the gate resistor R3 is connected to the second end of the gate resistor R2, the drain of the pHEMT transistor Q3 is connected to the first end of the capacitor C4, and the second end of the capacitor C4 is grounded; the gate of the pHEMT transistor Q4 is connected to the first end of the gate resistor R4, the second end of the gate resistor R4 is connected to the second end of the gate resistor R1, and the source of the pHEMT transistor Q4 is connected to the source of the pHEMT transistor Q5; the gate of the pHEMT transistor Q5 is connected to the first end of the gate resistor R5, and the second end of the gate resistor R5 is connected to the second end of the gate resistor R2. The drain of the pHEMT transistor Q5 is respectively connected to the first end of the inductor L2 and the source of the pHEMT transistor Q6; the gate of the pHEMT transistor Q6 is connected to the first end of the gate resistor R6, the second end of the gate resistor R6 is connected to the second end of the gate resistor R1, and the drain of the pHEMT transistor Q6 is connected to the first end of the capacitor C5; the second end of the capacitor C5 is grounded; the second end of the inductor L2 is respectively connected to the second end of the inductor L3 and the first end of the capacitor C6, the second end of the capacitor C6 is grounded, and the first end of the inductor L3 is respectively connected to the source of the pHEMT transistor Q7 and the drain of the pHEMT transistor Q8; the gate of the pHEMT transistor Q7 is connected to the first end of the gate resistor R7, the second end of the gate resistor R7 is connected to the second end of the gate resistor R1, the drain of the pHEMT transistor Q7 is connected to the first end of the capacitor C7, and the second end of the capacitor C7 is grounded; the gate of the pHEMT transistor Q8 is connected to the first end of the gate resistor R8, the second end of the gate resistor R8 is connected to the second end of the gate resistor R2, and the source of the pHEMT transistor Q8 is connected to the source of the pHEMT transistor Q1.

[0040] In this embodiment, when the 45° or 90° or 180° positive voltage controlled high-low pass switch network phase shift structure control terminal 1 is given a positive voltage (such as 5V) and the control terminal 2 is given 0V, the 5V at the control terminal 1 will leak to the source and drain through the gates of the pHEMT transistor Q1, the pHEMT transistor Q4, the pHEMT transistor Q6, and the pHEMT transistor Q7. In this embodiment, the 6-bit positive voltage controlled monolithic phase shifter RF path has a DC blocking capacitor, and the phase shift unit has a DC blocking capacitor C1-C7 to the ground path, so that the voltage of the entire 45° or 90° or 180° full-pass phase shift structure RF path can be clamped to 4.6V (the 5V at the control terminal 1 passes through the source and drain of the pHEMT transistor Q1, the pHEMT transistor Q4, the pHEMT transistor Q6, and the pHEMT transistor Q7). voltage); at this time, the gate-drain voltage of pHEMT transistor Q1, pHEMT transistor Q4, pHEMT transistor Q6, and pHEMT transistor Q7 is 0.4V, which is in the on state, and the gate-drain voltage of pHEMT transistor Q2, pHEMT transistor Q3, pHEMT transistor Q5, and pHEMT transistor Q8 is -4.6V, which is in the off state. At this time, the phase-shift structure is in the reference state; when the control terminal 1 is given 0V and the control terminal 2 is given 5V, the mechanism is the same. At this time, pHEMT transistor Q1, pHEMT transistor Q4, pHEMT transistor Q6, and pHEMT transistor Q7 are in the off state, pHEMT transistor Q2, pHEMT transistor Q3, pHEMT transistor Q5, and pHEMT transistor Q8 are in the on state, and the phase-shift structure is in the phase-shift state.

[0041] In one embodiment, please refer to Figure 3 As shown, Figure 3It is a positive voltage controlled simplified T-type phase shift structure. The 11.25° phase shift unit and the 22.5° phase shift unit both adopt a positive voltage controlled simplified T-type phase shift structure. The positive voltage controlled simplified T-type phase shift structure includes pHEMT transistors Q9, Q10, Q11, gate resistors R9, gate resistors R10, gate resistors R11, four inductors L4, L5, L6, L7 and capacitor C8; the source of the pHEMT transistor Q9 serves as the RF input end of the positive voltage controlled simplified T-type phase shift structure, and the drain of the pHEMT transistor Q9 serves as the RF output end of the positive voltage controlled simplified T-type phase shift structure; the gate of the pHEMT transistor Q9 is connected to the first end of the gate resistor R9, the second end of the gate resistor R9 is connected to the control end 3, the source of the pHEMT transistor Q9 is connected to the first end of the inductor L4, and the pH The drain of the EMT transistor Q9 is connected to the first end of the inductor L5, and the second end of the inductor L4 and the second end of the inductor L5 are respectively connected to the first end of the inductor L6; the second end of the inductor L6 is connected to the source of the pHEMT transistor Q10, the gate of the pHEMT transistor Q10 is connected to the first end of the gate resistor R10, the second end of the gate resistor R10 is connected to the second end of the gate resistor R9, and the drain of the pHEMT transistor Q10 is respectively connected to the source of the pHEMT transistor Q11 and the first end of the inductor L7; the gate of the pHEMT transistor Q11 is connected to the first end of the gate resistor R11, the second end of the gate resistor R11 is connected to the control terminal 4, the drain of the pHEMT transistor Q11 is respectively connected to the second end of the inductor L7 and the first end of the capacitor C8, and the second end of the capacitor C8 is grounded.

[0042] In this embodiment, when the 11.25° or 22.5° positive voltage control simplified T-type phase shift structure control terminal 3 is given a positive voltage (such as 5V) and the control terminal 4 is given 0V, the 5V at the control terminal 1 will leak to the source and drain through the gates of the pHEMT transistor Q9 and the pHEMT transistor Q10. In this embodiment, the 6-bit positive voltage control monolithic phase shifter RF path has a DC blocking capacitor, and the phase shift unit has a DC blocking capacitor C8 to the ground path, so that the voltage of the entire 11.25° or 22.5° full-pass phase shift structure RF path can be clamped to 4.6V (the 5V at the control terminal 3 is leaked to the source and drain through the pHEMT transistor Q9 and the pHEMT transistor Q10). The source-drain voltage after the gate of the HEMT transistor Q9 and the pHEMT transistor Q10); at this time, the gate-drain voltage of the pHEMT transistor Q9 and the pHEMT transistor Q10 is 0.4V, which is in the on state, and the gate-drain voltage of the pHEMT transistor Q11 is -4.6V, which is in the off state. At this time, the phase-shift structure is in the reference state; when the control terminal 3 is given 0V and the control terminal 4 is given 5V, the mechanism is the same. At this time, the pHEMT transistor Q9 and the pHEMT transistor Q10 are in the off state, the pHEMT transistor Q11 is in the on state, and the phase-shift structure is in the phase-shift state.

[0043] In one embodiment, please refer to Figure 4 As shown, Figure 4 It is a full-pass phase-shift structure. The 5.625° phase-shift unit adopts a full-pass phase-shift structure. The full-pass phase-shift structure includes a pHEMT transistor Q12, a pHEMT transistor Q13, a gate resistor R12, a gate resistor R13, an inductor L8, an inductor L9, an inductor L10, and a capacitor C9; the gate of the pHEMT transistor Q12 is connected to the first end of the gate resistor R12, the second end of the gate resistor R12 is connected to the control terminal 5, the source of the pHEMT transistor Q12 is connected to the first end of the inductor L8, and the second end of the inductor L8 is respectively connected to the drain of the pHEMT transistor Q12 and the source of the pHEMT transistor Q13; the pHEMT transistor The gate of Q13 is connected to the first end of the gate resistor R13, the second end of the gate resistor R13 is connected to the control terminal 6, the source of the pHEMT transistor Q13 is connected to the first end of the inductor L9, the second end of the inductor L9 is connected to the first end of the capacitor C9, the second end of the capacitor C9 is connected to the first end of the inductor L10, and the second end of the inductor L10 is connected to the drain of the pHEMT transistor Q13; the source of the pHEMT transistor Q12 serves as the RF input end of the full-pass phase-shift structure, the drain of the pHEMT transistor Q12 is connected to the source of the pHEMT transistor Q13, and the drain of the pHEMT transistor Q13 serves as the RF output end of the full-pass phase-shift structure.

[0044] In this embodiment, when the control terminal 5 of the 5.625° full-pass phase shift structure is given a positive voltage (such as 5V) and the control terminal 6 is given 0V, the 5V at the control terminal 1 will leak to the source and drain through the gate of the pHEMT transistor Q12. In this embodiment, the 6-bit positive voltage control monolithic phase shifter RF path has a DC blocking capacitor, so that the voltage of the entire 5.625° full-pass phase shift structure RF path can be clamped to 4.6V (the source-drain voltage after the 5V at the control terminal 5 passes through the gate of the transistor Q12); at this time, the gate-drain voltage of the pHEMT transistor Q12 is 0.4V, which is in the on state, and the gate-drain voltage of the pHEMT transistor Q13 is -4.6V, which is in the off state. At this time, the phase shift structure is in the reference state; when the control terminal 5 is given 0V and the control terminal 6 is given 5V, the mechanism is the same. At this time, the pHEMT transistor Q12 is in the off state, the pHEMT transistor Q13 is in the on state, and the phase shift structure is in the phase shift state.

[0045] In one embodiment, further, the phase shift states of the above-mentioned six phase shift units can be combined, and there are 64 states from the reference state with a phase shift of 5.625° to 354.375°; in any state of the phase shifter, the RF path voltage from the second end of the RF input DC blocking capacitor to the first end of the RF output DC blocking capacitor will maintain the positive voltage from the gate of the transistor controlled by different positive voltages to the source and drain and clamped by the DC blocking capacitor, so that the pHEMT transistor can still obtain the correct gate-source turn-on voltage and the correct gate-source turn-off voltage when the positive voltage and 0V are controlled;

[0046] The present invention improves the traditional negative voltage monolithic phase shifter circuit, improves the structure of the specific phase shifter unit, and adds DC blocking capacitors at the RF input and RF output ends of the monolithic circuit. By clamping the voltage of the RF path of the phase shifter, the problem that the traditional monolithic phase shifter cannot be controlled by positive voltage is solved.

[0047] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A positive pressure controlled monolithic phase shifter chip, characterized in that: The positive voltage controlled monolithic phase shifter chip comprises: an RF input DC blocking capacitor C1, an RF output DC blocking capacitor C2, a 5.625° phase shift unit, an 11.25° phase shift unit, a 22.5° phase shift unit, a 45° phase shift unit, a 90° phase shift unit, and a 180° phase shift unit; The RF input end is connected to the first end of the RF input DC blocking capacitor C1, the second end of the RF input DC blocking capacitor C1 is connected to the RF input end of the 90° phase shift unit, the RF output end of the 90° phase shift unit is connected to the RF input end of the 11.25° phase shift unit, the RF output end of the 11.25° phase shift unit is connected to the RF input end of the 45° phase shift unit, the RF output end of the 45° phase shift unit is connected to the RF input end of the 5.625° phase shift unit, the RF output end of the 5.625° phase shift unit is connected to the RF input end of the 22.5° phase shift unit, the RF output end of the 22.5° phase shift unit is connected to the RF input end of the 180° phase shift unit, the RF output end of the 180° phase shift unit is connected to the first end of the RF output DC blocking capacitor C2, and the second end of the RF output DC blocking capacitor C2 is connected to the RF output end, wherein the monolithic phase shifter chip adopts positive voltage control.

2. The positive pressure controlled monolithic phase shifter chip according to claim 1, characterized in that: The 45° phase shift unit, the 90° phase shift unit and the 180° phase shift unit all adopt a positive voltage controlled high-low pass switch network phase shift structure, and the positive voltage controlled high-low pass switch network phase shift structure includes pHEMT transistors Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, gate resistors R1, R2, R3, R4, R5, R6, R7, R8, inductors L1, L2, L3, capacitors C1, C2, C3, C4, C5, C6, C7; The source of the pHEMT transistor Q1 serves as the RF input terminal of the positive voltage controlled high-low pass switch network phase shift structure, and the source of the pHEMT transistor Q4 serves as the RF output terminal of the positive voltage controlled high-low pass switch network phase shift structure; the gate of the pHEMT transistor Q1 is connected to the first end of the gate resistor R1, the second end of the gate resistor R1 is connected to the control terminal 1, and the drain of the pHEMT transistor Q1 is respectively connected to the source of the pHEMT transistor Q2 and the first end of the capacitor C2; The gate of the pHEMT transistor Q2 is connected to the first end of the gate resistor R2, the second end of the gate resistor R2 is connected to the control terminal 2, the drain of the pHEMT transistor Q2 is connected to the first end of the capacitor C1, and the second end of the capacitor C1 is grounded; The second end of the capacitor C2 is connected to the second end of the capacitor C3 and the first end of the inductor L1 respectively, the second end of the inductor L1 is grounded, and the first end of the capacitor C3 is connected to the source of the pHEMT transistor Q3 and to the drain of the pHEMT transistor Q4; The gate of the pHEMT transistor Q3 is connected to the first end of the gate resistor R3, the second end of the gate resistor R3 is connected to the second end of the gate resistor R2, the drain of the pHEMT transistor Q3 is connected to the first end of the capacitor C4, and the second end of the capacitor C4 is grounded; The gate of pHEMT transistor Q4 is connected to the first end of gate resistor R4, the second end of gate resistor R4 is connected to the second end of gate resistor R1, and the source of pHEMT transistor Q4 is connected to the source of pHEMT transistor Q5; The gate of the pHEMT transistor Q5 is connected to the first end of the gate resistor R5, the second end of the gate resistor R5 is connected to the second end of the gate resistor R2, and the drain of the pHEMT transistor Q5 is connected to the first end of the inductor L2 and the source of the pHEMT transistor Q6 respectively; The gate of the pHEMT transistor Q6 is connected to the first end of the gate resistor R6, the second end of the gate resistor R6 is connected to the second end of the gate resistor R1, the drain of the pHEMT transistor Q6 is connected to the first end of the capacitor C5; the second end of the capacitor C5 is grounded; The second end of the inductor L2 is respectively connected to the second end of the inductor L3 and the first end of the capacitor C6, the second end of the capacitor C6 is grounded, and the first end of the inductor L3 is respectively connected to the source of the pHEMT transistor Q7 and the drain of the pHEMT transistor Q8; The gate of the pHEMT transistor Q7 is connected to the first end of the gate resistor R7, the second end of the gate resistor R7 is connected to the second end of the gate resistor R1, the drain of the pHEMT transistor Q7 is connected to the first end of the capacitor C7, and the second end of the capacitor C7 is grounded; The gate of pHEMT transistor Q8 is connected to the first end of gate resistor R8 , the second end of gate resistor R8 is connected to the second end of gate resistor R2 , and the source of pHEMT transistor Q8 is connected to the source of pHEMT transistor Q1 .

3. The positive pressure controlled monolithic phase shifter chip according to claim 1, characterized in that: The 11.25° phase shift unit and the 22.5° phase shift unit both adopt a positive voltage controlled simplified T-type phase shift structure, which includes pHEMT transistors Q9, Q10, Q11, gate resistors R9, R10, R11, four inductors L4, L5, L6, L7 and a capacitor C8; The source of the pHEMT transistor Q9 serves as the RF input terminal of the positive voltage controlled simplified T-type phase shift structure, and the drain of the pHEMT transistor Q9 serves as the RF output terminal of the positive voltage controlled simplified T-type phase shift structure; The gate of the pHEMT transistor Q9 is connected to the first end of the gate resistor R9, the second end of the gate resistor R9 is connected to the control terminal 3, the source of the pHEMT transistor Q9 is connected to the first end of the inductor L4, the drain of the pHEMT transistor Q9 is connected to the first end of the inductor L5, and the second end of the inductor L4 and the second end of the inductor L5 are connected to the first end of the inductor L6 respectively; The second end of the inductor L6 is connected to the source of the pHEMT transistor Q10, the gate of the pHEMT transistor Q10 is connected to the first end of the gate resistor R10, the second end of the gate resistor R10 is connected to the second end of the gate resistor R9, and the drain of the pHEMT transistor Q10 is respectively connected to the source of the pHEMT transistor Q11 and the first end of the inductor L7; The gate of pHEMT transistor Q11 is connected to the first end of gate resistor R11, the second end of gate resistor R11 is connected to control terminal 4, the drain of pHEMT transistor Q11 is respectively connected to the second end of inductor L7 and the first end of capacitor C8, and the second end of capacitor C8 is grounded.

4. The positive pressure controlled monolithic phase shifter chip according to claim 3, characterized in that: The 5.625° phase shift unit adopts a full-pass phase shift structure, which includes a pHEMT transistor Q12, a pHEMT transistor Q13, a gate resistor R12, a gate resistor R13, an inductor L8, an inductor L9, an inductor L10, and a capacitor C9; The gate of the pHEMT transistor Q12 is connected to the first end of the gate resistor R12, the second end of the gate resistor R12 is connected to the control terminal 5, the source of the pHEMT transistor Q12 is connected to the first end of the inductor L8, and the second end of the inductor L8 is respectively connected to the drain of the pHEMT transistor Q12 and the source of the pHEMT transistor Q13; The gate of the pHEMT transistor Q13 is connected to the first end of the gate resistor R13, the second end of the gate resistor R13 is connected to the control terminal 6, the source of the pHEMT transistor Q13 is connected to the first end of the inductor L9, the second end of the inductor L9 is connected to the first end of the capacitor C9, the second end of the capacitor C9 is connected to the first end of the inductor L10, and the second end of the inductor L10 is connected to the drain of the pHEMT transistor Q13; The source of pHEMT transistor Q12 serves as the RF input terminal of the all-pass phase-shift structure, the drain of pHEMT transistor Q12 is connected to the source of pHEMT transistor Q13, and the drain of pHEMT transistor Q13 serves as the RF output terminal of the all-pass phase-shift structure.

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