A comparator with a preamplifier and its control method

Abstract

The present invention discloses a comparator with a preamplifier and its control method. First, the preamplifier is controlled to work, and the latch is in the reset state. After the preamplifier amplifies the signal at the output node to a preset gain, the preamplifier is kept working, and the latch is controlled to enter the working state. After the latch amplifies the input signal to the latch node, the preamplifier is controlled to be reset, and the latch enters the regeneration stage. After the latch generates a result, the clock control signal of the latch is turned off, and at this time, both the preamplifier and the latch are reset. The present invention adopts a four-stage circuit timing design, and controls the working states of the preamplifier and the latch through the clock control signal, realizing the functions of alternating amplification, regeneration, and reset, thereby improving the accuracy and speed of signal comparison and reducing power consumption.

Description

Technical Field

[0001] The present invention relates to the field of analog-to-digital conversion, and particularly to a comparator with a preamplifier and a control method thereof. Background Art

[0002] In the current field of analog-to-digital converter (ADC) technology, as a key component, the performance of the comparator has a decisive impact on the overall performance of the ADC. The comparators in existing ADCs face many problems that need to be solved urgently. On the one hand, in the high-precision working state, the comparator is extremely vulnerable to noise interference. On the other hand, in order to reduce noise, a preamplifier is usually adopted, which generally consists of two-stage circuits. The first stage is the preamplifier, which adopts a common-source (CS) or cascode structure to preliminarily amplify the input signal, or adopts a dynamic amplifier structure to periodically sample and amplify the input signal under the control of a clock to enhance the signal strength. The second stage is the core of the comparator, which often adopts a latch structure to quickly compare the amplified signal with the reference voltage and output a digital level. During the entire clock cycle, the preamplifier amplifies the input signal to increase the signal amplitude, and the amplified signal enters the latch, and the latch outputs the corresponding digital level to prepare for subsequent comparison. Under the existing technology, the high power consumption of the comparator is a major problem. In addition, during the reset process of the traditional comparator circuit, voltage residual errors will inevitably occur. This kind of error will accumulate in the subsequent signal processing, further reducing the signal accuracy and limiting its use in high-speed and high-precision applications. Summary of the Invention

[0003] Aiming at the deficiencies of the prior art, the present invention proposes a comparator with a preamplifier and a control method thereof. The specific technical solutions are as follows:

[0004] A control method for a comparator with a preamplifier, the comparator with a preamplifier includes a preamplifier and a latch, and the control method includes the following steps:

[0005] In the first stage, control the clock control signal of the preamplifier to make the preamplifier work, and the latch is in the reset state; after the preamplifier amplifies the signal at the output node to a preset gain, enter the second stage;

[0006] In the second stage: keep the preamplifier still working, control the clock control signal of the latch to make the latch enter the working state, and after the latch amplifies the input signal to the latch node, enter the third stage;

[0007] The third stage: The preamplifier is reset, and the latch enters the regeneration stage. At this time, the clock control signal of the preamplifier is turned off, and the preamplifier is reset. Wait for the latch to generate a result and enter the fourth stage;

[0008] The fourth stage: Turn off the clock control signal of the latch. At this time, both the preamplifier and the latch are reset.

[0009] Further, the preamplifier includes 12 MOS transistors MA01 - MA12 and 3 capacitors C1 - C3, where:

[0010] The drain of MA01 is connected to node VN, the source is connected to the drain of MA06, and the gate is connected to INN;

[0011] The drain of MA02 is connected to node VP, the source is connected to the drain of MA06, and the gate is connected to INP;

[0012] The drain of MA03 is connected to node VN, the source is connected to the drain of MA05, and the gate is connected to INN;

[0013] The source of MA04 is connected to the drain of MA05, the drain is connected to node VP, and the gate is connected to INP;

[0014] The source of MA05 is connected to one end of capacitor C1, the drain is connected to the sources of MA03 and MA04, and the gate is connected to the clock control signal CK1;

[0015] The source of MA06 is connected to the other end of capacitor C1, the drain is connected to the sources of MA01 and MA02, and the gate is connected to the inverted signal CK1B of the clock control signal CK1;

[0016] The source of MA07 is grounded, the drain is connected to one end of capacitor C1, and the gate is controlled by the inverted signal CK1B of the clock control signal CK1;

[0017] The source of MA08 is connected to the power supply, the drain is connected to the other end of capacitor C1, and the gate is controlled by the clock control signal CK1;

[0018] One end of capacitor C2 is connected to the power ground, and the other end is connected to node VN;

[0019] One end of capacitor C3 is connected to the power ground, and the other end is connected to node VP;

[0020] The source of MA09 is connected to VN, the drain is connected to VCM, and the gate is connected to the inverted signal CK1B of the clock control signal CK1;

[0021] The source of MA10 is connected to VP, the drain is connected to VCM, and the gate is connected to the inverted signal CK1B of the clock control signal CK1;

[0022] The source of MA11 is connected to VN, the source of MA12 is connected to VP, the drains of MA11 and MA12 are connected to each other, and the gates of MA11 and MA12 are controlled by the clock control signal CK1B.

[0023] Furthermore, the latch includes 11 MOS transistors M01 - M11, where:

[0024] The source of M01 is connected to the drain of M11, the drain is respectively connected to the source of M03 and the drain of M09, and the gate is connected to the node VN;

[0025] The source of M02 is connected to the drain of M11, the drain is connected to the source of M04, and the gate is connected to the node VP;

[0026] The source of M03 is connected to the drain of M01, the drain is connected to the source of M05, and the gate is connected to the output OUTP;

[0027] The source of M04 is connected to the drain of M02, the drain is connected to the drain of M06, and the gate is connected to the output OUTN;

[0028] The drain of M05 is connected to the drain of M03, the source is connected to the power supply, and the gate is connected to the output OUTP;

[0029] The drain of M06 is connected to the drain of M04, the source is connected to the power supply, and the gate is connected to the output OUTN;

[0030] The source of M07 is connected to the power supply, the drain is connected to the output OUTN, and the gate is connected to the clock control signal CK2;

[0031] The source of M08 is connected to the power supply, the drain is connected to the output signal OUTP, and the gate is connected to the clock control signal CK2;

[0032] The gate of M09 is connected to the clock control signal CK2, the drain is connected to the source of M03, and the source is connected to the power supply;

[0033] The gate of M10 is connected to the clock control signal CK2, the drain is connected to the source of M04, and the source is connected to the power supply;

[0034] The source of M11 is grounded, the drain is connected to the sources of M01 and M02, and the gate is connected to the clock control signal CK2.

[0035] Furthermore, the working states of the preamplifier and the latch are controlled by the clock control signal CK1, its inverted signal CK1B, and CK2. Specifically:

[0036] In the first stage, the clock control signal CK1 is at a high level, and the inverted signal CK1B of CK1 is at a low level, enabling the preamplifier to work while the latch is in a reset state. After the preamplifier amplifies the signal at the output node to a preset gain, it enters the second stage.

[0037] In the second stage, while keeping the clock control signal CK1 still at a high level and the inverted signal CK1B of CK1 at a low level, the clock control signal CK2 is at a high level, enabling the latch to enter the working state. After the latch amplifies the input signal to the latch node, it enters the third stage.

[0038] In the third stage, the clock control signal CK1 of the preamplifier is turned off, and the inverted signal CK1B of CK1 is pulled high. The clock control signal CK2 is still at a high level. The preamplifier is reset, and the latch enters the regeneration stage. After the latch generates a result, it enters the fourth stage.

[0039] In the fourth stage, the clock control signal CK2 of the latch is turned off, and at this time, both the preamplifier and the latch are reset.

[0040] Furthermore, the preamplifier includes five MOS transistors MA13 - MA17 and two capacitors C4 - C5, where:

[0041] The drain of MA14 is connected to node VN, the source is connected to the drain of MA13, and the gate is connected to INN.

[0042] The drain of MA15 is connected to node VP, the source is connected to the drain of MA13, and the gate is connected to INP.

[0043] The gate of MA13 is connected to the clock control signal CK1, and the source is connected to the ground.

[0044] The gate of MA16 is connected to the clock control signal CK1, the source is connected to the power supply voltage, and the drain is connected to node VN.

[0045] The gate of MA17 is connected to the clock control signal CK1, the source is connected to the power supply voltage, and the drain is connected to node VP.

[0046] One end of capacitor C4 is connected to the ground, and the other end is connected to node VN.

[0047] One end of capacitor C5 is connected to the ground, and the other end is connected to node VP.

[0048] Further, the latch includes six MOS transistors M12 - M18, where:

[0049] The gate of M17 is connected to node VN, the source is connected to the power ground, and the drain is connected to output node OUTN;

[0050] The gate of M18 is connected to node VP, the source is connected to the power ground, and the drain is connected to output node OUTP;

[0051] The gate of M12 is connected to node OUTP, the source is connected to the power ground, and the drain is connected to output node OUTN;

[0052] The gate of M13 is connected to node OUTN, the source is connected to the power ground, and the drain is connected to output node OUTP;

[0053] The gate of M14 is connected to output node OUTP, the drain is connected to output node OUTN, and the source is connected to the drain of M16;

[0054] The gate of M15 is connected to output node OUTN, the drain is connected to output node OUTP, and the source is connected to the drain of M16;

[0055] The gate of M16 is connected to the inverted signal CK2B of clock control signal CK2, the source is connected to the power voltage, and the drain is connected to the sources of M14 and M15.

[0056] Further, the working states of the pre - amplifier and the latch are controlled by clock control signals CK1 and CK2B, specifically:

[0057] First stage: Control the clock control signal CK1 of the pre - amplifier and the inverted signal CK2B of the clock control signal CK2 of the latch to be at a high level, so that the pre - amplifier works and the latch is in a reset state; after the pre - amplifier amplifies the signal of the output node to a preset gain, enter the second stage;

[0058] Second stage: Keep the clock control signal CK1 at a high level and CK2B at a low level. While keeping the pre - amplifier working, control the latch to work; after the latch amplifies the input signal to the latch node, enter the third stage;

[0059] Third stage: Turn off the clock control signal CK1 of the pre - amplifier, reset the pre - amplifier, and the latch enters the regeneration stage. After the latch generates a result, enter the fourth stage;

[0060] Fourth stage: Pull up the inverted signal CK2B of the clock control signal CK2, and reset both the preamplifier and the latch.

[0061] The beneficial effects of the present invention are as follows:

[0062] The comparator with a preamplifier and its control method of the present invention, the comparator includes a preamplification circuit and a latch circuit, adopts a four-stage circuit timing design, controls the working states of the preamplifier and the latch through a clock control signal, realizes the functions of alternating amplification, regeneration and reset, thereby improving the accuracy of signal comparison and reducing power consumption. Description of the Drawings

[0063] Figure 1 It is a circuit schematic diagram of the preamplifier in the comparator with a preamplifier according to one embodiment of the present invention.

[0064] Figure 2 It is a circuit schematic diagram of the latch of the comparator with a preamplifier according to one embodiment of the present invention.

[0065] Figure 3 It is a control timing diagram of the comparator with a preamplifier according to one embodiment of the present invention.

[0066] Figure 4 It is a circuit schematic diagram of the preamplifier in the comparator with a preamplifier according to another embodiment of the present invention.

[0067] Figure 5 It is a circuit schematic diagram of the latch in the comparator with a preamplifier according to another embodiment of the present invention.

[0068] Figure 6 It is a control timing diagram of the comparator with a preamplifier according to another embodiment of the present invention. Detailed Description of the Invention

[0069] The present invention will be described in detail below according to the drawings and preferred embodiments. The purpose and effects of the present invention will become more apparent. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0070] Explanation of Technical Terms:

[0071] MOS: Metal-Oxide-Semiconductor, metal-oxide-semiconductor field effect transistor;

[0072] VN: Negative voltage, negative voltage node;

[0073] VP: Positive voltage, positive voltage node;

[0074] INN: Negative input, negative input;

[0075] INP: Positive input, positive input;

[0076] VCM: Common mode voltage, common mode voltage;

[0077] OUTN: Negative output, negative output;

[0078] OUTP: Positive output, positive output;

[0079] CK: Clock signal, clock signal.

[0080] As Figure 1 shown, the comparator with a preamplifier in this embodiment includes a preamplifier and a latch. The preamplifier includes 12 MOS transistors MA01 - MA12 and 3 capacitors C1 - C3, and the latch includes 11 MOS transistors M01 - M11.

[0081] Among them, the drain of MOS transistor MA01 in the preamplifier is connected to node VN, the source is connected to the drain of MA06, and the gate is connected to INN; the drain of MA02 is connected to node VP, the source is connected to the drain of MA06, and the gate is connected to INP. The drain of MA03 is connected to node VN, the source is connected to the drain of MA05, and the gate is connected to INN; the source of MA04 is connected to the drain of MA05, the drain is connected to node VP, and the gate is connected to INP. The source of MA05 is connected to one end of capacitor C1, the drain is connected to the sources of MA03 and MA04, and the gate is connected to the clock control signal CK1. The source of MA06 is connected to the other end of capacitor C1, the drain is connected to the sources of MA01 and MA02, and the gate is connected to the inverted signal CK1B of the clock control signal CK1; the source of MA07 is grounded, the drain is connected to one end of capacitor C1, and the gate is controlled by the inverted signal CK1B of the clock control signal CK1. The source of MA08 is connected to the power supply, the drain is connected to the other end of capacitor C1, and the gate is controlled by the clock control signal CK1. One end of capacitor C2 is connected to the power ground, and the other end is connected to node VN. One end of capacitor C3 is connected to the power ground, and the other end is connected to node VP. The source of MA09 is connected to VN, the drain is connected to VCM, and the gate is connected to the inverted signal CK1B of the clock control signal CK1. The source of MA10 is connected to VP, the drain is connected to VCM, and the gate is connected to the inverted signal CK1B of the clock control signal CK1. The source of MA11 is connected to VN, the source of MA12 is connected to VP, the drains of MA11 and MA12 are connected to each other, and the gates of MA11 and MA12 are controlled by the clock control signal CK1B.

[0082] AsFigure 2 As shown, the source of M01 in the latch circuit is connected to the drain of M11, and the drains are respectively connected to the source of M03 and the drain of M09, and the gate is connected to node VN. The source of M02 is connected to the drain of M11, the drain is connected to the source of M04, and the gate is connected to node VP. The source of M03 is connected to the drain of M01, the drain is connected to the source of M05, and the gate is connected to output OUTP. The source of M04 is connected to the drain of M02, the drain is connected to the drain of M06, and the gate is connected to output OUTN. The drain of M05 is connected to the drain of M03, the source is connected to the power supply, and the gate is connected to output OUTP. The drain of M06 is connected to the drain of M04, the source is connected to the power supply, and the gate is connected to output OUTN. The source of M07 is connected to the power supply, the drain is connected to output signal OUTN, and the gate is connected to clock control signal CK2. The source of M08 is connected to the power supply, the drain is connected to output signal OUTP, and the gate is connected to clock control signal CK2. The gate of M09 is connected to clock control signal CK2, the drain is connected to the source of M03, and the source is connected to the power supply. The gate of M10 is connected to clock control signal CK2, the drain is connected to the source of M04, and the source is connected to the power supply. The source of M11 is grounded, the drain is connected to the sources of M01 and M02, and the gate is controlled by clock control signal CK2.

[0083] Compared with the circuit structure in which a traditional amplifier and a latch work and reset together, the control method of the comparator with a preamplifier of the present invention pipelines the working processes of the amplifier and the latch, and controls the working states of the preamplifier and the latch through clock control signal CK1 and its inverted signals CK1B and CK2, as Figure 3 shown:

[0084] In the first stage P1, the clock control signal CK1 is at a high level, and the inverted signal CK1B of CK1 is at a low level, causing the preamplifier to work and the latch to be in a reset state, saving power consumption; after the preamplifier amplifies the signal at the output node to a preset gain, it enters the second stage;

[0085] In the second stage P2, while keeping the clock control signal CK1 still at a high level and the inverted signal CK1B of CK1 at a low level, the clock control signal CK2 is at a high level, causing the latch to enter the working state. At this time, the amplifier is still working, and the amplified signal reduces the equivalent input noise of the latch; after the latch amplifies the input signal to the latch node again, it enters the third stage;

[0086] In the third stage P3, the clock control signal CK1 of the preamplifier is turned off, and the inverted signal CK1B of CK1 is pulled high. The clock control signal CK2 remains high, and the preamplifier is reset. Since there are multiple capacitor nodes in the preamplifier, early reset can reduce the residual voltage error. The latch enters the regeneration stage. When the latch generates a result, it enters the fourth stage;

[0087] In the fourth stage P4, the clock control signal CK2 of the latch is turned off. At this time, both the preamplifier and the latch are reset, completing the working cycle.

[0088] As Figure 4 and Figure 5 shown, another alternative architecture includes a preamplifier and a latch. The preamplifier includes five MOS transistors MA13 - MA17 and two capacitors C4 - C5, and the latch includes six MOS transistors M12 - M18.

[0089] Among them, as Figure 4 shown, the drain of the MOS transistor MA14 in the preamplifier is connected to the node VN, the source is connected to the drain of MA13, and the gate is connected to INN; the drain of MA15 is connected to the node VP, the source is connected to the drain of MA13, and the gate is connected to INP. The gate of MA13 is connected to the clock control signal CK1, and the source is connected to the ground. The gate of MA16 is connected to the clock control signal CK1, the source is connected to the power supply voltage, and the drain is connected to the node VN; the gate of MA17 is connected to the clock control signal CK1, the source is connected to the power supply voltage, and the drain is connected to the node VP. One end of the capacitor C4 is connected to the ground, and the other end is connected to the node VN; one end of the capacitor C5 is connected to the ground, and the other end is connected to the node VP.

[0090] As Figure 5 shown in the latch, the gate of M17 is connected to the node VN, the source is connected to the ground, and the drain is connected to the output node OUTN; the gate of M18 is connected to the node VP, the source is connected to the ground, and the drain is connected to the output node OUTP. The gate of M12 is connected to the node OUTP, the source is connected to the ground, and the drain is connected to the output node OUTN; the gate of M13 is connected to the node OUTN, the source is connected to the ground, and the drain is connected to the output node OUTP. The gate of M14 is connected to the output node OUTP, the drain is connected to the output node OUTN, and the source is connected to the drain of M16; the gate of M15 is connected to the output node OUTN, the drain is connected to the output node OUTP, and the source is connected to the drain of M16. The gate of M16 is connected to the inverted signal CK2B of the clock control signal CK2, the source is connected to the power supply voltage, and the drain is connected to the sources of M14 and M15.

[0091] Figure 4 and Figure 5In the circuit, the working states of the preamplifier and the latch are controlled by the clock control signals CK1 and CK2B, as Figure 6 shown, specifically as follows:

[0092] First stage: The clock control signal CK1 of the preamplifier and the inverted signal CK2B of the clock control signal CK2 of the latch are at high level, enabling the preamplifier to work and the latch to be in the reset state, saving power consumption; after the preamplifier amplifies the signal at the output node to the preset gain, it enters the second stage;

[0093] Second stage: Keep the clock control signal CK1 at high level and CK2B at low level. While keeping the preamplifier working, control the latch to work; the amplified signal reduces the equivalent input noise of the latch; after the latch amplifies the input signal to the latch node, it enters the third stage;

[0094] Third stage: Turn off the clock control signal CK1 of the preamplifier to reset the preamplifier. Since the preamplifier contains multiple capacitor nodes, early reset can reduce the voltage residual error; the latch enters the regeneration stage, and after the latch generates the result, it enters the fourth stage;

[0095] Fourth stage: Pull up the inverted signal CK2B of the clock control signal CK2 to reset both the preamplifier and the latch.

[0096] Those of ordinary skill in the art can understand that the above are only preferred examples of the invention and are not used to limit the invention. Although the invention has been described in detail with reference to the foregoing examples, for those skilled in the art, they can still modify the technical solutions described in the foregoing examples or perform equivalent replacements for some of the technical features. Any modifications, equivalent replacements, etc. made within the spirit and principle of the invention shall be included within the protection scope of the invention.

Claims

1. A control method for a comparator with a preamplifier, characterized in that: The comparator with a preamplifier comprises a preamplifier and a latch, and the control method comprises the following steps: In the first stage, the clock control signal of the preamplifier is controlled to make the preamplifier work, and the latch is in a reset state; after the preamplifier amplifies the signal of the output node to a preset gain, the second stage is entered; The second stage: keep the preamplifier still working, control the clock control signal of the latch, make the latch work, wait for the latch to amplify the input signal to the latch node, and then enter the third stage; The third stage: the preamplifier is reset, and the latch enters the regeneration stage. At this time, the clock control signal of the preamplifier is turned off, the preamplifier is reset, and the latch generates a result before entering the fourth stage. The fourth stage: the clock control signal of the latch is turned off, at which time the preamplifier and the latch are both reset.

2. The control method of the comparator with preamplifier according to claim 1, characterized in that: The preamplifier includes 12 MOS tubes MA01-MA12 and 3 capacitors C1-C3, wherein: The drain of MA01 is connected to the node VN, the source is connected to the drain of MA06, and the gate is connected to INN; The drain of the MA02 is connected to the node VP, the source is connected to the drain of MA06, and the gate is connected to INP; The drain of MA03 is connected to the node VN, the source is connected to the drain of MA05, and the gate is connected to INN; The source of MA04 is connected to the drain of MA05, the drain is connected to the node VP, and the gate is connected to INP; The source of MA05 is connected to one end of the capacitor C1, the drain is connected to the sources of MA03 and MA04, and the gate is connected to the clock control signal CK1; The source of MA06 is connected to the other end of the capacitor C1, the drain is connected to the sources of MA01 and MA02, and the gate is connected to the inverted signal CK1B of the clock control signal CK1; The source of MA07 is grounded, the drain is connected to one end of the capacitor C1, and the gate is controlled by the inverted signal CK1B of the clock control signal CK1; The source of MA08 is connected to the power supply, the drain is connected to the other end of the capacitor C1, and the gate is controlled by the clock control signal CK1; One end of the capacitor C2 is connected to the power ground, and the other end is connected to the node VN; One end of the capacitor C3 is connected to the power ground, and the other end is connected to the node VP; The source of MA09 is connected to VN, the drain is connected to VCM, and the gate is connected to the inverted signal CK1B of the clock control signal CK1; The source of MA10 is connected to VP, the drain is connected to VCM, and the gate is connected to the inverted signal CK1B of the clock control signal CK1; The source of MA11 is connected to VN, the source of MA12 is connected to VP, the drains of MA11 and MA12 are connected to each other, and the gates of MA11 and MA12 are controlled by a clock control signal CK1B.

3. The control method of the comparator with preamplifier according to claim 2, characterized in that: The latch includes 11 MOS transistors M01-M11, wherein: The source of M01 is connected to the drain of M11, the drain is connected to the source of M03 and the drain of M09 respectively, and the gate is connected to the node VN; The source of M02 is connected to the drain of M11, the drain is connected to the source of M04, and the gate is connected to the node VP; The source of M03 is connected to the drain of M01, the drain is connected to the source of M05, and the gate is connected to the output OUTP; The source of M04 is connected to the drain of M02, the drain is connected to the drain of M06, and the gate is connected to the output OUTN; The drain of M05 is connected to the drain of M03, the source is connected to the power supply, and the gate is connected to the output OUTP; The drain of M06 is connected to the drain of M04, the source is connected to the power supply, and the gate is connected to the output OUTN; The source of M07 is connected to the power supply, the drain is connected to the output OUTN, and the gate is connected to the clock control signal CK2; The source of M08 is connected to the power supply, the drain is connected to the output signal OUTP, and the gate is connected to the clock control signal CK2; The gate of M09 is connected to the clock control signal CK2, the drain is connected to the source of M03, and the source is connected to the power supply; The gate of M10 is connected to the clock control signal CK2, the drain is connected to the source of M04, and the source is connected to the power supply; The source of M11 is grounded, the drain is connected to the sources of M01 and M02, and the gate is connected to the clock control signal CK2.

4. The control method of the comparator with preamplifier according to claim 3, characterized in that: The working states of the preamplifier and the latch are controlled by the clock control signal CK1 and its inverted signals CK1B and CK2, specifically: In the first stage, the clock control signal CK1 is at a high level, and the inverted signal CK1B of CK1 is at a low level, so that the preamplifier works and the latch is in a reset state; after the preamplifier amplifies the signal of the output node to a preset gain, the second stage is entered; In the second stage, the clock control signal CK1 is kept at a high level, the inverted signal CK1B of CK1 is at a low level, and the clock control signal CK2 is at a high level, so that the latch enters operation. After the latch amplifies the input signal to the latch node, the third stage is entered. In the third stage, the clock control signal CK1 of the preamplifier is turned off, and the inverted signal CK1B of CK1 is pulled high, the clock control signal CK2 is still at a high level, the preamplifier is reset, and the latch enters the regeneration stage; wait for the latch to produce a result, and enter the fourth stage; In the fourth stage, the clock control signal CK2 of the latch is turned off, and at this time, the preamplifier and the latch are both reset.

5. The control method of the comparator with preamplifier according to claim 1, characterized in that: The preamplifier includes five MOS tubes MA13-MA17 and two capacitors C4-C5, wherein: The drain of MA14 is connected to the node VN, the source is connected to the drain of MA13, and the gate is connected to INN; The drain of MA15 is connected to the node VP, the source is connected to the drain of MA13, and the gate is connected to INP; The gate of MA13 is connected to the clock control signal CK1, and the source is connected to the power ground; The gate of the MA16 is connected to the clock control signal CK1, the source is connected to the power supply voltage, and the drain is connected to the node VN; The gate of MA17 is connected to the clock control signal CK1, the source is connected to the power supply voltage, and the drain is connected to the node VP; One end of the capacitor C4 is connected to the power ground, and the other end is connected to the node VN; One end of the capacitor C5 is connected to the power ground, and the other end is connected to the node VP.

6. The control method of the comparator with preamplifier according to claim 5, characterized in that: The latch includes 6 MOS tubes M12-M18, wherein: The gate of M17 is connected to the node VN, the source is connected to the power ground, and the drain is connected to the output node OUTN; The gate of M18 is connected to the node VP, the source is connected to the power ground, and the drain is connected to the output node OUTP; The gate of M12 is connected to the node OUTP, the source is connected to the power ground, and the drain is connected to the output node OUTN; The gate of M13 is connected to the node OUTN, the source is connected to the power ground, and the drain is connected to the output node OUTP; The gate of M14 is connected to the output node OUTP, the drain is connected to the output node OUTN, and the source is connected to the drain of M16; The gate of M15 is connected to the output node OUTN, the drain is connected to the output node OUTP, and the source is connected to the drain of M16; The gate of M16 is connected to the inverted signal CK2B of the clock control signal CK2 , the source is connected to the power supply voltage, and the drain is connected to the sources of M14 and M15 .

7. The control method of the comparator with preamplifier according to claim 6, characterized in that: The working states of the preamplifier and latch are controlled by clock control signals CK1 and CK2B, specifically: The first stage: the clock control signal CK1 of the preamplifier and the inverted signal CK2B of the clock control signal CK2 of the latch are controlled to be high level, so that the preamplifier works and the latch is in a reset state; after the preamplifier amplifies the signal of the output node to a preset gain, the second stage is entered; The second stage: keep the clock control signal CK1 at a high level and CK2B at a low level, keep the preamplifier working, and control the latch to work; after the latch amplifies the input signal to the latch node, enter the third stage; The third stage: the clock control signal CK1 of the preamplifier is turned off, the preamplifier is reset, the latch enters the regeneration stage, and the latch generates a result before entering the fourth stage; The fourth stage: the inverted signal CK2B of the clock control signal CK2 is pulled high, and the preamplifier and the latch are reset.

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