High-precision quick-response POR circuit
By introducing a constant current source module and a POR comparison module into the POR circuit, the power supply voltage is directly sampled, which solves the problems of slow detection speed and large threshold voltage deviation of existing POR circuits, and realizes high-precision and fast response power detection to ensure effective protection of the system.
Patent Information
- Application Number
- CN202411973170.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-30
- Publication Date
- 2025-04-25
AI Technical Summary
The detection speed of existing POR circuits is slow, and the threshold voltage deviation is large, which is susceptible to the influence of temperature and process angle, resulting in poor system protection.
A high-precision and fast response POR circuit is designed. By introducing a constant current source module and a POR comparison module into the comparison sub-circuit, the influence of parasitic gate capacitance is reduced, and the use of voltage-dividing resistors is reduced by directly sampling the power supply voltage, thereby improving detection speed and accuracy.
It greatly improves the detection threshold accuracy and response speed of the POR circuit, can detect system power changes in time, and effectively protect circuits and systems.
Smart Images
Figure CN119892038A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a high-precision and fast-response POR circuit. Background Art
[0002] The POR (power-on reset) circuit is generally at the highest priority in the system, so there is generally no available reference voltage source and current source. Therefore, the threshold voltage of the POR circuit generally has a large deviation (the error range of the common POR circuit is about +-20%) and is easily affected by temperature and process angle.
[0003] Secondly, as a high priority circuit in the circuit, the POR circuit must be alive at all times to detect the power supply voltage. Therefore, the POR circuit has very high requirements on power consumption. Due to this limitation, the detection speed of the POR circuit is also very slow.
[0004] Generally, since the reference circuit has a lower priority than the POR circuit, when the threshold voltage of the POR circuit is set low (taking 1.6V as an example), no stable reference voltage is available; secondly, if the reference priority is higher than the POR, when the power supply voltage is lower than the minimum operating voltage of the reference source, the reference source outputs zero voltage, causing the POR circuit to give an erroneous indication and fail to protect the system. Summary of the invention
[0005] The main purpose of the present invention is to provide a high-precision and fast-response POR circuit, aiming to improve the detection speed of the POR circuit.
[0006] To achieve the above object, the present invention provides a high-precision and fast-response POR circuit, comprising a start-up subcircuit, a reference subcircuit connected to the start-up subcircuit, and a comparison subcircuit connected to the reference subcircuit, wherein the start-up subcircuit receives a start-up signal to start the entire circuit, the reference subcircuit is used to generate a reference voltage, and the comparison subcircuit receives and compares a sampled voltage of the reference voltage and a power supply voltage, and when the sampled voltage is greater than the reference voltage, outputs a reset signal RSTN to a subsequent circuit; The comparison subcircuit includes a constant current source module and a POR comparison module, wherein the constant current source module is connected to the reference subcircuit and provides a constant current source for the POR comparison module; The POR comparison module includes an eighth NMOS tube, a ninth NMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a ninth resistor and a comparator. The gates of the eighth NMOS tube and the ninth NMOS tube are both connected to the constant current source module, and the sources are both grounded; the drain of the eighth NMOS tube is connected to the drain of the thirteenth PMOS tube, and the drain of the ninth NMOS tube is connected to the drain of the fourteenth PMOS tube; the source of the thirteenth PMOS tube is connected to the drain of the tenth PMOS tube in the reference subcircuit, used for receiving the reference voltage, and the drain is connected to the first input terminal of the comparator; one end of the ninth resistor is connected to the power supply voltage, and the source of the fourteenth PMOS tube is connected to the other end of the ninth resistor, used for receiving the sampling voltage; the drain of the fourteenth PMOS tube is connected to the second input terminal of the comparator, and the gate is connected to the gate and drain of the thirteenth PMOS tube; the output terminal of the comparator outputs a reset signal.
[0007] Preferably, the reference subcircuit comprises a bandgap reference core module, an operational amplifier module, a first NMOS tube, a second NMOS tube, a fourth NMOS tube, a ninth PMOS tube, a tenth PMOS tube and a first capacitor; the gates of the first NMOS tube and the second NMOS tube are connected to each other, and the source is grounded, the drain of the first NMOS tube is connected to the gate and the drain of the fourth PMOS tube in the starter subcircuit; the drain of the second NMOS tube is connected to the gates of the ninth PMOS tube and the tenth PMOS tube, and one end of the first capacitor, and the other end of the first capacitor is grounded; the gate and drain of the fourth PMOS tube are connected to the gate and the drain of the fourth PMOS tube in the starter subcircuit; The gates of the ninth and tenth PMOS tubes are connected to the power supply voltage, and the gates are connected to the starter sub-circuit. The drain of the tenth PMOS tube is connected to the bandgap reference core module and the source of the thirteenth PMOS tube in the comparator sub-circuit to output the reference voltage to the comparison sub-circuit. The operational amplifier module is connected to the bandgap reference core module. When the bandgap reference core module is started, the operational amplifier module is turned on, the operational amplifier module starts to work and provides a driving voltage of the working current for the reference sub-circuit.
[0008] Preferably, the starter subcircuit comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first Native tube, a second Native tube, a first low-voltage tube, a second low-voltage tube and a first resistor; the gate of the first PMOS tube is used to receive a start signal, the sources of the first PMOS tube, the third PMOS tube and the fourth PMOS tube are connected to the power supply voltage, and the drain of the first PMOS tube is connected to the source of the second PMOS tube; the gate of the second PMOS tube is grounded, and the drain is respectively connected to the drain of the first Native tube, the gate of the second Native tube, and the drain of the second Native tube. The source of the first Native tube is connected to the drain of the first low-voltage tube, the gates of the two are connected to each other and connected to the source of the second low-voltage tube, and the source of the first low-voltage tube is grounded; the drain of the second Native tube is connected to the drain of the third PMOS tube and the gate of the fourth PMOS tube, and the source is connected to the drain of the second low-voltage tube; the source of the second low-voltage tube is grounded through the first resistor; the gate of the third PMOS tube is connected to the gates of the ninth PMOS tube and the tenth PMOS tube in the reference sub-circuit; the drain of the fourth PMOS tube is connected to the gate and drain of the first NMOS tube in the reference sub-circuit.
[0009] Preferably, the bandgap reference core module includes a first triode, a second triode, a second resistor, a third resistor, a fourth resistor and a fifth resistor; the base and collector of the first triode and the second triode are both grounded, the emitter of the first triode is connected to one end of the second resistor, the other end of the second resistor is connected to one end of the fourth resistor, and the other end of the fourth resistor is connected to the drain of the tenth PMOS tube; the emitter of the second triode is connected to one end of the fifth resistor, the other end of the fifth resistor is connected to one end of the third resistor, and the other end of the third resistor is connected to one end of the fourth resistor.
[0010] Preferably, the operational amplifier module includes a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube and an eighth PMOS tube whose sources are connected to the power supply voltage; and also includes a third native tube, a fourth native tube, a third low-voltage tube, a fourth low-voltage tube and a third NMOS tube; The gate of the fifth PMOS tube is connected to the gate and drain of the sixth PMOS tube, and the drain is connected to the gate and drain of the first NMOS tube; the drain and gate of the sixth PMOS tube are also connected to the drain of the third native tube; the source of the third native tube is connected to the drain of the third low-voltage tube, and the source of the third low-voltage tube is connected to the drain of the third NMOS tube; the gate of the seventh PMOS tube is connected to the gate of the eighth PMOS tube, and the drain is connected to the gate and the drain of the fourth native tube, the source of the fourth native tube is connected to the drain of the fourth low-voltage tube, and the source of the fourth low-voltage tube is connected to the drain of the third NMOS tube; the gates of the third native tube and the third low-voltage tube are connected to each other and connected to one end of the second resistor in the bandgap reference core module; the gates of the fourth native tube and the fourth low-voltage tube are connected to each other and connected to one end of the third resistor in the bandgap reference core module; the source of the third NMOS tube is grounded, and the gate is connected to the gate and drain of the fourth NMOS tube.
[0011] Preferably, the constant current source module in the comparison subcircuit includes a sixth resistor, a seventh resistor, an eighth resistor, an operational amplifier, an eleventh PMOS tube, a twelfth PMOS tube and a seventh NMOS tube, one end of the sixth resistor is connected to the reference subcircuit to receive a reference voltage, the other end is connected to one end of the seventh resistor and the first input end of the operational amplifier, and the other end of the seventh resistor is grounded; the output end of the operational amplifier is connected to its second input end, the gate and drain of the eleventh PMOS tube and one end of the eighth resistor, and the other end of the eighth resistor is grounded; the sources of the eleventh PMOS tube and the twelfth PMOS tube are connected to the power supply voltage, and the gates are connected to each other; the drain of the twelfth PMOS tube is connected to the drain of the seventh NMOS tube and the gates of the seventh NMOS tube, the eighth NMOS tube and the ninth NMOS tube, so as to provide a constant current source to the POR comparison module, and the source of the seventh NMOS tube is grounded.
[0012] Preferably, the comparison subcircuit further comprises a delay module, wherein the delay module is connected to the output end of the comparator and is used for delaying the output of the reset signal.
[0013] Preferably, the high-precision and fast-response POR circuit further includes a D trigger connected to the delay module to receive a reset signal; the D trigger is triggered to flip and then outputs a signal to the startup subcircuit to completely shut down the startup subcircuit.
[0014] In the technical solution of the present invention, the comparison subcircuit provides power for the POR comparison module through a constant current source, and the sources of the thirteenth PMOS tube and the fourteenth PMOS tube receive the reference voltage and the sampling voltage respectively, which reduces the influence of the parasitic gate capacitance and greatly improves the response speed. When the system loses power quickly, it can detect feedback in time, greatly improves the detection threshold accuracy of the existing POR circuit, and achieves the purpose of protecting the circuit and the system. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 It is a schematic diagram of a reset circuit in the prior art; Figure 2 A circuit diagram of a start-up subcircuit and a reference subcircuit in a high-precision and fast-response POR circuit according to an embodiment of the present invention; Figure 3 A circuit diagram of a comparison subcircuit in a high-precision and fast-response POR circuit according to an embodiment of the present invention; Figure 4 a is a schematic diagram showing the relationship between the power supply voltage, the reference voltage and the reset voltage during the startup and operation of the reset circuit in the prior art; Figure 4 b is a schematic diagram of the relationship between the power supply voltage, the reference voltage and the reset voltage during the startup and operation of the high-precision and fast-response POR circuit of an embodiment of the present invention.
[0016] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION
[0017] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.
[0018] The present invention is further described below in conjunction with the accompanying drawings.
[0019] The present invention designs a high-precision and fast-response POR circuit with a built-in low-voltage startup bandgap reference core module. When the input voltage cannot meet the reference, the power supply voltage is output, which solves the accuracy problem and the false flip problem. By closing the startup circuit current, reducing the current of each branch, etc., the total current is designed to be less than 400nA. On this basis, a direct sampling power supply voltage is designed without a voltage divider resistor, and the power supply voltage is input from the source level together with the reference voltage, which reduces the influence of the gate parasitic capacitance, greatly improves the detection speed, improves the response speed, and greatly reduces the total circuit area, while also meeting the requirement of low power consumption.
[0020] The high-precision and fast-response POR circuit of the embodiment of the present invention includes a start-up subcircuit, a reference subcircuit connected to the start-up subcircuit, and a comparison subcircuit connected to the reference subcircuit. The start-up subcircuit receives a start-up signal ST to start the entire circuit, the reference subcircuit is used to generate a reference voltage VREF, and the comparison subcircuit receives and compares the reference voltage VREF and a sampling voltage VSAM of the power supply voltage. When the sampling voltage VSAM is greater than the reference voltage VREF, a reset signal RSTN is output to the subsequent circuit.
[0021] like Figure 2As shown, the starter circuit includes a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a first Native tube MN_NA1, a second Native tube MN_NA2, a first low-voltage tube MN_LV1, a second low-voltage tube MN_LV2, and a first resistor R1; the gate of the first PMOS tube MP1 is connected to the start signal sending end to receive the start signal ST, the source of the first PMOS tube MP1, the third PMOS tube MP3 and the fourth PMOS tube MP4 are connected to the power supply voltage VIN, and the drain of the first PMOS tube MP1 is connected to the source of the second PMOS tube MP2; the gate of the second PMOS tube MP2 is grounded GND, and the drain is respectively connected to the drain of the first Native tube MN_NA1, the gate of the second Native tube MN_NA2 and the second low-voltage tube MN_LV 2; the source of the first Native tube MN_NA1 is connected to the drain of the first low-voltage tube MN_LV1, the gates of the two are connected to each other and connected to the source of the second low-voltage tube MN_LV2, and the source of the first low-voltage tube MN_LV1 is grounded GND; the drain of the second Native tube MN_NA2 is connected to the drain of the third PMOS tube MP3 and the gate of the fourth PMOS tube MP4, and the source is connected to the drain of the second low-voltage tube MN_LV2; the source of the second low-voltage tube MN_LV2 is grounded through the first resistor R1, one end of the first resistor R1 is connected to the source of the second low-voltage tube MN_LV2, and the other end is grounded GND; the gate of the third PMOS tube MP3 is connected to the gates of the ninth PMOS tube MP9 and the tenth PMOS tube MP10 in the reference sub-circuit; the drain of the fourth PMOS tube MP4 is connected to the gate and drain of the first NMOS tube MN1 in the reference sub-circuit.
[0022] In a specific embodiment, the first Native transistor MN_NA1 and the second Native transistor MN_NA2 are both N-type native devices, whose conduction threshold is approximately 0, but whose withstand voltage is relatively high; the first low-voltage transistor MN_LV1 and the second low-voltage transistor MN_LV2 are both N-type low-voltage devices, whose conduction threshold is relatively low and whose withstand voltage is relatively low. Using the two devices in series can not only increase the withstand voltage, but also maintain a low conduction threshold, thereby reducing the minimum operating voltage of the circuit.
[0023] Specifically, the first PMOS tube MP1 in the startup subcircuit receives the startup signal ST. In the initial state, the startup signal ST is at a low level. MP1 is a very small inverse ratio tube, used as a very small linear region resistor, and turned on after startup; the second PMOS tube MP2 is an inverse ratio tube, whose channel length is greater than the channel width, and used as a large resistor; the gate voltages of the second Native tube MN_NA2 and the second low-voltage tube MN_LV2 increase and are turned on, the voltage on the first resistor R1 increases, the first Native tube MN_NA1 and the first low-voltage tube MN_LV1 begin to be turned on, the gate voltages of the second Native tube MN_NA2 and the second low-voltage tube MN_LV2 are pulled down, and the startup subcircuit enters a balanced state, generating a stable startup current I START =VGS MN_LV1 / R1, where VGS MN_LV1 is the gate-source voltage of the first low-voltage transistor MN_LV1, and R1 is the resistance value of the first resistor R1. At this time, the gate voltage of the fourth PMOS transistor MP4 is pulled down, the fourth PMOS transistor MP4 starts to conduct, and the entire circuit enters the startup process.
[0024] like Figure 2 As shown, the reference subcircuit includes a bandgap reference core module, an operational amplifier module, a first NMOS transistor MN1, a second NMOS transistor MN2, a fourth NMOS transistor MN4, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10 and a first capacitor C1; the gates of the first NMOS transistor MN1 and the second NMOS transistor MN2 are connected to each other, and the source is grounded GND, the drain of the first NMOS transistor MN1 is connected to the gate and the drain of the fourth PMOS transistor MP4 in the starter subcircuit; the drain of the second NMOS transistor MN2 is connected to the gates of the ninth PMOS transistor MP9 and the tenth PMOS transistor MP10, and one end of the first capacitor C1, and the other end of the first capacitor C1 is grounded; the fourth PMOS transistor MN4 is connected to the gates of the ninth PMOS transistor MP9 and the tenth PMOS transistor MP10, and one end of the first capacitor C1, and the other end of the first capacitor C1 is grounded; The gate and drain of the OS transistor MP4 are connected to each other and to the drain of the ninth PMOS transistor MP9 and the operational amplifier module, and the source of the fourth PMOS transistor MP4 is grounded; the sources of the ninth PMOS transistor MP9 and the tenth PMOS transistor MP10 are connected to the power supply voltage VIN, and the gates are connected to the gate of the third PMOS transistor MP3 in the startup subcircuit, and the drain of the tenth PMOS transistor MP10 is connected to the bandgap reference core module and the comparator subcircuit to output the reference voltage VREF to the comparison subcircuit; the operational amplifier module is connected to the bandgap reference core module, and when the bandgap reference core module is started, the operational amplifier module is turned on, the operational amplifier module starts to work and provides a driving voltage for the working current to the reference subcircuit.
[0025] When the circuit enters the startup process, the fourth PMOS tube MP4 is turned on, the gate voltages of the first NMOS tube MN1 and the second NMOS tube MN2 are increased and turned on, and then the gate voltages of the ninth PMOS tube MP9 and the tenth PMOS tube MP10 are pulled down and turned on, and the bandgap reference core module is started and a static working point is established; at this time, the operational amplifier circuit starts to work, providing the ninth PMOS tube MP9 and the tenth PMOS tube MP10 with a driving voltage of the working current, and the circuit gradually enters a balanced state. After the startup is completed, a 1.2V standard reference voltage is output; at the same time, the current of the tenth PMOS tube MP10 gradually increases, and since the currents of the third PMOS tube MP3 and the tenth PMOS tube MP10 in the startup subcircuit are equal, the increase in the current of the third PMOS tube MP3 will cause the gate voltage of the fourth PMOS tube MP4 to be pulled up, thereby cutting off the startup subcircuit, and preventing the startup subcircuit from affecting the operation of the reference subcircuit.
[0026] like Figure 2 As shown, the bandgap reference core module includes a first triode Q1, a second triode Q2, a second resistor R2, a third resistor R3, a fourth resistor R4 and a fifth resistor R5; the base and collector of the first triode Q1 and the second triode Q2 are both grounded GND, the emitter of the first triode Q1 is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is connected to the drain of the tenth PMOS tube MP10; the emitter of the second triode Q2 is connected to one end of the fifth resistor R5, the other end of the fifth resistor R5 is connected to one end of the third resistor R3, and the other end of the third resistor R3 is connected to one end of the fourth resistor R4.
[0027] In other embodiments, the bandgap reference core module can use other bandgap reference circuits in the prior art according to the needs of designers. The bandgap reference core module of the embodiment of the present invention has high precision and requires low power supply voltage.
[0028] like Figure 2As shown, the operational amplifier module includes a fifth PMOS tube MP5, a sixth PMOS tube MP6, a seventh PMOS tube MP7 and an eighth PMOS tube MP8, whose sources are connected to the power supply voltage; and also includes a third native tube MN_NA3, a fourth native tube MN_NA4, a third low-voltage tube MN_LV3, a fourth low-voltage tube MN_LV4 and a third NMOS tube MN3; the gate of the fifth PMOS tube MP5 is connected to the gate and drain of the sixth PMOS tube MP6, and the drain is connected to the gate and drain of the first NMOS tube MN1; the drain and gate of the sixth PMOS tube MP6 are also connected to the drain of the third native tube MN_NA3; the source of the third native tube MN_NA3 is connected to the drain of the third low-voltage tube MN_LV3, and the source of the third low-voltage tube MN_LV3 is connected to the drain of the third NMOS tube MN3. drain; the gate of the seventh PMOS tube MP7 is connected to the gate of the eighth PMOS tube MP8, and the drain is connected to the gate and the drain of the fourth native tube MN_NA4, the source of the fourth native tube MN_NA4 is connected to the drain of the fourth low-voltage tube MN_LV4, and the source of the fourth low-voltage tube MN_LV4 is connected to the drain of the third NMOS tube MN3; the gates of the third native tube MN_NA3 and the third low-voltage tube MN_LV3 are connected to each other and to one end of the second resistor R2 in the bandgap reference core module, that is, the VP end; the gates of the fourth native tube MN_NA4 and the fourth low-voltage tube MN_LV4 are connected to each other and to one end of the third resistor R3 in the bandgap reference core module, that is, the VN end; the source of the third NMOS tube MN3 is grounded, and the gate is connected to the gate and drain of the fourth NMOS tube MN4.
[0029] In a specific embodiment, the third native transistor MN_NA3 and the fourth native transistor MN_NA4 are both N-type native devices, whose conduction threshold is approximately 0, but whose withstand voltage is relatively high; the third low-voltage transistor MN_LV3 and the fourth low-voltage transistor MN_LV4 are both N-type low-voltage devices, whose conduction threshold is relatively low and whose withstand voltage is relatively low. Using the two devices in series can not only increase the withstand voltage, but also maintain a low conduction threshold, thereby reducing the minimum operating voltage of the circuit.
[0030] When the bandgap reference core module is started, a static operating point is established, and the voltages of the VN and VP terminals connected to the operational amplifier module increase. At this time, the operational amplifier module is started and begins to work, providing a driving voltage of the operating current for the ninth field effect transistor MP9 and the tenth field effect transistor MP10 in the reference sub-circuit, and the circuit gradually enters a balanced state.
[0031] In other embodiments, the operational amplifier module in the embodiment of the present invention may also use other operational amplifier circuits in the prior art. The operational amplifier module used in the embodiment of the present invention has a low conduction threshold and a low minimum operating voltage, which can meet the low power consumption requirements of this embodiment.
[0032] During the circuit startup process, the power supply voltage VIN gradually rises from 0. As the bias circuit starts, the current on the first resistor R1 gradually increases, that is, the ISART current gradually increases, and the current of the fourth PMOS tube MP4 begins to increase. Its current is mirrored to the second NMOS tube MN2 through the first NMOS tube MN1. The second NMOS tube MN2 pulls down the Gate voltage of the third PMOS tube MP3, the ninth PMOS tube MP9, and the tenth PMOS tube MP10. At this time, the operational amplifier module and the bandgap reference core module have working current; when the power supply voltage VIN voltage continues to increase, the current of the third PMOS tube MP3 continues to increase. When its current is greater than the ISTART current, the fourth PMOS tube MP4 is turned off, and the startup circuit ends. Before the reference sub-circuit loop is established, the tenth PMOS tube MP10 is always in the on state, so the reference voltage output by the reference sub-circuit is always the power supply voltage; that is, after the loop is established, the reference voltage target outputs a 1.2V voltage. If the power supply voltage is lower than 1.2V, the power supply voltage is output, and the POR output signal is always kept from malfunctioning.
[0033] like Figure 3 As shown, the comparison subcircuit includes a constant current source module and a POR comparison module, the constant current source module is connected to the reference subcircuit and provides a constant current source for the POR comparison module; The POR comparison module includes an eighth NMOS tube MN8, a ninth NMOS tube MN9, a thirteenth PMOS tube MP13, a fourteenth PMOS tube MP14, a ninth resistor R9 and a comparator COMP. The gates of the eighth NMOS tube MN8 and the ninth NMOS tube MN9 are both connected to the constant current source module, and the sources are both grounded; the drain of the eighth NMOS tube MN8 is connected to the drain of the thirteenth PMOS tube MP13, the drain of the ninth NMOS tube MN9 is connected to the drain of the fourteenth PMOS tube MP14; the source of the thirteenth PMOS tube MP13 is connected to the The drain of the tenth PMOS tube MP10 in the reference sub-circuit is used to receive the reference voltage VREF, and the drain is connected to the first input terminal of the comparator COMP; one end of the ninth resistor R9 is connected to the power supply voltage VIN, and the source of the fourteenth PMOS tube MP14 is connected to the other end of the ninth resistor R9, and is used to receive the sampling voltage VSAM; the drain of the fourteenth PMOS tube MP14 is connected to the second input terminal of the comparator COMP, and the gate is connected to the gate and drain of the thirteenth PMOS tube MP13; the output terminal of the comparator COMP outputs a reset signal RSTN.
[0034] In the embodiment of the present invention, the sources of the thirteenth PMOS tube MP13 and the fourteenth PMOS tube MP14 receive the reference voltage VREF and the sampling voltage VSAM respectively, which reduces the influence of the parasitic gate capacitance and greatly improves the response speed. When the system loses power quickly, it can detect feedback in time, greatly improves the detection threshold accuracy of the existing POR circuit, and achieves the purpose of protecting the circuit and the system.
[0035] Meanwhile, in the embodiment of the present invention, when sampling the power supply voltage, the sampling voltage VSAM is equal to the power supply voltage minus the voltage on the ninth resistor R9, that is, VSAMPLE=VIN-IREFÍR 9 , where VSAMPLE is the sampling voltage, VIN is the power supply voltage, IREF is the constant current source, and R9 is the resistance value of the ninth resistor R9. This makes it unnecessary to use voltage divider resistors in this embodiment, greatly reducing the use of resistors and reducing the chip area.
[0036] like Figure 3 As shown, the constant current source module in the comparison subcircuit includes a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, an operational amplifier OPA, an eleventh PMOS transistor MP11, a twelfth PMOS transistor MP12 and a seventh NMOS transistor MN7. One end of the sixth resistor R6 is connected to the drain of the tenth PMOS transistor MP10 in the reference subcircuit to receive the reference voltage VREF, and the other end is connected to one end of the seventh resistor R7 and the first input end of the operational amplifier OPA. The other end of the seventh resistor R7 is grounded; the output end of the operational amplifier OPA is connected to the second input end thereof. The input terminal, the gate and drain of the eleventh PMOS tube MP11 and one end of the eighth resistor R8, and the other end of the eighth resistor R8 is grounded; the sources of the eleventh PMOS tube MP11 and the twelfth PMOS tube MP12 are connected to the power supply voltage VIN, and the gates are connected to each other; the drain of the twelfth PMOS tube MP12 is connected to the drain of the seventh NMOS tube MN7 and the gates of the seventh NMOS tube MN7, the eighth NMOS tube MN8 and the ninth NMOS tube MN9, so as to provide a constant current source to the POR comparison module, and the source of the seventh NMOS tube MN7 is grounded.
[0037] In a specific embodiment, the 1.2V reference voltage VREF is divided by the sixth resistor R6 and the seventh resistor R7, and then fed back by the operational amplifier OPA to generate a constant current IREF as the current source of the POR comparator, and its value is expressed by the equation Calculation is performed, wherein VREF is the reference voltage VREF outputted in the reference sub-circuit, R6 is the resistance value of the sixth resistor, and R7 is the resistance value of the seventh resistor; the constant current source is converted into a P-type current source after being mirrored by the eleventh PMOS tube MP11 and the twelfth PMOS tube MP12, and then converted into an N-type current source after being mirrored by the seventh NMOS tube MN7, the eighth NMOS tube MN8, and the ninth NMOS tube MN9.
[0038] When the sampling voltage VSAM is higher than the reference voltage VREF, the comparator COMP flips, indicating that the circuit can work normally. The voltage detection value of the POR comparison module is VDECT=VREF+IREF ÍR 9 Since IREF is a constant current source, and the temperature coefficients and process angle deviations of the eighth resistor R8 and the ninth resistor R9 offset each other, the voltage detection value VDECT of the POR comparison module is theoretically not affected by temperature and process angle.
[0039] The comparison subcircuit also includes a delay module for outputting a reset signal after a delay to avoid erroneous output when the circuit is not completely stable.
[0040] The high-precision and fast-response POR circuit of the embodiment of the present invention also includes a D trigger, which is connected to the delay module and receives a reset signal. After the D trigger is triggered and flipped, it outputs a signal to the startup subcircuit to completely shut down the startup subcircuit, thereby significantly saving the power consumption of the circuit. The working principle of the embodiment of the present invention is: The startup subcircuit receives the startup signal ST, and the circuit starts to start: The start signal ST is at a low level in the initial state. The first PMOS tube MP1 is turned on after being started. The gate voltage of the second Native tube MN_NA2 and the second low-voltage tube MN_LV2 increases and turns on. The voltage on the first resistor R1R1 increases. The first Native tube MN_NA1 and the first low-voltage tube MN_LV1 begin to turn on. The gate voltage of the second Native tube MN_NA2 and the second low-voltage tube MN_LV2 is pulled down. The start sub-circuit enters a balanced state, generating a stable start current I START .
[0041] Starting current I STARTThe gate voltage of the fourth PMOS tube MP4 is pulled down, and the fourth PMOS tube MP4 starts to be turned on. At this time, the gate voltages of the first NMOS tube MN1 and the second NMOS tube MN2 are increased and turned on. Then, the gate voltages of the third PMOS tube MP3, the ninth PMOS tube MP9, and the tenth PMOS tube MP10 are pulled down and turned on. The bandgap reference core module is started and a static operating point is established. The voltages of the VN terminal and the VP terminal are increased. At this time, the operational amplifier module starts to work and provides a driving voltage of the operating current for the third PMOS tube MP3, the ninth PMOS tube MP9, and the tenth PMOS tube MP10. The circuit gradually enters a balanced state, and the output reference voltage VREF is 1.2V.
[0042] When the circuit is started and the loop is established, the reference voltage VREF no longer needs to be pulled up by the starter subcircuit, and the current of the third PMOS tube MP3 gradually increases, pulling up the gate voltage of the fourth PMOS tube MP4 to cut off the starter circuit, thereby preventing the starter circuit from affecting the reference subcircuit.
[0043] The 1.2V reference voltage VREF is divided by the sixth resistor R6 and the seventh resistor R7, and then fed back by the operational amplifier OPA to generate a constant current IREF as the current source of the POR comparison module; the current is mirrored by the eleventh PMOS tube MP11 and the twelfth PMOS tube MP12 to be converted into a P-type current source, and then mirrored by the seventh NMOS tube MN7, the eighth NMOS tube MN8, and the ninth NMOS tube MN9 to be converted into an N-type current source. The input voltage of the POR comparison module is the reference voltage VREF and the sampling voltage VSAMV, which are input from the source of the thirteenth PMOS tube MP13 and the fourteenth PMOS tube MP14 respectively. When the sampling voltage VSAM is higher than the reference voltage VREF, the comparator COMP flips, indicating that the circuit can work normally.
[0044] After the comparator COMP flips, it outputs after a delay. At the same time, the D flip-flop flips, and the current of the startup sub-circuit is completely turned off, which greatly saves the power consumption of the circuit.
[0045] Since the reset circuit in the prior art usually has the highest priority and no reference source, the embodiment of the present invention designs a bandgap reference subcircuit started by a low power supply voltage VIN, so that the reference subcircuit has the highest priority in the system. The power-on reset circuit of this embodiment has a high-precision reference source, and its flip threshold is not easily affected by factors such as process angle and temperature.
[0046] Furthermore, when the power supply voltage VIN of the bandgap reference is lower than the minimum operating voltage, the output voltage of the reset circuit structure in the prior art will directly drop to zero or be at a lower voltage value, which will cause the reset circuit to flip erroneously, thereby losing the protection effect on the subsequent circuit. Figure 4(a) shows the working state of the reset circuit using a traditional bandgap reference: the reference voltage VREF is generally high enough to meet the minimum working voltage point, and when it is lower than the minimum working voltage, the output of the reference is generally 0 or a lower voltage (such as 0.2-0.3V). When the power supply voltage VIN rises to a certain stage but does not reach the threshold voltage of the reset circuit (i.e., the working voltage), an erroneous flip will occur (see reset signal RSTN); then, the power supply voltage VIN continues to rise, the reset circuit returns to normal, and flips normally when the threshold voltage of the reset circuit is reached.
[0047] The bandgap reference source circuit designed in the embodiment of the present invention can always approximately follow the power supply voltage VIN before the startup completion stage, that is, when the reference is lower than the minimum operating voltage, it is the output power supply voltage VIN; after the startup is completed, the reference voltage VREF is output, that is, when it is at the normal operating voltage, the output is the reference voltage VREF; Figure 4 (b) shows the situation when the circuit of the present invention is started, and there is no abnormal flipping during the startup process.
[0048] It should be understood that the above are only preferred embodiments of the present invention, and the patent scope of the present invention cannot be limited thereto. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.
Claims
1. A high-precision and fast-response POR circuit, comprising a start-up subcircuit, a reference subcircuit connected to the start-up subcircuit, and a comparison subcircuit connected to the reference subcircuit, wherein the start-up subcircuit receives a start-up signal to start the entire circuit, the reference subcircuit is used to generate a reference voltage, and the comparison subcircuit receives and compares the reference voltage and a sampled voltage of a power supply voltage, and outputs a reset signal RSTN to a subsequent circuit when the sampled voltage is greater than the reference voltage; characterized in that: The comparison subcircuit includes a constant current source module and a POR comparison module, wherein the constant current source module is connected to the reference subcircuit and provides a constant current source for the POR comparison module; The POR comparison module includes an eighth NMOS tube, a ninth NMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a ninth resistor and a comparator. The gates of the eighth NMOS tube and the ninth NMOS tube are both connected to the constant current source module, and the sources are both grounded; the drain of the eighth NMOS tube is connected to the drain of the thirteenth PMOS tube, and the drain of the ninth NMOS tube is connected to the drain of the fourteenth PMOS tube; the source of the thirteenth PMOS tube is connected to the drain of the tenth PMOS tube in the reference subcircuit, used for receiving the reference voltage, and the drain is connected to the first input terminal of the comparator; one end of the ninth resistor is connected to the power supply voltage, and the source of the fourteenth PMOS tube is connected to the other end of the ninth resistor, used for receiving the sampling voltage; the drain of the fourteenth PMOS tube is connected to the second input terminal of the comparator, and the gate is connected to the gate and drain of the thirteenth PMOS tube; the output terminal of the comparator outputs a reset signal.
2. The high-precision and fast-response POR circuit according to claim 1, characterized in that: The reference subcircuit comprises a bandgap reference core module, an operational amplifier module, a first NMOS tube, a second NMOS tube, a fourth NMOS tube, a ninth PMOS tube, a tenth PMOS tube and a first capacitor; the gates of the first NMOS tube and the second NMOS tube are connected to each other, the source is grounded, the drain of the first NMOS tube is connected to the gate and the drain of the fourth PMOS tube in the starter subcircuit; the drain of the second NMOS tube is connected to the gates of the ninth PMOS tube and the tenth PMOS tube, one end of the first capacitor, and the other end of the first capacitor is grounded; the gate and drain of the fourth PMOS tube are connected to each other. The fourth PMOS tube is connected to each other and to the drain of the ninth PMOS tube and the operational amplifier module, and the source of the fourth PMOS tube is grounded; the sources of the ninth PMOS tube and the tenth PMOS tube are connected to the power supply voltage, and the gates are connected to the starter subcircuit, and the drain of the tenth PMOS tube is connected to the bandgap reference core module and the source of the thirteenth PMOS tube in the comparator subcircuit to output the reference voltage to the comparison subcircuit; the operational amplifier module is connected to the bandgap reference core module, and when the bandgap reference core module is started, the operational amplifier module is turned on, the operational amplifier module starts to work and provides a driving voltage of the working current for the reference subcircuit.
3. The high-precision and fast-response POR circuit according to claim 2, characterized in that: The starter subcircuit includes a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first Native tube, a second Native tube, a first low-voltage tube, a second low-voltage tube and a first resistor; the gate of the first PMOS tube is used to receive a start signal, the sources of the first PMOS tube, the third PMOS tube and the fourth PMOS tube are connected to the power supply voltage, and the drain of the first PMOS tube is connected to the source of the second PMOS tube; The gate of the second PMOS tube is grounded, and the drain is respectively connected to the drain of the first Native tube, the gate of the second Native tube, and the gate of the second low-voltage tube; The source of the first Native tube is connected to the drain of the first low-voltage tube, the gates of the two are connected to each other and connected to the source of the second low-voltage tube, and the source of the first low-voltage tube is grounded; The drain of the second Native tube is connected to the drain of the third PMOS tube and the gate of the fourth PMOS tube, and the source is connected to the drain of the second low-voltage tube; The source of the second low-voltage tube is grounded through the first resistor; the gate of the third PMOS tube is connected to the gates of the ninth PMOS tube and the tenth PMOS tube in the reference subcircuit; the drain of the fourth PMOS tube is connected to the gate and drain of the first NMOS tube in the reference subcircuit.
4. The high-precision and fast-response POR circuit according to claim 2, characterized in that: The bandgap reference core module includes a first triode, a second triode, a second resistor, a third resistor, a fourth resistor and a fifth resistor; the base and collector of the first triode and the second triode are both grounded, the emitter of the first triode is connected to one end of the second resistor, the other end of the second resistor is connected to one end of the fourth resistor, and the other end of the fourth resistor is connected to the drain of the tenth PMOS tube; the emitter of the second triode is connected to one end of the fifth resistor, the other end of the fifth resistor is connected to one end of the third resistor, and the other end of the third resistor is connected to one end of the fourth resistor.
5. The high-precision and fast-response POR circuit according to claim 4, characterized in that: The operational amplifier module includes a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube and an eighth PMOS tube whose sources are connected to the power supply voltage; and also includes a third native tube, a fourth native tube, a third low-voltage tube, a fourth low-voltage tube and a third NMOS tube; The gate of the fifth PMOS tube is connected to the gate and drain of the sixth PMOS tube, and the drain is connected to the gate and drain of the first NMOS tube; the drain and gate of the sixth PMOS tube are also connected to the drain of the third native tube; the source of the third native tube is connected to the drain of the third low-voltage tube, and the source of the third low-voltage tube is connected to the drain of the third NMOS tube; the gate of the seventh PMOS tube is connected to the gate of the eighth PMOS tube, and the drain is connected to the gate and the drain of the fourth native tube, the source of the fourth native tube is connected to the drain of the fourth low-voltage tube, and the source of the fourth low-voltage tube is connected to the drain of the third NMOS tube; the gates of the third native tube and the third low-voltage tube are connected to each other and connected to one end of the second resistor in the bandgap reference core module; the gates of the fourth native tube and the fourth low-voltage tube are connected to each other and connected to one end of the third resistor in the bandgap reference core module; the source of the third NMOS tube is grounded, and the gate is connected to the gate and drain of the fourth NMOS tube.
6. The high-precision and fast-response POR circuit according to claim 1, characterized in that: The constant current source module in the comparison subcircuit includes a sixth resistor, a seventh resistor, an eighth resistor, an operational amplifier, an eleventh PMOS tube, a twelfth PMOS tube and a seventh NMOS tube. One end of the sixth resistor is connected to the reference subcircuit to receive a reference voltage, and the other end is connected to one end of the seventh resistor and the first input end of the operational amplifier, and the other end of the seventh resistor is grounded; the output end of the operational amplifier is connected to its second input end, the gate and drain of the eleventh PMOS tube and one end of the eighth resistor, and the other end of the eighth resistor is grounded; the sources of the eleventh PMOS tube and the twelfth PMOS tube are connected to the power supply voltage, and the gates are connected to each other; the drain of the twelfth PMOS tube is connected to the drain of the seventh NMOS tube and the gates of the seventh NMOS tube, the eighth NMOS tube and the ninth NMOS tube, so as to provide a constant current source to the POR comparison module, and the source of the seventh NMOS tube is grounded.
7. The high-precision and fast-response POR circuit according to claim 1, characterized in that: The comparison subcircuit also includes a delay module, which is connected to the output end of the comparator and is used to delay the output of the reset signal.
8. The high-precision and fast-response POR circuit according to claim 1, characterized in that: The high-precision and fast-response POR circuit also includes a D trigger connected to the delay module to receive a reset signal; the D trigger is triggered to flip and then outputs a signal to the startup subcircuit to completely shut down the startup subcircuit.