Novel logic gate

Abstract

The invention discloses a novel logic gate. The logic gate is composed of three power supply pins, two input interfaces and one output interface, the power supply pins are connected with a plurality of MOS tubes according to a specific mode, and the input interfaces are connected with grid electrodes of the MOS tubes. The unique structure enables the logic gate to have special logic operation capability. Meanwhile, in a circuit system comprising the logic gate, the logic gate serves as a key element to achieve a complex logic function, a new way is provided for electronic circuit design, and the logic gate can be widely applied to the related electronic field.

Description

Technical Field

[0001] The present invention relates to the field of electronic circuits, and in particular to a novel logic gate. Background Art

[0002] Among the existing logic gates, there are seven basic logic gates, which have functional and structural limitations. The present invention aims to provide a logic gate with a completely new structure and function to meet the needs of more complex and diverse circuit designs. Summary of the invention

[0003] The present invention discloses a logic gate named Luwei array. It is composed of three power pins, two input interfaces and an output interface in a specific connection mode. The first power pin is connected in series with two PMOS tubes, the second power pin is connected in series with two systems consisting of two MOS tubes, the two systems are two parallel NMOS tubes and two parallel PMOS tubes, the third power pin is connected in series with two NMOS tubes, the first input interface is connected to the gate of a PMOS tube of the first power pin, the gate of an NMOS tube and a PMOS tube of the second power pin, and the gate of an NMOS tube of the third power pin, the second input interface is connected to the gate of a PMOS tube of the first power pin, the gate of an NMOS tube and a PMOS tube of the second power pin, and the gate of an NMOS tube of the third power pin, and the idle drains of the three power pin MOS tubes are connected together to form an output interface. This unique structure enables the logic gate to have a unique logical operation capability. Specifically, the connection between its power pins and different types of MOS tubes and the connection mode of the input interface and the gates of these MOS tubes determine its processing mode for the input signal, and finally outputs the corresponding result through the output interface. In addition, the circuit system constructed based on this logic gate, in which this logic gate serves as a key functional element, can realize complex logical operation functions and provide a new solution for electronic circuit design. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 Schematic diagram of the overall structure of the present invention DETAILED DESCRIPTION

[0005] In actual production, according to the semiconductor manufacturing process well known to those skilled in the art, the Lu-bit matrix logic gate is constructed according to the above connection relationship. For the power pin, a suitable voltage value is selected to meet the normal working conditions of the logic gate. For the MOS tube, selection and manufacturing are carried out according to the design rules. When assembling the circuit system, the Lu-bit matrix logic gate is connected with other components (such as auxiliary components such as resistors and capacitors) according to the designed logical function to achieve the expected circuit system function.

Claims

1. A logic gate based on a MOS circuit, characterized in that: It includes a power pin, an input interface, and an output interface. The power pin provides a logic level, the input interface receives an input signal, and the output interface outputs a logic operation result.

2. The logic gate based on MOS circuit according to claim 1, characterized in that: The power pin is connected in series with two PMOS tubes through the source and drain of the MOS tube, the second is connected in series with two PMOS tubes, and the third is connected in series with two NMOS tubes.

3. The logic gate based on MOS circuit according to claim 2, characterized in that: The two systems are one of two NMOS tubes connected in parallel, and the other of two PMOS tubes connected in parallel.

4. The logic gate based on MOS circuit according to claim 1, characterized in that: The input interface is first connected to the gate of a PMOS tube of the first power pin, an NMOS tube and a gate of a PMOS tube of the second power pin, and a gate of an NMOS tube of the third power pin, and the second input interface is connected to the gate of a PMOS tube of the first power pin, an NMOS tube and a gate of a PMOS tube of the second power pin, and a gate of an NMOS tube of the third power pin.

5. The logic gate based on MOS circuit according to claim 1, characterized in that: The output interface is connected to the drains of all idle MOS tubes.

6. A circuit system comprising the MOS circuit-based logic gate of claim 1, wherein the logic gate serves as a key functional element to perform a logic operation function in the system.

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