Boolean logic circuit based on memristor, control method and Boolean logic operation device

Abstract

The invention discloses a Boolean logic circuit based on a memristor, a control method and a Boolean logic operation device, and belongs to the technical field of microelectronic devices. The Boolean logic circuit comprises a memristor M1, a memristor M2, a first NMOS (N-channel Metal Oxide Semiconductor) tube, a second NMOS tube, a resistor and a voltage comparator; a voltage Vr is applied to the control end of the T1 and the control end of the T2 respectively, a grid voltage corresponding to a logic value a is applied to the grid of the first transistor, a grid voltage corresponding to a logic value c is applied to the grid of the second transistor, and the control end of the T3 is grounded, so that a corresponding Boolean logic operation result can be obtained at the output end of the voltage comparator. According to the invention, the resistance state characteristic of the memristor and the switching characteristic of the transistor are fully utilized, the values of the logic values a, b, c and d are set, any Boolean logic operation can be realized with fewer operation steps, and the realization of complete Boolean logic operation is supported. Meanwhile, the method is easy to cascade and has the advantage of parallel computing.

Description

Technical Field

[0001] The present invention belongs to the technical field of microelectronic devices, and more specifically, relates to a Boolean logic circuit, a control method and a Boolean logic operation device based on a memristor. Background Art

[0002] Traditional computers use the von Neumann architecture, where computing and storage functions are performed by processing units and storage units respectively. These two units are physically separated and communicate through a bus interconnection. In the context of the era of artificial intelligence and big data, the explosive growth of data has put forward higher requirements on the information processing capabilities of computers, and the computing bottleneck under the traditional structure has become increasingly prominent. On the one hand, the computing frequency of the processor is much faster than the access speed of the memory, resulting in a speed mismatch, namely the "storage wall" problem; on the other hand, data processing requires frequent transmission, reading and writing processes, which puts a great burden on the bus, and the data handling consumes a large proportion of power consumption and time. Storage and computing technology is considered to be one of the key ideas to solve the above problems. By integrating the data computing unit and the storage unit, in-situ logical computing and storage can be realized, thereby avoiding frequent data handling and greatly improving the computing parallelism.

[0003] Memristor is a memory device that can change the resistance of the resistive layer material to high and low resistance by applying an electric field. Due to its natural non-volatile characteristics and advantages such as small device size, fast read and write speed, low power consumption and compatibility with CMOS process, it can provide a hardware foundation for in-memory computing research. In digital logic, by mapping logical values ​​to physical quantities such as resistance and voltage, and configuring port voltage according to calculation needs, the memristor can be switched to the corresponding resistance state under specific conditions to complete the logic operation. However, when the existing memristor-based logic circuit realizes complete Boolean logic operations, for the more complex logic operations, it often requires a variety of basic Boolean logic combinations to realize them. For example, for the AND-NOT logic operation, it is necessary to first realize the AND logic operation through the AND control operation, and then negate the AND logic operation result through the non-control operation. This method requires more operation steps and is more complicated. Summary of the invention

[0004] In view of the above defects or improvement needs of the prior art, the present invention provides a Boolean logic circuit, a control method and a Boolean logic operation device based on a memristor, which are used to solve the technical problem that the prior art has relatively complex operations when implementing complete Boolean logic operations.

[0005] In order to achieve the above-mentioned object, in a first aspect, the present invention provides a Boolean logic circuit based on a memristor, comprising: a memristor M1, a memristor M2, a first NMOS transistor, a second NMOS transistor, a resistor and a voltage comparator; The positive electrode of the memristor M1 serves as the control terminal of T1, and the negative electrode is connected to the source of the first NMOS tube; the positive electrode of the memristor M2 serves as the control terminal of T2, and the negative electrode is connected to the source of the second NMOS tube; the drains of the first NMOS tube and the second NMOS tube are both connected to one end of the resistor, and the other end of the resistor serves as the control terminal of T3; the positive end of the voltage comparator is connected to the common node of the memristor M1, the memristor M2 and the resistor; the first transistor and the second transistor are the same; the memristor M1 and the memristor M2 are the same; the resistance value of the resistor is the low-resistance resistance value of the memristor; When performing Boolean logic operations, the memristor M1 is used to store the logic value b; the negative terminal of the voltage comparator is used to access the reference voltage V ref ; Memristor M2 is used to store logic value d; T1 control terminal and T2 control terminal are respectively used to access voltage V r ; The gate of the first transistor is used to access the gate voltage corresponding to the logic value a; the gate of the second transistor is used to access the gate voltage corresponding to the logic value c; the T3 control terminal is used to be grounded; the output terminal of the voltage comparator is used to output the corresponding Boolean logic operation result; Among them, V ref and V r Satisfy: (R H +R L )V r / (2R H +R L ) <V ref <2V r / 3; R H and R L are the high resistance and low resistance of the memristor respectively; the gate voltage corresponding to the logic value 0 is the voltage V less than the transistor turn-on voltage G , the gate voltage corresponding to the logic value 1 is greater than or equal to the transistor turn-on voltage V DD .

[0006] Further preferably, when the Boolean logic operation is a true logic operation, a is 1, c is 0 or 1, b is 1, and d is 0 or 1; When the Boolean logic operation is a false logic operation, a is 0, c is 0, b is 0 or 1, and d is 0 or 1; When the Boolean logic operation is a p logic operation, a is p, c is 0, b is 1, and d is 0 or 1; When the Boolean logic operation is q logic operation, a is 0, c is q, b is 0 or 1, and d is 1; When the Boolean logic operation is a non-p logic operation, a is a logical value non-p, c is 0, b is 1, and d is 0 or 1; When the Boolean logic operation is a non-q logic operation, a is 0, c is a logical value non-q, b is 0 or 1, and d is 1; When the Boolean logic operation is the AND operation of logical values ​​p and q, a is p, c is 0, b is q, and d is 0 or 1; When the Boolean logic operation is the AND-NOT logic operation of logical values ​​p and q, a is the logical value not p, c is the logical value not q, b is 1, and d is 1; When the Boolean logic operation is the OR operation of logical values ​​p and q, a is p, c is q, b is 1, and d is 1; When the Boolean logic operation is a logical value p, q or a not logical operation, a is a logical value not p, c is 0, b is a logical value not q, and d is 0 or 1; When the Boolean logic operation is a substantial implied logic operation of logical values ​​p and q, a is the logical value not p, c is q, b is 1, and d is 1; When the Boolean logic operation is a negative substantial implication logic operation of logical values ​​p and q, a is p, c is 0, b is logical value not q, and d is 0 or 1; When the Boolean logic operation is the inverse substantial implication logic operation of the logical values ​​p and q, a is p, c is the logical value not q, b is 1, and d is 1; When the Boolean logic operation is the negative substantive implied logic operation of the logical values ​​p and q, a is the logical value not p, c is 0, b is q, and d is 0 or 1; When the Boolean logic operation is the exclusive OR logic operation of logical values ​​p and q, a is the logical value not p, c is p, b is q, and d is the logical value not q; When the Boolean logic operation is the exclusive OR logic operation of logical values ​​p and q, a is p, c is the logical value not p, b is q, and d is the logical value not q.

[0007] In a second aspect, the present invention provides a control method for the above-mentioned Boolean logic circuit, comprising a Boolean logic operation: applying a voltage V to the control terminal T1 and the control terminal T2 respectively; r , applying a gate voltage corresponding to the logic value a to the gate of the first transistor, applying a gate voltage corresponding to the logic value c to the gate of the second transistor, grounding the control terminal of T3, and reading the corresponding Boolean logic operation result at the output terminal of the voltage comparator; The memristor M1 stores the logic value b, and the memristor M2 stores the logic value d. The negative terminal of the voltage comparator is connected to the reference voltage V ref ; V ref and V r Satisfy: (R H +R L )V r / (2R H +R L ) <V ref <2V r / 3; R H and R Lare the high resistance and low resistance of the memristor respectively; the gate voltage corresponding to the logic value 0 is the voltage V less than the transistor turn-on voltage G , the gate voltage corresponding to the logic value 1 is greater than or equal to the transistor turn-on voltage V DD .

[0008] Further preferably, the control method further comprises: an initialization memristor operation performed before the Boolean logic operation; The operation of initializing the memristor includes: writing a logic value b in the memristor M1 and writing a logic value d in the memristor M2; The corresponding logic value is written by setting the high and low resistance states of the memristor; the high resistance state of the memristor corresponds to a logic value of 0, and the low resistance state corresponds to a logic value of 1.

[0009] Further preferably, the step of writing the logic value b into the memristor M1 includes: When b is 0, the control terminal of T1 is grounded, the control terminal of T2 is set to a floating state, and a fixed voltage V is connected to the control terminal of T3. q , apply V to the gates of the first and second transistors DD , thereby writing the logic value b into the memristor M1; When b is 1, a fixed voltage V is connected to the control terminal of T1. p , set the T2 control terminal to a floating state, ground the T3 control terminal, and apply V to the gates of the first and second transistors. DD , thereby writing the logic value b into the memristor M1; Among them, V q >2|V reset |;V p >(R H +R L )V set / R H ; V reset V is the threshold value of the memristor changing from low resistance state to high resistance state; set is the threshold value of the memristor changing from high resistance state to low resistance state; R H is the high-resistance resistance of the memristor; R L is the low-resistance resistance value of the memristor.

[0010] Further preferably, the step of writing the logic value d into the memristor M2 comprises: When d is 0, the control terminal of T1 is set to a floating state, the control terminal of T2 is grounded, and a fixed voltage V is connected to the control terminal of T3. q , apply V to the gates of the first and second transistors DD , write the logic value d into the memristor M2; When d is 1, the control terminal of T1 is set to a floating state, and a fixed voltage V is connected to the control terminal of T2. p , ground the control terminal of T3, and apply V to the gates of the first and second transistors. DD , write the logic value d into the memristor M2; Among them, V q >2|V reset |;V p >(R H +R L )V set / R H ; V reset V is the threshold value of the memristor changing from low resistance state to high resistance state; set is the threshold value of the memristor changing from high resistance state to low resistance state; R H is the high-resistance resistance of the memristor; R L is the low-resistance resistance value of the memristor.

[0011] Further preferably, when the Boolean logic operation is a true logic operation, a is 1, c is 0 or 1, b is 1, and d is 0 or 1; When the Boolean logic operation is a false logic operation, a is 0, c is 0, b is 0 or 1, and d is 0 or 1; When the Boolean logic operation is a p logic operation, a is p, c is 0, b is 1, and d is 0 or 1; When the Boolean logic operation is q logic operation, a is 0, c is q, b is 0 or 1, and d is 1; When the Boolean logic operation is a non-p logic operation, a is a logical value non-p, c is 0, b is 1, and d is 0 or 1; When the Boolean logic operation is a non-q logic operation, a is 0, c is a logical value non-q, b is 0 or 1, and d is 1; When the Boolean logic operation is the AND operation of logical values ​​p and q, a is p, c is 0, b is q, and d is 0 or 1; When the Boolean logic operation is the AND-NOT logic operation of logical values ​​p and q, a is the logical value not p, c is the logical value not q, b is 1, and d is 1; When the Boolean logic operation is the OR operation of logical values ​​p and q, a is p, c is q, b is 1, and d is 1; When the Boolean logic operation is a logical value p, q or a not logical operation, a is a logical value not p, c is 0, b is a logical value not q, and d is 0 or 1; When the Boolean logic operation is a substantial implied logic operation of logical values ​​p and q, a is the logical value not p, c is q, b is 1, and d is 1; When the Boolean logic operation is a negative substantial implication logic operation of logical values ​​p and q, a is p, c is 0, b is logical value not q, and d is 0 or 1; When the Boolean logic operation is the inverse substantial implication logic operation of the logical values ​​p and q, a is p, c is the logical value not q, b is 1, and d is 1; When the Boolean logic operation is the negative substantive implied logic operation of the logical values ​​p and q, a is the logical value not p, c is 0, b is q, and d is 0 or 1; When the Boolean logic operation is the exclusive OR logic operation of logical values ​​p and q, a is the logical value not p, c is p, b is q, and d is the logical value not q; When the Boolean logic operation is the exclusive OR logic operation of logical values ​​p and q, a is p, c is the logical value not p, b is q, and d is the logical value not q.

[0012] In a third aspect, the present invention provides a Boolean logic operation device, comprising: a controller and the Boolean logic circuit provided in the first aspect of the present invention; The controller is used to execute the control method provided in the second aspect of the present invention.

[0013] In a fourth aspect, the present invention provides a control system, comprising: a memory and a processor, wherein the memory stores a computer program, and the processor executes the control method provided in the second aspect of the present invention when executing the computer program.

[0014] In a fifth aspect, the present invention further provides a computer-readable storage medium, which includes a stored computer program, wherein when the computer program is executed by a processor, the device where the storage medium is located is controlled to execute the control method provided in the second aspect of the present invention.

[0015] In a sixth aspect, the invention further provides a computer program product, comprising a computer program / instruction, which, when executed by a processor, implements the control method provided in the second aspect of the invention.

[0016] In general, the above technical solutions conceived by the present invention can achieve the following beneficial effects: 1. The present invention provides a memristor-based Boolean logic circuit, comprising a memristor M1, a memristor M2, a first NMOS transistor, a second NMOS transistor, a resistor and a voltage comparator; by applying a voltage V to the control terminal T1 and the control terminal T2 respectively r , a gate voltage corresponding to the logic value a is applied to the gate of the first transistor, a gate voltage corresponding to the logic value c is applied to the gate of the second transistor, and the control terminal of T3 is grounded, and the corresponding Boolean logic operation result can be obtained at the output terminal of the voltage comparator; wherein, V ref and V r Satisfy: (R H +R L )V r / (2RH +R L ) <V ref <2V r / 3, ensuring the correct execution of logical operations and the accuracy of reading results. The present invention makes full use of the resistance characteristics of the memristor and the switching characteristics of the transistor. By setting the values ​​of the logic values ​​a, b, c, and d, any Boolean logic operation can be realized with fewer operation steps. The operation is relatively simple and supports the realization of complete Boolean logic operations.

[0017] 2. In the Boolean logic circuit provided by the present invention, during the operation of logic calculation, the resistance states of the memristors M1 and M2 do not change, and the entire operation process is non-destructive, which is beneficial to protecting the integrity of input information.

[0018] 3. The Boolean logic circuit provided by the present invention requires fewer operation steps, has a faster operation speed, lower operation power consumption, and has a simplified peripheral circuit configuration. It is suitable for application in memory computing and the design of digital logic units. It is easy to cascade, has significant parallel computing advantages, and supports large-scale parallel computing. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A result schematic diagram of a memristor-based Boolean logic circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0021] In order to achieve the above objectives, in a first aspect, the present invention provides a Boolean logic circuit based on a memristor, such as Figure 1 As shown, it includes: a memristor M1, a memristor M2, a first NMOS tube N1, a second NMOS tube N2, a resistor R and a voltage comparator SA; The positive electrode of memristor M1 is used as the control terminal of T1, and the negative electrode is connected to the source of the first NMOS tube; the positive electrode of memristor M2 is used as the control terminal of T2, and the negative electrode is connected to the source of the second NMOS tube; the gate of the first NMOS tube is connected to the word line WL1; the gate of the second NMOS tube is connected to the word line WL2; the drains of the first NMOS tube and the second NMOS tube are both connected to one end of the resistor, and the other end of the resistor is used as the control terminal of T3; the positive end of the voltage comparator is connected to the common node of the memristor M1, the memristor M2 and the resistor, and the negative end is connected to the reference voltage V ref; The first transistor and the second transistor are the same; The memristor M1 and the memristor M2 are the same; The resistance value of the resistor is the low resistance value of the memristor; When performing Boolean logic operations, the memristor M1 is used to store the logic value b; the negative terminal of the voltage comparator is used to access the reference voltage V ref ; Memristor M2 is used to store logic value d; T1 control terminal and T2 control terminal are respectively used to access voltage V r ; The gate of the first transistor is used to access the gate voltage corresponding to the logic value a; the gate of the second transistor is used to access the gate voltage corresponding to the logic value c; the T3 control terminal is used for grounding; the output terminal of the voltage comparator is used to output the corresponding Boolean logic operation result.

[0022] The memristor has two resistance states, namely high resistance state and low resistance state, and the corresponding resistance values ​​are R H and R L ; Among them, the high resistance state of the memristor corresponds to the logic value 0, and the low resistance state of the memristor corresponds to the logic value 1. The forward voltage value applied across the memristor is greater than V set When |V is applied to both ends of the memristor, the memristor can be changed from a high-resistance state to a low-resistance state (i.e., the Set process of the memristor). reset | can make the memristor change from a high resistance state to a low resistance state (i.e., the reset process of the memristor). Specifically, in an optional implementation, the V set and V reset The average values ​​are 0.6V and -1.2V respectively, and the high impedance value R H =100kΩ, low resistance value R L =1kΩ, resistance value R=1kΩ.

[0023] The Boolean logic circuit provided by the present invention can be regarded as a combination of two 1T1R units. By defining the input of this structure, all Boolean logic can be represented. It is a complete reconfigurable logic set. In an optional implementation, the input and output definitions of the Boolean logic circuit are shown in Table 1: It should be noted that the gate voltage corresponding to the logic value 0 is a voltage V less than the transistor turn-on voltage. G , the gate voltage corresponding to the logic value 1 is greater than or equal to the transistor turn-on voltage V DD When a voltage V is applied to the gate of the transistor G When the transistor is not conducting, the gate voltage V DD When the transistor is turned on. Normally, V G0V, corresponding to the operation of grounding the gate of the transistor. For the input logic variable p or q, in positive logic (i.e., Boolean logic operation does not involve the negation of p or q), when the gate voltage (WL1 or WL2) of the NMOS transistor (N1 or N2) is grounded, it represents the logic value "0"; when the gate voltage (WL1 or WL2) of the NMOS transistor (N1 or N2) is connected to a fixed voltage V DD When the memristor (M1 or M2) is in a high resistance state, it represents a logic value "1"; when the memristor (M1 or M2) is in a high resistance state, it represents a logic value "0"; when the memristor (M1 or M2) is in a low resistance state, it represents a logic value "1". For the input logic variable p or q, when the inverse logic (involving the inversion of p or q) is performed, the gate voltage (WL1 or WL2) of the NMOS transistor (N1 or N2) is grounded, it represents a logic value "1"; the gate voltage (WL1 or WL2) of the NMOS transistor (N1 or N2) is connected to a fixed voltage V DD When the resistance state of the memristor (M1 or M2) is high resistance, it represents a logic value of "1"; when the resistance state of the memristor (M1 or M2) is low resistance, it represents a logic value of "0". For the output variable V o , V o When it is low level, it represents the output logic value "0"; V o When it is at a high level, it represents the output logic value "1".

[0024] The positive terminal of the voltage comparator is connected to the voltage V at the common node of the memristor M1, memristor M2 and resistor cond V will change according to the resistance of memristor M1 and memristor M2. In order to ensure the correct execution of the logic operation and read the result correctly, V ref and V r Satisfies the following relationship: (R H +R L )V r / (2R H +R L ) <V ref <2V r / 3. Preferably, in an optional implementation, the switching ratio of the memristor is greater than or equal to 100. It should be noted that the switching ratio of the memristor directly affects the resistance state change window of the memristor in the output column. The larger the switching ratio, the larger the resistance state change window of the memristor in the output column. When the switching ratio is greater than or equal to 100, the memristor in the output column can realize the resistance state change more accurately, thereby further improving the accuracy of the calculation. At this time, the above relationship can be further simplified to: 101V r / 201 <V ref <2V r / 3.

[0025] The Boolean logic circuit provided by the present invention is a four-input logic circuit, and the output result is the result of the AND or combination of the four inputs, and the expression is: o=ab+cd. By setting the values ​​of the logic values ​​a, b, c, and d, the four variables can be reduced in dimension to realize complete Boolean logic operations.

[0026] Specifically, in an optional implementation, when the Boolean logic operation is a true logic operation, a is 1, c is 0 or 1, b is 1, and d is 0 or 1; When the Boolean logic operation is a false logic operation, a is 0, c is 0, b is 0 or 1, and d is 0 or 1; When the Boolean logic operation is a p logic operation, a is p, c is 0, b is 1, and d is 0 or 1; When the Boolean logic operation is q logic operation, a is 0, c is q, b is 0 or 1, and d is 1; When the Boolean logic operation is a non-p logic operation, a is a logical value non-p, c is 0, b is 1, and d is 0 or 1; When the Boolean logic operation is a non-q logic operation, a is 0, c is a logical value non-q, b is 0 or 1, and d is 1; When the Boolean logic operation is the AND operation of logical values ​​p and q, a is p, c is 0, b is q, and d is 0 or 1; When the Boolean logic operation is the AND-NOT logic operation of logical values ​​p and q, a is the logical value not p, c is the logical value not q, b is 1, and d is 1; When the Boolean logic operation is the OR operation of logical values ​​p and q, a is p, c is q, b is 1, and d is 1; When the Boolean logic operation is a logical value p, q or a not logical operation, a is a logical value not p, c is 0, b is a logical value not q, and d is 0 or 1; When the Boolean logic operation is a substantial implied logic operation of logical values ​​p and q, a is the logical value not p, c is q, b is 1, and d is 1; When the Boolean logic operation is a negative substantial implication logic operation of logical values ​​p and q, a is p, c is 0, b is logical value not q, and d is 0 or 1; When the Boolean logic operation is the inverse substantial implication logic operation of the logical values ​​p and q, a is p, c is the logical value not q, b is 1, and d is 1; When the Boolean logic operation is the negative substantive implied logic operation of the logical values ​​p and q, a is the logical value not p, c is 0, b is q, and d is 0 or 1; When the Boolean logic operation is the exclusive OR logic operation of logical values ​​p and q, a is the logical value not p, c is p, b is q, and d is the logical value not q; When the Boolean logic operation is the exclusive OR logic operation of logical values ​​p and q, a is p, c is the logical value not p, b is q, and d is the logical value not q.

[0027] In a second aspect, the present invention provides a control method for the above-mentioned Boolean logic circuit, comprising: Initialization of the memristor operation performed before the actual Boolean logic operation: A logic value b is written into the memristor M1 so that the memristor M1 stores the logic value b; a logic value d is written into the memristor M2 so that the memristor M2 stores the logic value d. In an optional implementation, the corresponding logic value is written by setting the high and low resistance states of the memristor; wherein the high resistance state of the memristor corresponds to the logic value 0, and the low resistance state corresponds to the logic value 1.

[0028] Specifically, in an optional implementation manner, the above-mentioned writing of the logic value b into the memristor M1 includes: When b is 0, the control terminal of T1 is grounded, the control terminal of T2 is set to a floating state, and a fixed voltage V is connected to the control terminal of T3. q A fixed voltage V for selecting the transistor is applied to the gates of the first transistor and the second transistor. DD At this time, the memristor M1 implements the Reset process and becomes a high-resistance state, thereby writing a logic value of 0 into the memristor M1.

[0029] When b is 1, a fixed voltage V is connected to the control terminal of T1. p , set the T2 control terminal to a floating state, ground the T3 control terminal, and apply a fixed voltage V for selecting the transistor to the gate of the first transistor and the second transistor. DD At this time, the memristor M1 implements the set process and changes to a low resistance state, thereby writing a logic value 1 into the memristor M1.

[0030] In an optional implementation manner, writing the logic value d in the memristor M2 includes: When d is 0, the control terminal of T1 is set to a floating state, the control terminal of T2 is grounded, and a fixed voltage V is connected to the control terminal of T3. q A fixed voltage V for selecting the transistor is applied to the gates of the first transistor and the second transistor. DD At this time, the memristor M2 implements the Reset process, becomes a high-resistance state, and writes a logic value of 0 into the memristor M2.

[0031] When d is 1, the control terminal of T1 is set to a floating state, and a fixed voltage V is connected to the control terminal of T2. p , ground the control terminal of T3, and apply a fixed voltage V for selecting the transistor to the gate of the first transistor and the second transistor. DD At this time, the memristor M2 implements the set process, changes to a low resistance state, and writes a logic value 1 into the memristor M2.

[0032] It should be noted that in order to ensure that the input information on the memristor M1 and the memristor M2 can be written normally, it is necessary to meet the following conditions: V q >2|V reset |;V p >(R H +R L )V set / R H ; Among them, V reset V is the threshold value of the memristor changing from low resistance state to high resistance state; set is the threshold value of the memristor changing from high resistance state to low resistance state; R H is the high-resistance resistance of the memristor; R L is the low-resistance resistance value of the memristor.

[0033] Preferably, in an optional implementation manner, according to the above limitation of the operating voltage value range, combined with the actual use of the memristor V set With V reset The relationship between V p =1.2V set ; V q =2.2|V reset |;V ref =0.6V r ; V r =0.4V.

[0034] Actual Boolean logic operations: Apply voltage V to the control terminal of T1 and the control terminal of T2 respectively. r A gate voltage corresponding to the logic value a is applied to the gate of the first transistor, a gate voltage corresponding to the logic value c is applied to the gate of the second transistor, the control terminal of T3 is grounded, and the corresponding Boolean logic operation result is read at the output terminal of the voltage comparator.

[0035] Among them, the negative terminal of the voltage comparator is connected to the reference voltage V ref ; V ref and V r Satisfy: (R H +R L )V r / (2R H +R L ) <V ref <2V r / 3; R H and R L are the high resistance and low resistance of the memristor respectively; the gate voltage corresponding to the logic value 0 is the voltage V less than the transistor turn-on voltage G , the gate voltage corresponding to the logic value 1 is greater than or equal to the transistor turn-on voltage V DD .

[0036] The expression of the Boolean logic operation result in the present invention is: o=ab+cd, and the complete Boolean logic operation can be realized by setting the values ​​of the logic values ​​a, b, c, and d. Specifically, a reference voltage V is applied to the negative terminal of the voltage comparator. ref , apply voltage V to the control terminal of T1 and the control terminal of T2 respectively r , the control terminal of T3 is grounded. When a=0, c=0, the gates of NMOS transistors N1 and N2 are both connected to a fixed voltage V G When a=1, c=0, the gate of NMOS transistor N1 is connected to a fixed voltage V DD , the gate of NMOS transistor N2 is connected to a fixed voltage V G When a=0, c=1, the gate of NMOS transistor N1 is connected to a fixed voltage V G , the gate of NMOS transistor N2 is connected to a fixed voltage V DD When a=1, c=1, the gates of NMOS transistors N1 and NMOS transistors N2 are both connected to a fixed voltage V DD The corresponding Boolean logic operation result is obtained at the output end of the voltage comparator.

[0037] The specific voltage configuration is shown in Table 2: The related technical solution is the same as the Boolean logic circuit provided in the first aspect of the present invention, and will not be described in detail here.

[0038] In order to make the technical solution and advantages of the present invention more clear, in an optional implementation, a table of operations for implementing 16 Boolean logics in one step based on a four-input logic scheme of a memristor is provided as shown in Table 3. In this implementation, V G is a voltage with an amplitude of 0, corresponding to the operation of grounding the gate of the transistor.

[0039] The specific operations are as follows: When the Boolean logic operation is a true logic operation, the logical expression is 1. At this time, a=1, c=0 or 1, b=1, and d=0 or 1. Specifically, before performing the Boolean logic operation, the memristor M1 is pre-set to a low resistance state, and the memristor M2 is pre-set to a high resistance state or a low resistance state, which is not limited here. When performing the Boolean logic operation, a voltage V is applied to the control terminal T1 and the control terminal T2 respectively. r , ground the control terminal of T3, and apply a fixed voltage V to the gate of the first transistor DD , a voltage with an amplitude of 0 or a fixed voltage V is applied to the gate of the second transistor DD , no limitation is made here. At this time, the current flowing through the fixed resistor R is large, Vcond >V ref , the voltage output by the voltage comparator is a high level, that is, the result of the logic operation is always 1, realizing true logic.

[0040] When the Boolean logic operation is a false logic operation, the logic expression is 0. At this time, a is 0, c is 0, b is 0 or 1, and d is 0 or 1. Specifically, before performing the Boolean logic operation, the memristor M1 is pre-set to a high resistance state or a low resistance state, and the memristor M2 is pre-set to a high resistance state or a low resistance state, which is not limited here. When performing the Boolean logic operation, a voltage V is applied to the control terminal T1 and the control terminal T2 respectively. r , ground the control terminal of T3, and ground the gates of the first transistor and the second transistor. At this time, the current flowing through the fixed resistor R is small, and V cond <V ref , the voltage output by the voltage comparator is a low level, that is, the result of the logic operation is always 0, realizing false logic.

[0041] When the Boolean logic operation is a p logic operation, the logic expression is p. At this time, a is p, c is 0, b is 1, and d is 0 or 1. Specifically, before performing the Boolean logic operation, the memristor M1 is pre-set to a low resistance state, and the memristor M2 is pre-set to a high resistance state or a low resistance state, which is not limited here. When performing the Boolean logic operation, a voltage V is applied to the control terminal T1 and the control terminal T2 respectively. r , the control terminal of T3 is grounded, and when p is 0, the gate of the first transistor is grounded, and when p is 1, a fixed voltage V is applied to the gate of the first transistor DD , the gate of the second transistor is grounded; at this time, the current flowing through the fixed resistor R changes according to the input logic value p, thereby affecting V cond With V ref When p is 0, V cond <V ref , the voltage comparator outputs a low level voltage, that is, the logical operation result is 0; when p is 1, V cond >V ref When , the voltage comparator outputs a high level voltage, that is, the logic operation result is 1. Thus, p logic operation is realized, and the Boolean logic operation result is p.

[0042] When the Boolean logic operation is q logic operation, the logic expression is q, at this time, a is 0, c is q, b is 0 or 1, and d is 1. Specifically, before the Boolean logic operation is performed, the memristor M1 is pre-set to a high resistance state or a low resistance state, which is not limited here; the memristor M2 is pre-set to a low resistance state. When performing the Boolean logic operation, a voltage V is applied to the control terminal T1 and the control terminal T2 respectively. r, ground the control terminal of T3, ground the gate of the first transistor, and ground the gate of the second transistor when q is 0, and apply a fixed voltage V to the gate of the second transistor when q is 1 DD At this time, the current flowing through the fixed resistor R changes according to the input logic value q, thus affecting V cond With V ref When q is 0, V cond <V ref , the voltage comparator outputs a low level voltage, that is, the logical operation result is 0; when q is 1, V cond >V ref When , the voltage comparator outputs a high level voltage, that is, the logic operation result is 1; thereby, q logic operation is realized, and the Boolean logic operation result is q.

[0043] When the Boolean logic operation is a non-p logic operation, the logical expression is , at this time, a is a logical value not p, c is 0, b is 1, and d is 0 or 1. Specifically, before performing the Boolean logic operation, the memristor M1 is pre-set to a low resistance state, and the memristor M2 is pre-set to a high resistance state or a low resistance state, which is not limited here. When performing the Boolean logic operation, a voltage V is applied to the control terminal T1 and the control terminal T2 respectively. r , ground the control terminal of T3, and apply a fixed voltage V to the gate of the first transistor when p is 0 (not p is 1) DD , when p is 1 (not p is 0), the gate of the first transistor is grounded, and the gate of the second transistor is grounded; at this time, the current flowing through the fixed resistor R changes according to the change of the input logic value p, thereby affecting V cond With V ref When p is 1, V cond <V ref , the voltage comparator outputs a low level voltage, that is, the logical operation result is 0; when p is 0, V cond >V ref When , the voltage comparator outputs a high level voltage, that is, the logical operation result is 1. This implements the non-p logic operation, and the Boolean logic operation result is .

[0044] When the Boolean logic operation is a non-q logic operation, the logical expression is , at this time, a is 0, c is a logical value not q, b is 0 or 1, and d is 1. Specifically, before performing the Boolean logic operation, the memristor M1 is pre-set to a high resistance state or a low resistance state, which is not limited here; the memristor M2 is pre-set to a low resistance state. When performing the Boolean logic operation, a voltage V is applied to the control terminal T1 and the control terminal T2 respectively. r, ground the control terminal of T3, ground the gate of the first transistor, and apply a fixed voltage V to the gate of the second transistor when q is 0 (not q is 1) DD , when p is 1 (not p is 0), the gate of the second transistor is grounded. At this time, the current flowing through the fixed resistor R changes according to the input logic value q, thereby affecting V cond With V ref When q is 1, V cond <V ref , the voltage comparator outputs a low level voltage, that is, the logical operation result is 0; when q is 0, V cond >V ref When , the voltage comparator outputs a high level voltage, that is, the logical operation result is 1. This implements the non-q logic operation, and the Boolean logic operation result is .

[0045] When the Boolean logic operation is the AND logic operation of the logic values ​​p and q, the logic expression is pq. At this time, a is p, c is 0, b is q, and d is 0 or 1. Specifically, before performing the Boolean logic operation, the memristor M1 is pre-set to the resistance state corresponding to the logic value q. When q is 0, the memristor M1 is pre-set to the high resistance state. When q is 1, the memristor M1 is pre-set to the low resistance state. The memristor M2 is pre-set to the high resistance state or the low resistance state, which is not limited here. When performing the Boolean logic operation, a voltage V is applied to the control terminal T1 and the control terminal T2 respectively. r , the control terminal of T3 is grounded, and when p is 0, the gate of the first transistor is grounded, and when p is 1, a fixed voltage V is applied to the gate of the first transistor DD , the gate of the second transistor is grounded; at this time, the current flowing through the fixed resistor R changes according to the input logic value pq, thereby affecting V cond With V ref When pq is 0, V cond <V ref , the voltage comparator outputs a low level voltage, that is, the logical operation result is 0; when pq is 1, V cond >V ref When , the voltage comparator outputs a high level voltage, that is, the logic operation result is 1. Thus, the AND logic operation is realized, and the Boolean logic operation result is pq.

[0046] When the Boolean logic operation is the AND-NOT logic operation of logical values ​​p and q, the logical expression is , at this time, a is a logic value not p, c is a logic value not q, b is 1, and d is 1. Specifically, before performing the Boolean logic operation, the memristor M1 and the memristor M2 are both set to a low resistance state in advance. When performing the Boolean logic operation, a voltage V is applied to the control terminal T1 and the control terminal T2 respectively.r , ground the control terminal of T3, and when p is 1 (not p is 0), ground the gate of the first transistor, and when p is 0 (not p is 1), apply a fixed voltage V to the gate of the first transistor. DD , when q is 1 (not q is 0), the gate of the second transistor is grounded, and when q is 0 (not q is 1), a fixed voltage V is applied to the gate of the second transistor DD ; At this time, the current flowing through the fixed resistor R depends on the input logic value changes with the change of V cond With V ref The size relationship is When V cond <V ref , the voltage output by the voltage comparator is low level, that is, the result of the logic operation is 0; when When V cond >V ref When , the voltage comparator outputs a high level voltage, that is, the logical operation result is 1. This realizes the AND-NOT logic operation, and the Boolean logic operation result is .

[0047] When the Boolean logic operation is the OR operation of the logical values ​​p and q, the logical expression is p+q. At this time, a is p, c is q, b is 1, and d is 1. Specifically, before the Boolean logic operation is performed, the memristor M1 and the memristor M2 are both set to a low resistance state in advance. When the Boolean logic operation is performed, a voltage V is applied to the control terminal T1 and the control terminal T2 respectively. r , the control terminal of T3 is grounded, and when p is 0, the gate of the first transistor is grounded, and when p is 1, a fixed voltage V is applied to the gate of the first transistor DD When q is 0, the gate of the second transistor is grounded, and when q is 1, a fixed voltage V is applied to the gate of the second transistor. DD ; At this time, the current flowing through the fixed resistor R changes according to the input logic value p+q, thus affecting V cond With V ref When p+q is 0, V cond <V ref , the voltage comparator outputs a low level voltage, that is, the logic operation result is 0; when a+b is 1, V cond >V ref When , the voltage comparator outputs a high level voltage, that is, the logic operation result is 1. Thus, the OR logic operation is realized, and the Boolean logic operation result is p+q.

[0048] When the Boolean logic operation is the OR or NOT operation of the logical values ​​p and q, the logical expression is , at this time, a is a logic value not p, c is 0, b is a logic value not q, and d is 0 or 1. Specifically, before performing the Boolean logic operation, the memristor M1 is pre-set to the resistance state corresponding to the logic value not q. When q is 1 (not q is 0), the memristor M1 is pre-set to a high resistance state. When q is 0 (not q is 1), the memristor M1 is pre-set to a low resistance state. The memristor M2 is pre-set to a high resistance state or a low resistance state, which is not limited here. When performing the Boolean logic operation, a voltage V is applied to the control terminal T1 and the control terminal T2 respectively. r , ground the control terminal of T3, and when p is 1 (not p is 0), ground the gate of the first transistor, and when p is 0 (not p is 1), apply a fixed voltage V to the gate of the first transistor. DD , the gate of the second transistor is grounded; at this time, the current flowing through the fixed resistor R is based on the input logic value. changes with the change of V cond With V ref The size relationship is When V cond <V ref , the voltage output by the voltage comparator is low level, that is, the result of the logic operation is 0; when When V cond >V ref When , the voltage comparator outputs a high level voltage, that is, the logical operation result is 1. This realizes the NOR logic operation, and the Boolean logic operation result is .

[0049] When the Boolean logic operation is the substantial implied logic operation of the logical values ​​p and q, the logical expression is , at this time, a is a logical value not p, c is q, b is 1, and d is 1. Specifically, before performing the Boolean logic operation, the memristor M1 and the memristor M2 are both set to a low resistance state in advance. When performing the Boolean logic operation, a voltage V is applied to the control terminal T1 and the control terminal T2 respectively. r , ground the control terminal of T3, and when p is 1 (not p is 0), ground the gate of the first transistor, and when p is 0 (not p is 1), apply a fixed voltage V to the gate of the first transistor. DD When q is 0, the gate of the second transistor is grounded, and when q is 1, a fixed voltage V is applied to the gate of the second transistor. DD ; At this time, the current flowing through the fixed resistor R depends on the input logic value changes with the change of V cond With V ref The size relationship is When V cond <V ref , the voltage output by the voltage comparator is low level, that is, the result of the logic operation is 0; when When V cond >V ref When , the voltage comparator outputs a high level voltage, that is, the result of the logic operation is 1. This realizes the substantial implicit logic operation, and the result of the Boolean logic operation is .

[0050] When the Boolean logic operation is the negative substantial implication logic operation of the logical values ​​p and q, the logical expression is , at this time, a is p, c is 0, b is the logic value non-q, and d is 0 or 1. Specifically, before performing the Boolean logic operation, the memristor M1 is pre-set to the resistance state corresponding to the logic value non-q. When q is 1 (non-q is 0), the memristor M1 is pre-set to the high resistance state, and when q is 0 (non-q is 1), the memristor M1 is pre-set to the low resistance state; the memristor M2 is pre-set to the high resistance state or the low resistance state, which is not limited here. When performing the Boolean logic operation, the voltage V is applied to the control terminal T1 and the control terminal T2 respectively. r , the control terminal of T3 is grounded, and when p is 0, the gate of the first transistor is grounded, and when p is 1, a fixed voltage V is applied to the gate of the first transistor DD , the gate of the second transistor is grounded; at this time, the current flowing through the fixed resistor R is based on the input logic value. changes with the change of V cond With V ref The size relationship is When V cond <V ref , the voltage output by the voltage comparator is low level, that is, the result of the logic operation is 0; when When V cond >V ref When , the voltage comparator outputs a high level voltage, that is, the logical operation result is 1. This realizes the negative substantive logical operation, and the Boolean logic operation result is .

[0051] When the Boolean logic operation is the inverse substantial implication logic operation of the logical values ​​p and q, the logical expression is , at this time, a is p, c is a logical value not q, b is 1, and d is 1. Specifically, before performing the Boolean logic operation, the memristor M1 and the memristor M2 are both set to a low resistance state in advance. When performing the Boolean logic operation, a voltage V is applied to the control terminal T1 and the control terminal T2 respectively. r , the control terminal of T3 is grounded, and when p is 0, the gate of the first transistor is grounded, and when p is 1, a fixed voltage V is applied to the gate of the first transistor DD , when q is 1 (not q is 0), the gate of the second transistor is grounded, and when q is 0 (not q is 1), a fixed voltage V is applied to the gate of the second transistorDD ; At this time, the current flowing through the fixed resistor R depends on the input logic value changes with the change of V cond With V ref The size relationship is When V cond <V ref , the voltage output by the voltage comparator is low level, that is, the result of the logic operation is 0; when When V cond >V ref When , the voltage comparator outputs a high level voltage, that is, the result of the logic operation is 1. This realizes the inverse substantive logic operation, and the result of the Boolean logic operation is .

[0052] When the Boolean logic operation is the inverse of the logical value p, q, the logical expression is , at this time, a is a logic value not p, c is 0, b is q, and d is 0 or 1. Specifically, before performing the Boolean logic operation, the memristor M1 is pre-set to the resistance state corresponding to the logic value q. When q is 0, the memristor M1 is pre-set to a high resistance state, and when q is 1, the memristor M1 is pre-set to a low resistance state; the memristor M2 is pre-set to a high resistance state or a low resistance state, which is not limited here. When performing the Boolean logic operation, a voltage V is applied to the control terminal T1 and the control terminal T2 respectively. r , ground the control terminal of T3, and when p is 1 (not p is 0), ground the gate of the first transistor, and when p is 0 (not p is 1), apply a fixed voltage V to the gate of the first transistor. DD , the gate of the second transistor is grounded; at this time, the current flowing through the fixed resistor R is based on the input logic value. changes with the change of V cond With V ref The size relationship is When V cond <V ref , the voltage output by the voltage comparator is low level, that is, the result of the logic operation is 0; when When V cond >V ref When , the voltage comparator outputs a high level voltage, that is, the result of the logic operation is 1. This realizes the negative real implicit logic operation, and the Boolean logic operation result is .

[0053] When the Boolean logic operation is the exclusive OR logic operation of the logical values ​​p and q, the logical expression is , at this time, a is a logic value not p, c is p, b is q, and d is a logic value not q. Specifically, before performing a Boolean logic operation, the memristor M1 is pre-set to a resistance state corresponding to the logic value q. When q is 0, the memristor M1 is pre-set to a high resistance state, and when q is 1, the memristor M1 is pre-set to a low resistance state; the memristor M2 is pre-set to a resistance state corresponding to the logic value not q. When q is 1 (not q is 0), the memristor M2 is pre-set to a high resistance state, and when q is 0 (not q is 1), the memristor M2 is pre-set to a low resistance state. When performing a Boolean logic operation, a voltage V is applied to the control terminal T1 and the control terminal T2 respectively. r , ground the control terminal of T3, and when p is 1 (not p is 0), ground the gate of the first transistor, and when p is 0 (not p is 1), apply a fixed voltage V to the gate of the first transistor. DD When p is 0, the gate of the second transistor is grounded, and when p is 1, a fixed voltage V is applied to the gate of the second transistor. DD ; At this time, the current flowing through the fixed resistor R depends on the input logic value changes with the change of V cond With V ref The size relationship is When V cond <V ref , the voltage output by the voltage comparator is low level, that is, the result of the logic operation is 0; when When V cond >V ref When , the voltage comparator outputs a high level voltage, that is, the logical operation result is 1. This implements the XOR logic operation, and the Boolean logic operation result is .

[0054] When the Boolean logic operation is the exclusive OR logic operation of logical values ​​p and q, the logical expression is , at this time, a is p, c is the logical value not p, b is q, and d is the logical value not q. Specifically, before performing the Boolean logic operation, the memristor M1 is pre-set to the resistance state corresponding to the logical value q. When q is 0, the memristor M1 is pre-set to the high resistance state, and when q is 1, the memristor M1 is pre-set to the low resistance state; the memristor M2 is pre-set to the resistance state corresponding to the logical value not q. When q is 1 (not q is 0), the memristor M2 is pre-set to the high resistance state, and when q is 0 (not q is 1), the memristor M2 is pre-set to the low resistance state. When performing the Boolean logic operation, the voltage V is applied to the control terminal T1 and the control terminal T2 respectively. r , the control terminal of T3 is grounded, and when p is 0, the gate of the first transistor is grounded, and when p is 1, a fixed voltage V is applied to the gate of the first transistor DD, and when p is 1 (not p is 0), the gate of the second transistor is grounded, and when p is 0 (not p is 1), a fixed voltage V is applied to the gate of the second transistor DD ; At this time, the current flowing through the fixed resistor R depends on the input logic value changes with the change of V cond With V ref The size relationship is When V cond <V ref , the voltage output by the voltage comparator is low level, that is, the result of the logic operation is 0; when When V cond >V ref When , the voltage comparator outputs a high level voltage, that is, the logical operation result is 1. This implements the exclusive OR logic operation, and the Boolean logic operation result is .

[0055] The number of devices used and the number of operation steps are relatively small, the circuit structure is simple, and in more complex application scenarios, the input variables that need to be retained can be flexibly selected for logical cascading, which can lay the foundation for complex logical operations.

[0056] In a third aspect, the present invention provides a Boolean logic operation device, comprising: a controller and the Boolean logic circuit provided in the first aspect of the present invention; The controller is used to execute the control method provided in the second aspect of the present invention.

[0057] The related technical solutions are the same as the Boolean logic circuit provided in the first aspect of the present invention and the control method provided in the second aspect of the present invention, and will not be described in detail here.

[0058] In a fourth aspect, the present invention provides a control system, comprising: a memory and a processor, wherein the memory stores a computer program, and the processor executes the control method provided in the second aspect of the present invention when executing the computer program.

[0059] The related technical solution is the same as the control method provided in the second aspect of the present invention, and will not be described in detail here.

[0060] In a fifth aspect, the present invention further provides a computer-readable storage medium, which includes a stored computer program, wherein when the computer program is executed by a processor, the device where the storage medium is located is controlled to execute the control method provided in the second aspect of the present invention.

[0061] The related technical solution is the same as the control method provided in the second aspect of the present invention, and will not be described in detail here.

[0062] In a sixth aspect, the invention further provides a computer program product, comprising a computer program / instruction, which, when executed by a processor, implements the control method provided in the second aspect of the invention.

[0063] The related technical solution is the same as the control method provided in the second aspect of the present invention, and will not be described in detail here.

[0064] In summary, the present invention provides a method for implementing a four-input reconfigurable logic based on a memristor, which can complete any one of 16 complete Boolean logics in two steps under a one-time operation scheme, and is easy to cascade. At the same time, the method can realize large-scale parallel computing in a 1T1R array, and has great advantages in the process of realizing digital logic components such as full adders.

[0065] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A Boolean logic circuit based on a memristor, characterized in that: include: Memristor M1, memristor M2, a first NMOS tube, a second NMOS tube, a resistor and a voltage comparator; The positive electrode of the memristor M1 serves as the control terminal of T1, and the negative electrode is connected to the source of the first NMOS tube; the positive electrode of the memristor M2 serves as the control terminal of T2, and the negative electrode is connected to the source of the second NMOS tube; the drains of the first NMOS tube and the second NMOS tube are both connected to one end of the resistor, and the other end of the resistor serves as the control terminal of T3; the positive end of the voltage comparator is connected to the common node of the memristor M1, the memristor M2 and the resistor; the memristor M1 and the memristor M2 are the same; the first transistor and the second transistor are the same; the resistance value of the resistor is the low-resistance resistance value of the memristor; When performing Boolean logic operations, the memristor M1 is used to store the logic value b; the negative terminal of the voltage comparator is used to access the reference voltage V ref ; Memristor M2 is used to store logic value d; T1 control terminal and T2 control terminal are respectively used to access voltage V r ; The gate of the first transistor is used to access the gate voltage corresponding to the logic value a; the gate of the second transistor is used to access the gate voltage corresponding to the logic value c; the T3 control terminal is used to be grounded; the output terminal of the voltage comparator is used to output the corresponding Boolean logic operation result; Among them, V ref and V r Satisfy: (R H +R L )V r / (2R H +R L ) < V ref <2V r / 3; R H and R L are the high resistance and low resistance of the memristor respectively; the gate voltage corresponding to the logic value 0 is the voltage V less than the transistor turn-on voltage G , the gate voltage corresponding to the logic value 1 is greater than or equal to the transistor turn-on voltage V DD .

2. The Boolean logic circuit according to claim 1, characterized in that: When the Boolean logic operation is a true logic operation, a is 1, c is 0 or 1, b is 1, and d is 0 or 1; When the Boolean logic operation is a false logic operation, a is 0, c is 0, b is 0 or 1, and d is 0 or 1; When the Boolean logic operation is a p logic operation, a is p, c is 0, b is 1, and d is 0 or 1; When the Boolean logic operation is q logic operation, a is 0, c is q, b is 0 or 1, and d is 1; When the Boolean logic operation is a non-p logic operation, a is a logical value non-p, c is 0, b is 1, and d is 0 or 1; When the Boolean logic operation is a non-q logic operation, a is 0, c is a logical value non-q, b is 0 or 1, and d is 1; When the Boolean logic operation is the AND operation of logical values ​​p and q, a is p, c is 0, b is q, and d is 0 or 1; When the Boolean logic operation is the AND-NOT logic operation of logical values ​​p and q, a is the logical value not p, c is the logical value not q, b is 1, and d is 1; When the Boolean logic operation is the OR operation of logical values ​​p and q, a is p, c is q, b is 1, and d is 1; When the Boolean logic operation is a logical value p, q or a not logical operation, a is a logical value not p, c is 0, b is a logical value not q, and d is 0 or 1; When the Boolean logic operation is a substantial implied logic operation of logical values ​​p and q, a is the logical value not p, c is q, b is 1, and d is 1; When the Boolean logic operation is a negative substantial implication logic operation of logical values ​​p and q, a is p, c is 0, b is logical value not q, and d is 0 or 1; When the Boolean logic operation is the inverse substantial implication logic operation of the logical values ​​p and q, a is p, c is the logical value not q, b is 1, and d is 1; When the Boolean logic operation is the negative substantive implied logic operation of the logical values ​​p and q, a is the logical value not p, c is 0, b is q, and d is 0 or 1; When the Boolean logic operation is the exclusive OR logic operation of logical values ​​p and q, a is the logical value not p, c is p, b is q, and d is the logical value not q; When the Boolean logic operation is the exclusive OR logic operation of logical values ​​p and q, a is p, c is the logical value not p, b is q, and d is the logical value not q.

3. The control method of the Boolean logic circuit according to claim 1, characterized in that: The Boolean logic operation includes: applying voltage V to the T1 control terminal and the T2 control terminal of the Boolean logic circuit respectively. r , applying a gate voltage corresponding to a logic value a to the gate of the first transistor in the Boolean logic circuit, applying a gate voltage corresponding to a logic value c to the gate of the second transistor in the Boolean logic circuit, grounding the T3 control terminal of the Boolean logic circuit, and reading the corresponding Boolean logic operation result at the output terminal of the voltage comparator in the Boolean logic circuit; The memristor M1 in the Boolean logic circuit stores a logic value b, and the memristor M2 in the Boolean logic circuit stores a logic value d; the negative terminal of the voltage comparator in the Boolean logic circuit is connected to a reference voltage V ref ; V ref and V r Satisfy: (R H +R L )V r / (2R H +R L ) < V ref <2V r / 3; R H and R L are the high resistance and low resistance of the memristor respectively; the gate voltage corresponding to the logic value 0 is the voltage V less than the transistor turn-on voltage G , the gate voltage corresponding to the logic value 1 is greater than or equal to the transistor turn-on voltage V DD .

4. The control method according to claim 3, characterized in that: Also includes: an initialization memristor operation performed before the Boolean logic operation; The memristor initialization operation includes: writing a logic value b in the memristor M1; writing a logic value d in the memristor M2; The corresponding logic value is written by setting the high and low resistance states of the memristor; the high resistance state of the memristor corresponds to a logic value of 0, and the low resistance state corresponds to a logic value of 1.

5. The control method according to claim 4, characterized in that: Writing the logic value b into the memristor M1 comprises: When b is 0, the T1 control terminal is grounded, the T2 control terminal is set to a suspended state, and a fixed voltage V is connected to the T3 control terminal. q , V is applied to the gates of the first transistor and the second transistor DD , thereby writing a logic value b into the memristor M1; When b is 1, a fixed voltage V is connected to the control terminal of T1. p , set the T2 control terminal to a floating state, ground the T3 control terminal, and apply V to the gates of the first transistor and the second transistor. DD , thereby writing a logic value b into the memristor M1; Among them, V q >2|V reset |;V p >(R H +R L )V set / R H ; V reset V is the threshold value of the memristor changing from a low resistance state to a high resistance state; set is the threshold value of the memristor changing from a high resistance state to a low resistance state; R H is the high-resistance resistance value of the memristor; R L is the low-resistance state resistance value of the memristor.

6. The control method according to claim 4, characterized in that: Writing the logic value d into the memristor M2 comprises: When d is 0, the T1 control terminal is set to a suspended state, the T2 control terminal is grounded, and a fixed voltage V is connected to the T3 control terminal. q , V is applied to the gates of the first transistor and the second transistor DD , write a logic value d into the memristor M2; When d is 1, the T1 control terminal is set to a suspended state, and a fixed voltage V is connected to the T2 control terminal. p , ground the control terminal of T3, and apply V to the gates of the first transistor and the second transistor. DD , write a logic value d into the memristor M2; Among them, V q >2|V reset |;V p >(R H +R L )V set / R H ; V reset V is the threshold value of the memristor changing from a low resistance state to a high resistance state; set is the threshold value of the memristor changing from a high resistance state to a low resistance state; R H is the high-resistance resistance value of the memristor; R L is the low-resistance state resistance value of the memristor.

7. The control method according to any one of claims 3 to 6, characterized in that: When the Boolean logic operation is a true logic operation, a is 1, c is 0 or 1, b is 1, and d is 0 or 1; When the Boolean logic operation is a false logic operation, a is 0, c is 0, b is 0 or 1, and d is 0 or 1; When the Boolean logic operation is a p logic operation, a is p, c is 0, b is 1, and d is 0 or 1; When the Boolean logic operation is q logic operation, a is 0, c is q, b is 0 or 1, and d is 1; When the Boolean logic operation is a non-p logic operation, a is a logical value non-p, c is 0, b is 1, and d is 0 or 1; When the Boolean logic operation is a non-q logic operation, a is 0, c is a logical value non-q, b is 0 or 1, and d is 1; When the Boolean logic operation is the AND operation of logical values ​​p and q, a is p, c is 0, b is q, and d is 0 or 1; When the Boolean logic operation is the AND-NOT logic operation of logical values ​​p and q, a is the logical value not p, c is the logical value not q, b is 1, and d is 1; When the Boolean logic operation is the OR operation of logical values ​​p and q, a is p, c is q, b is 1, and d is 1; When the Boolean logic operation is a logical value p, q or a not logical operation, a is a logical value not p, c is 0, b is a logical value not q, and d is 0 or 1; When the Boolean logic operation is a substantial implied logic operation of logical values ​​p and q, a is the logical value not p, c is q, b is 1, and d is 1; When the Boolean logic operation is a negative substantial implication logic operation of logical values ​​p and q, a is p, c is 0, b is logical value not q, and d is 0 or 1; When the Boolean logic operation is the inverse substantial implication logic operation of the logical values ​​p and q, a is p, c is the logical value not q, b is 1, and d is 1; When the Boolean logic operation is the negative substantive implied logic operation of the logical values ​​p and q, a is the logical value not p, c is 0, b is q, and d is 0 or 1; When the Boolean logic operation is the exclusive OR logic operation of logical values ​​p and q, a is the logical value not p, c is p, b is q, and d is the logical value not q; When the Boolean logic operation is the exclusive OR logic operation of logical values ​​p and q, a is p, c is the logical value not p, b is q, and d is the logical value not q.

8. A Boolean logic operation device, characterized in that: include: A controller and a Boolean logic circuit as claimed in claim 1; The controller is used to execute the control method described in any one of claims 3-7.

9. A control system, characterized in that: include: A memory and a processor, wherein the memory stores a computer program, and the processor executes the control method according to any one of claims 3 to 7 when executing the computer program.

10. A computer program product, characterized in that The method comprises a computer program / instruction, which, when executed by a processor, implements the control method described in any one of claims 3 to 7.

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