A PLL adaptive trimming circuit

Abstract

The present invention belongs to the technical field of integrated circuits, and particularly relates to a PLL adaptive trimming circuit. It includes: a sampling analog-to-digital conversion module, which includes three sampling analog-to-digital conversion units. The in-phase input ends of the three sampling analog-to-digital conversion units are respectively connected to the voltage division nodes N1 to N3 on the voltage division network, the inverting input ends are all connected to the control voltage VCTRL, and the output ends respectively output a control signal B, a control signal E, and a control signal A; each of the sampling analog-to-digital conversion units is composed of a hysteresis comparator COMP1, a comparator COMP2, and an inverter INV1 connected in series in sequence; a digital trimming state machine, which is composed of a first gate circuit, an N-stage locking loop, and a second gate circuit connected in series in sequence; the present invention solves the problem that the working characteristics of the voltage-controlled phase-locked loop PLL are significantly reduced after being affected by PVT.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and particularly relates to a PLL adaptive trimming circuit. Background Art

[0002] In the design of PLL (Phase Lock Loop) phase-locked loops, there are two commonly used types. One is the LC phase-locked loop. Because of the presence of the inductor L in this phase-locked loop, it is commonly used for PLL systems with higher precision. However, the area occupied by the inductor L is relatively large, and there are noise problems in this area, which requires special treatment. The other is the loop design using an analog voltage-controlled unit. The circuit structure of this type has relatively lower precision than the LC delay unit, but its requirements for layout design are relatively low, and the area used is relatively small. For some non-radio frequency systems, this structure is more popular. However, because this structure is significantly affected by PVT, from front-end simulation to back-end simulation and even to the finished product stage, its locked frequency range is affected by PVT and may be reduced to 50% of the original design. The general design method is to add a large number of trimming designs peripherally to trim, so as to reduce the influence of process and voltage on the PLL. However, this will increase the workload and, to a certain extent, increase the difficulty of circuit trimming. Summary of the Invention

[0003] The purpose of the present invention is to provide a PLL adaptive trimming circuit to solve the significantly reduced working characteristics of the voltage-controlled phase-locked loop PLL after being affected by PVT.

[0004] To solve the above technical problems, the present invention provides a PLL adaptive trimming circuit, including:

[0005] A sampling analog-to-digital conversion module, including three sampling analog-to-digital conversion units. The in-phase input terminals of the three sampling analog-to-digital conversion units are respectively connected to the voltage-dividing nodes N1 to N3 on the voltage-dividing network, the anti-phase input terminals are all connected to the control voltage VCTRL, and the output terminals respectively output a control signal B, a control signal E, and a control signal A. Each sampling analog-to-digital conversion unit is composed of a hysteresis comparator COMP1, a comparator COMP2, and an inverter INV1 connected in series in sequence;

[0006] The digital trimming state machine is composed of a first gate circuit, N-level locking loops, and a second gate circuit connected in series in sequence; wherein the input end of the first gate circuit is used to input control signal A and control signal B, and the output end outputs control signal CON; the input end of the N-level locking loops is used to input control signal CON, enable signal EN, control signal A_Z, and control signal E_Z, and the output end is used to output digital signal Auto_Trim[N+1:0]; the input end of the second gate circuit is used to input power supply voltage VS, enable signal EN, and the output signal of the N-level locking loops, and the output end is used to output digital signal Auto_Trim[N];

[0007] The reference signal generation module is composed of a resistor array RES_ARRAY, several resistors R1, and a triode Q; the control end of the resistor array RES_ARRAY is used to input digital signal Auto_Trim[N:0], the power supply end is connected to power supply voltage VS, the grounding end is respectively connected to reference voltage VREF and grounded voltage VG through several series-connected resistors R1, reference voltage VREF is connected to the gate end of triode Q, and the substrate end, source end, and drain end of triode Q are all connected to grounded voltage VG.

[0008] Preferably, the voltage dividing network is composed of several resistors R2 connected in series in sequence, wherein the resistor R2 at the head end is connected to power supply voltage VS, the resistor R2 at the tail end is connected to grounded voltage VG, and voltage dividing nodes N1 to N3 are sequentially generated between every two adjacent resistors R2 from bottom to top.

[0009] Preferably, the three-channel sampling analog-to-digital conversion unit specifically includes: a first-channel sampling analog-to-digital conversion unit, a second-channel sampling analog-to-digital conversion unit, and a third-channel sampling analog-to-digital conversion unit;

[0010] Among them, in the first-channel sampling analog-to-digital conversion unit, the non-inverting input end and the inverting input end of the hysteresis comparator COMP1 are respectively connected to voltage dividing node N1 and control voltage VCTRL, the non-inverting output end and the inverting output end of the hysteresis comparator COMP1 respectively output control signals A1 and A2 to the inverting input end and the non-inverting input end of comparator COMP2, the output end of comparator COMP2 outputs control signal B_Z to the input end of inverter INV1, and the output end of inverter INV1 outputs control signal B;

[0011] In the second-channel sampling analog-to-digital conversion unit, the non-inverting input terminal and the inverting input terminal of the hysteresis comparator COMP1 are respectively connected to the voltage-dividing node N2 and the control voltage VCTRL. The non-inverting output terminal and the inverting output terminal of the hysteresis comparator COMP1 are respectively connected to the non-inverting input terminal and the inverting input terminal of the comparator COMP2. The output terminal of the comparator COMP2 outputs a control signal E_Z to the input terminal of the inverter INV1, and the output terminal of the inverter INV1 outputs a control signal E;

[0012] In the third-channel sampling analog-to-digital conversion unit, the non-inverting input terminal and the inverting input terminal of the hysteresis comparator COMP1 are respectively connected to the voltage-dividing node N3 and the control voltage VCTRL. The non-inverting output terminal and the inverting output terminal of the hysteresis comparator COMP1 are respectively connected to the non-inverting input terminal and the inverting input terminal of the comparator COMP2. The output terminal of the comparator COMP2 outputs a control signal A_Z to the input terminal of the inverter INV1, and the output terminal of the inverter INV1 outputs a control signal A.

[0013] Preferably, the first gate circuit is composed of NOR gates NOR1~NOR2, NAND gates NAND1~NAND2 and an inverter INV2. The control signal A and the control signal B are respectively connected to the two input terminals of the NOR gate NOR1. The output terminal of the NOR gate NOR1 is connected to the input terminal of the inverter INV2. The output terminal of the inverter INV2 and the output terminal of the NAND gate NAND1 are respectively connected to the two input terminals of the NAND gate NAND2. The control signal A and the control signal B are respectively connected to the two input terminals of the NAND gate NAND1. The output terminal of the NAND gate NAND2 and the control signal A are respectively connected to the two input terminals of the NOR gate NOR2, and the output terminal of the NOR gate NOR2 outputs a control signal CON.

[0014] Preferably, the N-stage lock-in loop includes a first-stage lock-in loop, a second-stage lock-in loop and a third-stage lock-in loop. Each stage of the lock-in loop is composed of a NAND gate NAND3, an inverter INV3, a flip-flop DFF and an inverter INV4. The output terminal of the NAND gate NAND3 is connected to the input terminal of the inverter INV3. The output terminal of the inverter INV3 is connected to the clock terminal of the flip-flop DFF. The power supply terminal of the flip-flop DFF is connected to the power supply voltage VS. The output terminal of the flip-flop DFF outputs a feedback signal through the inverter INV4 and is connected to the input terminal of the NAND gate NAND3.

[0015] Preferably, in the first-stage locking loop, the input terminals of the NAND gate NAND3 further include an input control signal CON and an enable signal EN. The output terminal of the inverter INV3 outputs a digital signal Auto_Trim[0], and the output terminal of the flip-flop DFF is connected to the input terminal of the NAND gate NAND3 in the second-stage locking loop.

[0016] Preferably, in the second-stage locking loop, the input terminals of the NAND gate NAND3 further include an input control signal E_Z and an enable signal EN. The output terminal of the inverter INV3 outputs a digital signal Auto_Trim[1], and the output terminal of the flip-flop DFF is connected to the input terminal of the NAND gate NAND3 in the third-stage locking loop.

[0017] Preferably, in the third-stage locking loop, the input terminals of the NAND gate NAND3 further include an input control signal A_Z and an enable signal EN. The output terminal of the inverter INV3 outputs a digital signal Auto_Trim[2], and the output terminal of the flip-flop DFF is connected to the input terminal of the NAND gate NAND4 in the second gate circuit.

[0018] Preferably, the second gate circuit is composed of a NAND gate NAND4 and an inverter INV5 connected in series in sequence. The input terminals of the NAND gate NAND4 further include an input enable signal EN and a power supply voltage VS, and the output terminal of the inverter INV5 outputs a digital signal Auto_Trim[3].

[0019] Preferably, the resistor array RES_ARRAY is composed of a plurality of resistors R3 connected in series in sequence and a plurality of transmission gate switches T connected in parallel in sequence. The power supply terminal of each transmission gate switch T is connected to any number of resistors R3, the ground terminal is connected to a reference voltage VREF, and the control terminal is connected to a digital signal Auto_Trim[3:0].

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] The PLL adaptive trimming circuit structure of the present invention can reduce the reduction of the PLL operating frequency and abnormal conditions caused by different system voltages, different process corners, and temperature deviations, and can reduce the difficulty of manual trimming. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is the basic structure circuit diagram of the PLL of the present invention.

[0023] Figure 2 is the structure circuit diagram of the VCO of the present invention.

[0024] Figure 3It is the circuit diagram of the basic ring oscillator unit structure of the present invention.

[0025] Figure 4 It is the circuit diagram of the sampling analog-to-digital conversion module of the present invention.

[0026] Figure 5 It is the present invention Figure 4 The enlarged view of the local structure in it; where (a) and (b) are the circuit diagrams of the connection ports of the hysteresis comparator COMP1 and the comparator COMP2 respectively.

[0027] Figure 6 It is the circuit diagram of the digital trimming state machine of the present invention.

[0028] Figure 7 It is the present invention Figure 6 The circuit diagram of the output control signal CON in it.

[0029] Figure 8 It is the circuit diagram of the reference signal generation module of the present invention.

[0030] Figure 9 It is the circuit diagram of the resistor array of the present invention.

[0031] Figure 10 It is the high and low frequency locking curve graph of the present invention. Specific embodiments

[0032] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for the purpose of conveniently and clearly assisting in explaining the embodiments of the present invention.

[0033] As Figure 1 shown, it is the basic PLL structure. This structure controls the oscillation frequency of the VCO through VCTRL. The bias current Ibias is generated by VCTRL, thereby realizing the VCO frequency control. Among them, PD is used to distinguish the phase frequency difference between the external reference clock and the clock generated inside the VCO, thereby generating the charging control for the charge pump. The capacitor of the LPF is used for integration, thereby generating the VCTRL voltage and controlling the VCO to change the frequency / phase, thereby realizing the matching with the reference frequency (the frequency and phase are the same as the reference clock). Therefore, this VCTRL is the main reference signal for the PLL circuit.

[0034] As Figure 2 shown, the VCO is composed of multiple serially connected amplifiers and a D2S differential-to-single-ended converter. As Figure 3As shown, the circuit is a delay unit of a basic ring oscillator. To achieve different oscillation frequencies, the magnitude of the Ibias current is used to change the oscillation frequency. Its most fundamental principle is RC delay, where the capacitor C is as shown in the circuit, and the resistor R is a variable resistor controlled by the Ibias current, which is achieved by adjusting the conduction state of the transistor through the Ibias current. Because there is a clamping amplifier (i.e., Figure 2 the amplifier structure in

[0035] ), the Vcalmp potential is the same as the VREF potential. Therefore, the resistance of PM1 at this time is (VS - Vclamp) / Ibias. When the current changes, the resistance of PM1 changes correspondingly. So, the gate potential of PM1 can control the resistance of PM2 and PM3, thereby achieving the delay effect. The oscillation frequency of the loop of the delay unit is f = 1 / (2NTd). The resistance R is significantly affected by the power supply voltage VS. For example, if the nominal value of VS is 1.1, and it may be 1 or 1.2 after deviation, it will cause the frequency to change. Similarly, temperature and process will also cause changes in Td. This situation objectively exists and cannot be avoided. Generally, when the chip is manufactured, factors such as process deviation are basically fixed. To achieve the optimal operating conditions of the chip / module, the performance of the circuit will be tested manually and optimized. However, PLL generally operates in different frequency ranges, especially in the case of a large frequency range. Because of different frequency conditions, the optimal trimming may be feasible at one frequency but may not be ideal in another case, so it will increase the difficulty of manual trimming. Figure 1 As can also be known from the above analysis, if VREF in the shown circuit decreases, the equivalent resistance of PM2 and PM3 is larger, Td is larger, and the frequency is smaller; similarly, if VREF increases, the equivalent resistance of PM2 and PM3 is smaller, Td is smaller, and the frequency is larger. The essence of changing VREF is to change the lockable range interval. For example, in the SS process corner, in the design where it is locked at 600M in TT, 600M may not be locked (due to the RC value being too large caused by process deviation, resulting in the inability to reach the locked frequency). In this case, the bias current Ibias can be controlled manually for optimization to achieve locking, but manual correction is required. With this design, a reference voltage can be set at a higher VREF value. When VCTRL is greater than the reference voltage VNX, the circuit will expand the high-frequency range, so that the SS process corner can be locked without adjusting the current. Similarly, in the SS process corner, manual correction for locking will increase the current value. Although this can achieve 600M locking, if SS is to be locked at a low frequency of 150M, because the increased current value is fixed, it cannot be locked at 150M. Therefore, the locking range of this circuit is limited (even though it can be trimmed).

[0036] Therefore, if a certain functional relationship can be established between the VCTRL signal and the VREF signal in the circuit, the frequency of the circuit can be correspondingly changed with the change of the input reference frequency, and at the same time, relevant stability or other adjustment operations can be carried out.

[0037] Therefore, the present invention adopts a circuit structure as shown in Figure 4 to compare the voltage VCTRL generated by the current generated by the charge pump in the LPF (low-pass filter circuit) with the resistance voltage division generated by the power supply voltage VS in the branch. Among them, it can be artificially designed to confirm the voltages of nodes N1, N2, and N3. When VCTRL changes to be greater than VN1, VN2, and VN3, the corresponding control signals A, E, and B become high levels. And because there is ripple in VCTRL, it is possible that its ripple is higher than VN1~NV3 (comparison values), but its RMS value is not higher than VNX (RMS is the abbreviation of root mean square, that is, root mean square. Here, it means that VCTRL can be considered as a sawtooth wave slanting upwards. When this waveform is compared with a stable VNX, if there is no hysteresis comparator, once the sawtooth wave is greater than VNX, a high level will be output. However, the actual waveform may not want it to be so sensitive, resulting in a change in VREF). Therefore, a hysteresis comparator COMP1 is added to achieve delayed comparison and avoid misjudgment.

[0038] When control signals A, E, B, and E_Z change correspondingly due to VCTRL, these signals are added to the state machine for analysis, and a signal of Auto_Trim[3:0] is generated accordingly. This signal can control Figure 8 the VREF value generated in the reference signal generation module in

[0039] Please refer specifically to the Figures 4 to 9 shown in the figure. The embodiment of the present invention specifically provides a PLL adaptive tuning circuit, including:

[0040] A sampling analog-to-digital conversion module, including three sampling analog-to-digital conversion units. The non-inverting input terminals of the three sampling analog-to-digital conversion units are respectively connected to the voltage division nodes N1~N3 on the voltage division network, the inverting input terminals are all connected to the control voltage VCTRL, and the output terminals respectively output a control signal B, a control signal E, and a control signal A; each sampling analog-to-digital conversion unit is composed of a hysteresis comparator COMP1, a comparator COMP2, and an inverter INV1 connected in series in sequence;

[0041] The digital trimming state machine is composed of a first gate circuit, N-level locking loops, and a second gate circuit connected in series in sequence. The input terminal of the first gate circuit is used to input control signal A and control signal B, and the output terminal outputs control signal CON. The input terminal of the N-level locking loops is used to input control signal CON, enable signal EN, control signal A_Z, and control signal E_Z, and the output terminal is used to output digital signal Auto_Trim[N+1:0]. The input terminal of the second gate circuit is used to input power supply voltage VS, enable signal EN, and the output signal of the N-level locking loops, and the output terminal is used to output digital signal Auto_Trim[N].

[0042] The reference signal generation module is composed of a resistor array RES_ARRAY, several resistors R1, and a triode Q. The control terminal of the resistor array RES_ARRAY is used to input digital signal Auto_Trim[N:0], the power supply terminal is connected to power supply voltage VS, the grounding terminal is respectively connected to reference voltage VREF and grounded voltage VG through several series-connected resistors R1, reference voltage VREF is connected to the gate terminal of triode Q, and the substrate terminal, source terminal, and drain terminal of triode Q are all connected to grounded voltage VG.

[0043] The voltage dividing network is composed of several resistors R2 connected in series in sequence. Among them, the resistor R2 at the head end is connected to power supply voltage VS, the resistor R2 at the tail end is connected to grounded voltage VG, and voltage dividing nodes N1 to N3 are sequentially generated between every two adjacent resistors R2 from bottom to top.

[0044] The three-channel sampling analog-to-digital conversion unit specifically includes: a first-channel sampling analog-to-digital conversion unit, a second-channel sampling analog-to-digital conversion unit, and a third-channel sampling analog-to-digital conversion unit.

[0045] Among them, in the first-channel sampling analog-to-digital conversion unit, the non-inverting input terminal and the inverting input terminal of the hysteresis comparator COMP1 are respectively connected to voltage dividing node N1 and control voltage VCTRL. The non-inverting output terminal and the inverting output terminal of the hysteresis comparator COMP1 respectively output control signals A1 and A2 to the inverting input terminal and the non-inverting input terminal of comparator COMP2. The output terminal of comparator COMP2 outputs control signal B_Z to the input terminal of inverter INV1, and the output terminal of inverter INV1 outputs control signal B.

[0046] Among them, in the second-channel sampling analog-to-digital conversion unit, the non-inverting input terminal and the inverting input terminal of the hysteresis comparator COMP1 are respectively connected to voltage dividing node N2 and control voltage VCTRL. The non-inverting output terminal and the inverting output terminal of the hysteresis comparator COMP1 are respectively connected to the non-inverting input terminal and the inverting input terminal of comparator COMP2. The output terminal of comparator COMP2 outputs control signal E_Z to the input terminal of inverter INV1, and the output terminal of inverter INV1 outputs control signal E.

[0047] In the third-channel sampling analog-to-digital conversion unit, the non-inverting input terminal and the inverting input terminal of the hysteresis comparator COMP1 are respectively connected to the voltage dividing node N3 and the control voltage VCTRL. The non-inverting output terminal and the inverting output terminal of the hysteresis comparator COMP1 are respectively connected to the non-inverting input terminal and the inverting input terminal of the comparator COMP2. The output terminal of the comparator COMP2 outputs a control signal A_Z to the input terminal of the inverter INV1, and the output terminal of the inverter INV1 outputs a control signal A.

[0048] As Figure 4 shown, when VCTRL > VN1, B outputs a low level; on the contrary, when VCTRL < VN1, B outputs a high level. The function of the hysteresis comparator COMP1 is that when VN1 > VCTRL by about 50 mV, B will then change from H to L; in other words, for A or E, it is exactly the opposite, that is, when VCTRL changes to be greater than VN2, E changes from L to H at this time (because the connection method of A1 and A2 is opposite to that of the A and E branches).

[0049] The first gate circuit is composed of NOR gates NOR1~NOR2, NAND gates NAND1~NAND2, and an inverter INV2. The control signal A and the control signal B are respectively connected to the two input terminals of the NOR gate NOR1. The output terminal of the NOR gate NOR1 is connected to the input terminal of the inverter INV2. The output terminal of the inverter INV2 and the output terminal of the NAND gate NAND1 are respectively connected to the two input terminals of the NAND gate NAND2. The control signal A and the control signal B are respectively connected to the two input terminals of the NAND gate NAND1. The output terminal of the NAND gate NAND2 and the control signal A are respectively connected to the two input terminals of the NOR gate NOR2. The output terminal of the NOR gate NOR2 outputs a control signal CON.

[0050] The N-stage locking loop includes a first-stage locking loop, a second-stage locking loop, and a third-stage locking loop. Each stage of the locking loop is composed of a NAND gate NAND3, an inverter INV3, a flip-flop DFF, and an inverter INV4. The output terminal of the NAND gate NAND3 is connected to the input terminal of the inverter INV3. The output terminal of the inverter INV3 is connected to the clock terminal of the flip-flop DFF. The power supply terminal of the flip-flop DFF is connected to the power supply voltage VS. The output terminal of the flip-flop DFF outputs a feedback signal through the inverter INV4 and is connected to the input terminal of the NAND gate NAND3.

[0051] In the first-stage locking loop, the input terminals of the NAND gate NAND3 further include an input control signal CON and an enable signal EN. The output terminal of the inverter INV3 outputs a digital signal Auto_Trim[0]. The output terminal of the flip-flop DFF is connected to the input terminal of the NAND gate NAND3 in the second-stage locking loop.

[0052] In the second-stage locking loop, the input terminals of the NAND gate NAND3 further include an input control signal E_Z and an enable signal EN. The output terminal of the inverter INV3 outputs a digital signal Auto_Trim[1]. The output terminal of the flip-flop DFF is connected to the input terminal of the NAND gate NAND3 in the third-stage locking loop.

[0053] In the third-stage locking loop, the input terminals of the NAND gate NAND3 further include an input control signal A_Z and an enable signal EN. The output terminal of the inverter INV3 outputs a digital signal Auto_Trim[2]. The output terminal of the flip-flop DFF is connected to the input terminal of the NAND gate NAND4 in the second gate circuit.

[0054] The second gate circuit is composed of a NAND gate NAND4 and an inverter INV5 connected in series in sequence. The input terminals of the NAND gate NAND4 further include an input enable signal EN and a power supply voltage VS. The output terminal of the inverter INV5 outputs a digital signal Auto_Trim[3].

[0055] As Figure 6 and Figure 7 shown, taking the input point of NAND3 as Y, then when A is H, Y = L; when A is L and B is H, Y = H; when A is L and B is L, Y = L.

[0056] As Figure 9 shown, the resistor array RES_ARRAY is composed of a number of resistors R3 connected in series in sequence and a number of transmission gate switches T connected in parallel in sequence. The power supply terminal of each transmission gate switch T is connected to any number of resistors R3, the ground terminal is connected to a reference voltage VREF, and the control terminal is connected to a digital signal Auto_Trim[3:0].

[0057] Specific implementation example: First, set RST in Figure 6 to a high level, that is, reset the flip-flop. The default output of the flip-flop is low level. When VCTRL is at a lower level, Figure 4If VN1 = (VS - VG) × 0.25, VN2 = (VS - VG) × 0.5, and VN3 = (VS - VG) × 0.75, then when VCTRL is low, i.e., VCTRL < VN1, for the input of NAND3 in branch B, since B = H and A = L, the output of NOR2 (the input of NAND3) is H (Y = H). At this time, Auto_Trim[0] will output a high level, thereby controlling the reference signal generation module to output VREF0 = (VS - VG) × 4R1 / (6 × R3 + 4 × R1). Then, as the PLL operates, VCTRL will continuously increase until the circuit stabilizes. It is possible that VCTRL at the locked frequency will not be higher than VN1, in which case only Auto_Trim[0] in the circuit outputs a high level, and the other Auto_Trim[3:1] will continue to maintain the low level after being set by RST. It is also possible that due to the action of the charge pump and integration on the capacitor of the LPF, the voltage of VCTRL increases, which may then lead to VN2 > VCTRL > VN1. In this case, first, B will change from the high level H to the low level L, causing the D flip - flop to be triggered on the falling edge, outputting the VS level from the D terminal to the Q terminal, so that the output of the first - stage DFF is H, and Auto_Trim[0] becomes low and remains so, thus locking the first stage (the loop composed of NAND3, INV3, DFF, and INV4), keeping Auto_Trim[0] low all the time. Looking at the second stage, since the first - stage output H goes to NAND3 and the EN enable is set to H (set to H from the beginning of this module), and the output level of the feedback loop INV4 in the second stage is high, the decision is then left to E_Z. When VCTRL < VN2, E_Z is high (E is low), so at this time Auto_Trim[1] is high, and thus VREF changes to VREF1 = (VS - VG) × 4R1 / (5 × R3 + 4 × R1), that is, VREF1 > VREF0. Since increasing VREF will increase the oscillation frequency range of the VCO, such a change can increase the locked - frequency range.

[0058] Furthermore, the embodiments of the present invention are elaborated in detail as follows in the implementation process:

[0059] 1) Taking FF_-55 at a low frequency of 100M as an example

[0060] Compared with the TT_25 process corner, FF_-55 has a larger current, a smaller threshold, and a relatively smaller resistance value, which will cause the frequency of the VCO to be higher than that of TT_25 under the same configuration. Relatively speaking, there may be problems with locking at low frequencies for FF_-55. If a lower VREF can be provided at low frequencies to Figure 3In the ring oscillator circuit, the overall frequency of the ring oscillator will decrease (without changing the tail current). For example, if Figure 4 the resistors in are designed and the VS voltage is 1.1V, then VN1, VN2, and VN3 are set to 400m, 600m, and 850m. When FF_-55 is locked at 100M, first VCTRL will increase. However, since the frequency corresponding to FF_-55 is relatively high, although VCTRL increases, it will not reach 400m. For the hysteresis comparator COMP1, when VIN is L and VIP is H, then VON is H and VOP is L. For the comparator COMP2, when VIN is L, the output is L; when VIN is H, the output is H. Therefore, the sampled ADC output is B_Z = L, B = H, A_Z = H, A = L, E_Z = H, E = L. First, the RST reset signal of the state machine is used to reset the circuit, and by default, Auto_Trim[3:0] are all at low level, thus resetting VREF to the low level 0. When the PLL starts to work, the VCTRL voltage increases. Looking at the trimming state machine again, at this time A = H and B = L, and the corresponding state machine Auto_Trim[0] is high while Auto_Trim[3:1] are all low. So at this time, the reference voltage VREF generated by the reference signal generation module is determined by VS - VS / (Rvar + Rcom)×Rvar = VS×Rcom / (Rvar + Rcom) (Rvar represents the resistor R3 in the trimming array, which realizes a variable resistor structure as the transmission gate accesses and separates the circuit; Rcom represents Figure 8 the four resistors R1 in). And when Rvar is relatively large, VREF is relatively small.

[0061] 2) Taking SS_125 at high frequency 600M as an example

[0062] Compared with the TT_25 process corner, SS_125 has a smaller current, a larger threshold, and a relatively larger resistance value. This will cause the frequency of the VCO to be higher than that of TT_25 under the same configuration. Relatively speaking, there may be problems with locking at high frequencies for SS_125. If a higher VREF can be provided at high frequencies to Figure 3In the ring oscillator circuit, the overall frequency of the ring oscillator will increase (without changing the tail current). Assume that VCTRL gradually increases. When it is higher than the potential of N3, at this time B = L, B_Z = H, E_Z = L, E = H, A = H, A_Z = L. However, before VCTRL is higher than N3, there is a situation where VCTRL is higher than N2 and lower than N3 voltage. In this case, at this time B = L, B_Z = H, E_Z = L, E = H, A_Z = H, A = L. In this situation, TT2 is high. When it is greater than N3, this situation will occur where A_Z = H → L. At this time, TT2 changes from high level to low level, and the subsequent DFF will capture the falling edge, thereby changing the output of the DFF to high level. As a result, the output of Auto_Trim[3] is high level, which controls the trimming resistor RES of the reference output circuit to change to Rvar. The corresponding voltage is smaller, and the relevant VREF is still VS×Rcom / (Rvar + Rcom). However, since the Rvar resistor decreases, VREF becomes larger, thereby increasing the circuit frequency. The DFF feedback loop is designed as a one-time locking design, which can ensure continuous locking after power-on.

[0063] The following Table 1, Table 2, and Table 3 are the tables of the hysteresis amplifier logic (analog), comparator logic (analog), and the output logic of the sampling analog-to-digital conversion module ADC, respectively.

[0064] Table 1

[0065] VIN H L VIP L H VON L H VOP H L

[0066] Table 2

[0067] VIN H L VIP L H VON H L

[0068] Table 3

[0069] Channel B A1 (Analog) A2 (Analog) B (Digital) B_Z (Digital) VCTRL > VREF L H L H VCTRL < VREF H L H L E, Channel A / / A / E (Digital) A / E (Digital) VCTRL > VREF L H H L VCTRL < VREF H L L H

[0070] As Figure 10 shown, VR1~VR4 represent VREF0~VREF3. A simple explanation: Look at the green curves (look at the two together). That is, when Auto_Trim[0] is turned on, the VREF1 output, and the corresponding locking curve is green; look at the red curve. When VCTRL is greater than VN1 (about dozens of millivolts), at this time Auto_Trim[0] is turned off, and Auto_Trim[1] is turned on. Similarly, when VCTRL is greater than VN2, Auto_Trim[1] is turned off, and Auto_Trim[2] is turned on. When VCTRL is greater than NV3, Auto_Trim[2] is turned off, and Auto_Trim[3] is turned on, and so on (it can be divided into several levels for resistor voltage division and Auto_Trim control).

[0071] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure fall within the scope of protection of the claims.

Claims

1. A PLL adaptive trimming circuit, characterized in that: include: The sampling analog-to-digital conversion module comprises three sampling analog-to-digital conversion units, wherein the in-phase input terminals of the three sampling analog-to-digital conversion units are respectively connected to the voltage-dividing nodes N1-N3 on the voltage-dividing network, and the inverting input terminals are all connected to the control voltage VCTRL, which is used as the control voltage of the VCO in the PLL, that is, the output voltage of the LPF in the PLL; the output terminals respectively output the control signal B, the control signal E and the control signal A; wherein each sampling analog-to-digital conversion unit is composed of a hysteresis comparator COMP1, a comparator COMP2 and an inverter INV1 connected in series in sequence; A digital trimming state machine, comprising a first gate circuit, an N-stage locked loop, and a second gate circuit connected in series in sequence; wherein the input end of the first gate circuit is used to input a control signal A and a control signal B, and the output end outputs a control signal CON; the input end of the N-stage locked loop is used to input a control signal CON, an enable signal EN, a control signal A_Z, and a control signal E_Z, wherein the control signal A_Z and the control signal E_Z are respectively inverted signals of the control signal A and the control signal E; the output end is used to output a digital signal Auto_Trim[N+1:0]; the input end of the second gate circuit is used to input a power supply voltage VS, an enable signal EN, and an output signal of the N-stage locked loop, and the output end is used to output a digital signal Auto_Trim[N]; A reference signal generating module is composed of a resistor array RES_ARRAY, a plurality of resistors R1 and a transistor Q; the control end of the resistor array RES_ARRAY is used to input a digital signal Auto_Trim[N:0], the power end is connected to a power supply voltage VS, the ground end is respectively connected to a reference voltage VREF and a ground voltage VG through a plurality of resistors R1 connected in series, the reference voltage VREF is connected to a gate end of the transistor Q, and the substrate end, source end and drain end of the transistor Q are all connected to the ground voltage VG; The output end of the sampling analog-to-digital conversion module is connected to the input end of the digital trimming state machine, the output end of the digital trimming state machine is connected to the control end of the reference signal generating module, the output end of the reference signal generating module outputs a reference voltage VREF and is connected to the VREF end of the VCO for adjusting the reference voltage VREF of the VCO; The first gate circuit is composed of NOR gates NOR1~NOR2, NAND gates NAND1~NAND2 and an inverter INV2; the control signal A and the control signal B are respectively connected to the two input ends of the NOR gate NOR1, the output end of the NOR gate NOR1 is connected to the input end of the inverter INV2, the output end of the inverter INV2 and the output end of the NAND gate NAND1 are respectively connected to the two input ends of the NAND gate NAND2, the control signal A and the control signal B are respectively connected to the two input ends of the NAND gate NAND1, the output end of the NAND gate NAND2 and the control signal A are respectively connected to the two input ends of the NOR gate NOR2, and the output end of the NOR gate NOR2 outputs the control signal CON; The N-level locked loop includes a first-level locked loop, a second-level locked loop and a third-level locked loop; each level of the locked loop is composed of a NAND gate NAND3, an inverter INV3, a trigger DFF and an inverter INV4; the output end of the NAND gate NAND3 is connected to the input end of the inverter INV3, the output end of the inverter INV3 is connected to the clock end of the trigger DFF, the power supply end of the trigger DFF is connected to the power supply voltage VS, the output end of the trigger DFF outputs a feedback signal by connecting to the inverter INV4, and is connected to the input end of the NAND gate NAND3; The second gate circuit is composed of a NAND gate NAND4 and an inverter INV5 connected in series in sequence; the input end of the NAND gate NAND4 also includes an input enable signal EN and a power supply voltage VS, and the output end of the inverter INV5 outputs a digital signal Auto_Trim[3].

2. A PLL adaptive trimming circuit as claimed in claim 1, characterized in that: The voltage divider network is composed of a plurality of resistors R2 connected in series, wherein the resistor R2 at the head end is connected to the power supply voltage VS, and the resistor R2 at the tail end is connected to the ground voltage VG, and voltage divider nodes N1 to N3 are generated in sequence between every two adjacent resistors R2 from bottom to top.

3. A PLL adaptive trimming circuit as claimed in claim 2, characterized in that: The three sampling analog-to-digital conversion units specifically include: a first sampling analog-to-digital conversion unit, a second sampling analog-to-digital conversion unit and a third sampling analog-to-digital conversion unit; Wherein, in the first sampling analog-to-digital conversion unit, the non-inverting input terminal and the inverting input terminal of the hysteresis comparator COMP1 are respectively connected to the voltage dividing node N1 and the control voltage VCTRL, the non-inverting output terminal and the inverting output terminal of the hysteresis comparator COMP1 respectively output control signals A1 and A2 to the inverting input terminal and the non-inverting input terminal of the comparator COMP2, the output terminal of the comparator COMP2 outputs the control signal B_Z to the input terminal of the inverter INV1, and the output terminal of the inverter INV1 outputs the control signal B; Wherein, in the second sampling analog-to-digital conversion unit, the non-inverting input terminal and the inverting input terminal of the hysteresis comparator COMP1 are respectively connected to the voltage dividing node N2 and the control voltage VCTRL, the non-inverting output terminal and the inverting output terminal of the hysteresis comparator COMP1 are respectively connected to the non-inverting input terminal and the inverting input terminal of the comparator COMP2, the output terminal of the comparator COMP2 outputs the control signal E_Z to the input terminal of the inverter INV1, and the output terminal of the inverter INV1 outputs the control signal E; In the third sampling analog-to-digital conversion unit, the non-inverting input terminal and the inverting input terminal of the hysteresis comparator COMP1 are respectively connected to the voltage dividing node N3 and the control voltage VCTRL, the non-inverting output terminal and the inverting output terminal of the hysteresis comparator COMP1 are respectively connected to the non-inverting input terminal and the inverting input terminal of the comparator COMP2, the output terminal of the comparator COMP2 outputs the control signal A_Z to the input terminal of the inverter INV1, and the output terminal of the inverter INV1 outputs the control signal A.

4. A PLL adaptive trimming circuit as claimed in claim 1, characterized in that: In the first-stage locked loop, the input end of the NAND gate NAND3 also includes the input control signal CON and the enable signal EN, the output end of the inverter INV3 outputs the digital signal Auto_Trim[0], and the output end of the trigger DFF is connected to the input end of the NAND gate NAND3 in the second-stage locked loop.

5. A PLL adaptive trimming circuit as claimed in claim 1, characterized in that: In the second-stage locked loop, the input end of the NAND gate NAND3 also includes the input control signal E_Z and the enable signal EN, the output end of the inverter INV3 outputs the digital signal Auto_Trim[1], and the output end of the trigger DFF is connected to the input end of the NAND gate NAND3 in the third-stage locked loop.

6. A PLL adaptive trimming circuit as claimed in claim 1, characterized in that: In the third-level locked loop, the input end of the NAND gate NAND3 also includes the input control signal A_Z and the enable signal EN, the output end of the inverter INV3 outputs the digital signal Auto_Trim[2], and the output end of the trigger DFF is connected to the input end of the NAND gate NAND4 in the second gate circuit.

7. A PLL adaptive trimming circuit as claimed in claim 1, characterized in that: The resistor array RES_ARRAY is composed of a number of resistors R3 connected in series and a number of transmission gate switches T connected in parallel; the power supply end of each transmission gate switch T is connected to an arbitrary number of resistors R3, the ground end is connected to a reference voltage VREF, and the control end is connected to a digital signal Auto_Trim[3:0].

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