Disturbance injection circuit and disturbance injection method

Abstract

The invention discloses a disturbance injection circuit and a disturbance injection method, the disturbance injection circuit is applied to an analog-to-digital converter with a 1-bit quantizer, the disturbance injection circuit comprises a capacitor array of a first-stage integrator in a loop filter, the 1-bit quantizer and a disturbance unit, and the output of the loop filter is connected with the 1-bit quantizer; the 1-bit quantizer comprises a second sampling capacitor, a comparison capacitor, a first injection capacitor, a second injection capacitor, a comparator and a register. According to the quantizer, disturbance signals are injected twice through the comparison capacitor, the first injection capacitor and the second injection capacitor to obtain the corresponding second digital output quantity, and finally the capacitor array is disturbed by combining the first digital output quantity output by the disturbance unit, so that the quantizer can ensure that the residual voltage is smaller than a minimum significant bit in a full input measuring range; therefore, the problem that in the prior art, when the resolution is 1-bit, the suppression effect on extra noise caused by disturbance signals is remarkably reduced is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a disturbance injection circuit and a disturbance injection method. Background Art

[0002] Sigma-delta ADC (analog-to-digital converter) is a commonly used medium-to-high precision ADC structure. However, when the input signal is DC or changes slowly with a small amplitude (such as in sensor applications), the output of the modulator will have an idle tone phenomenon, thereby deteriorating the signal-to-noise-distortion ratio (SNDR) within the band. The idle tone problem can be eliminated by injecting a discrete random disturbance signal (dither) at the input of the quantizer. However, this method not only reduces the signal-to-quantization-noise ratio (SQNR) of the modulator, but also causes the output swing of the first-stage integrator to increase, thereby placing higher linearity requirements on the transconductance operational amplifier (OTA) in the first-stage integrator. In addition, for modulator structures using low-resolution quantizers, the injection of dither may also reduce the maximum stable input amplitude (MSA).

[0003] In the prior art, subtractive dithering technology can be used to meet the above requirements, such as Figure 1 As shown in the figure, by injecting a dither signal with the same amplitude as the quantizer input into the DA capacitor array of the first-stage integrator and the digital output of the quantizer at the same time, the additional noise power caused by dither can be effectively reduced. However, when the quantizer resolution is 1-bit, the suppression effect of the subtractive disturbance injection technology on the additional noise caused by dither will be significantly reduced.

[0004] Based on this, a new technical solution is needed. Summary of the invention

[0005] In view of this, an embodiment of the present invention provides a disturbance injection circuit and a disturbance injection method to at least solve the problem that the suppression effect of the existing subtractive disturbance injection technology on the additional noise caused by the disturbance signal is significantly reduced when the resolution is 1-bit.

[0006] The embodiment of the present invention provides the following technical solutions: An embodiment of the present invention provides a disturbance injection circuit, which is applied to an analog-to-digital converter with a 1-bit quantizer. The disturbance injection circuit includes a capacitor array of a first-stage integrator in a loop filter, a 1-bit quantizer, and a disturbance unit. The output of the loop filter is connected to the 1-bit quantizer, and the disturbance unit is used to output a first digital output quantity. The 1-bit quantizer includes a second sampling capacitor, a comparison capacitor, a first injection capacitor, a second injection capacitor, a comparator and a register; The bottom plate of the second sampling capacitor can be connected to the output terminal and the common mode voltage of the loop filter respectively through a sampling switch, and the bottom plate of the comparison capacitor, the bottom plate of the first injection capacitor, and the bottom plate of the second injection capacitor can all be connected to a positive reference voltage, a negative reference voltage, or a common mode voltage through corresponding switches, and can all obtain the disturbance signal injected by the disturbance unit through the corresponding switches; The top plate of the second sampling capacitor, the top plate of the comparison capacitor, the top plate of the first injection capacitor, and the top plate of the second injection capacitor are all connected to the positive input terminal of the comparator, the negative input terminal of the comparator is grounded, and the positive input terminal of the comparator is connected to the negative input terminal of the comparator through a comparator input switch, the output terminal of the comparator is connected to the register, and the register outputs a corresponding second digital output according to the output result of the comparator, and the second digital output and the first digital output are superimposed to control the array capacitor in the capacitor array to be connected to a positive reference voltage or a negative reference voltage.

[0007] Further, the comparison capacitor is connected to the positive reference voltage, the negative reference voltage or the common mode voltage through a comparison switch; The first injection capacitor is connected to the positive reference voltage, the negative reference voltage or the common mode voltage through a first injection switch; The second injection capacitor is connected to the positive reference voltage, the negative reference voltage or the common mode voltage through a second injection switch; The disturbance unit injects a first disturbance signal into the second injection capacitor through the second injection switch, and injects a second disturbance signal into the comparison capacitor and the first injection capacitor through the comparison switch and the first injection switch respectively; The comparator outputs a first comparison result according to the input signal, the second disturbance signal injected into the first injection capacitor, and the first disturbance signal injected into the second injection capacitor, and outputs a second comparison result according to the input signal and the second disturbance signal injected into the comparison capacitor; The register stores the first comparison result and the second comparison result, and outputs two second digital output quantities according to the first comparison result and the second comparison result.

[0008] Further, when the second disturbance signal is equal to 0, the first injection capacitor is connected to the negative reference voltage through the first injection switch, and when the second disturbance signal is equal to 1, the first injection capacitor is connected to the positive reference voltage through the first injection switch; When the first disturbance signal is equal to 0, the second injection capacitor is connected to the negative reference voltage through the second injection switch; when the first disturbance signal is equal to 1, the second injection capacitor is connected to the positive reference voltage through the second injection switch.

[0009] Further, when the second disturbance signal is equal to 0, the comparison capacitor is connected to the positive reference voltage through the comparison switch, and when the second disturbance signal is equal to 1, the comparison capacitor is connected to the negative reference voltage through the comparison switch.

[0010] Furthermore, when the comparator outputs a result of 1, the register outputs 0; and when the comparator outputs a result of 0, the register outputs -1.

[0011] Furthermore, the capacitor array includes a plurality of array capacitors connected in parallel, and each of the array capacitors can be connected to the positive reference voltage, the negative reference voltage or the common mode voltage through a corresponding array switch.

[0012] Furthermore, the loop filter further comprises: An operational amplifier, wherein the positive input terminal of the operational amplifier is grounded, the negative input terminal is connected to the first sampling capacitor and the capacitor array respectively, and the positive input terminal of the operational amplifier is connected to the negative input terminal of the operational amplifier through a corresponding operational amplifier input switch; an integrating capacitor connected between the negative input terminal of the operational amplifier and the output terminal of the operational amplifier; A back-end integrated unit, wherein the input end of the back-end integrated unit is connected to the output end of the operational amplifier, and the output end of the back-end integrated unit is connected to the second sampling capacitor.

[0013] The present invention also provides a disturbance injection method, which is applied to any disturbance injection circuit as described above, comprising: Connecting the bottom plate of the capacitor array, the bottom plate of the comparison capacitor, the bottom plate of the first injection capacitor, and the bottom plate of the second injection capacitor to a common mode voltage, sampling the input signal through the first sampling capacitor, and sampling the output of the loop filter through the second sampling capacitor; Connecting the bottom plate of the first sampling capacitor to the common mode voltage, and connecting the bottom plate of the first injection capacitor and the bottom plate of the second injection capacitor to a positive reference voltage or a negative reference voltage according to the disturbance signal injected into the first injection capacitor and the second injection capacitor, so as to sum the input signal, the disturbance signal injected into the first injection capacitor, and the disturbance signal injected into the second injection capacitor in the signal domain and obtain a first input voltage; The comparator obtains the first input voltage, compares it with the first comparator threshold, obtains a first comparison result, and sends the first comparison result to a register for temporary storage; The bottom plate of the comparison capacitor is connected to a positive reference voltage or a negative reference voltage according to the value of the corresponding disturbance signal, so as to achieve the summation of the input signal and the disturbance signal injected into the comparison capacitor in the signal domain to obtain a second input voltage; The comparator obtains the second input voltage, compares it with the second comparator threshold, obtains a second comparison result, and sends the second comparison result to the register for temporary storage; The register outputs two second digital output quantities correspondingly according to the first comparison result and the second comparison result; The two second digital outputs are superimposed on the first digital output outputted by the disturbance unit to obtain a third digital output, and the bottom plate of the array capacitor in the capacitor array is adjusted to be connected to the positive reference voltage or the negative reference voltage according to the third digital output.

[0014] Further, the connecting the bottom plate of the first injection capacitor and the bottom plate of the second injection capacitor to the positive reference voltage or the negative reference voltage according to the disturbance signal injected into the first injection capacitor and the second injection capacitor comprises: When the value of the disturbance signal injected into the first injection capacitor and the second injection capacitor is 0, the bottom plate of the first injection capacitor and the bottom plate of the second injection capacitor are connected to the negative reference voltage; When the value of the disturbance signal injected into the first injection capacitor and the second injection capacitor is 1, the bottom plate of the first injection capacitor and the bottom plate of the second injection capacitor are connected to the positive reference voltage.

[0015] Further, the bottom plate of the comparison capacitor is connected to a positive reference voltage or a negative reference voltage according to the value of the corresponding disturbance signal, including: When the value of the disturbance signal injected into the comparison capacitor is 1, the bottom plate of the comparison capacitor is connected to the negative reference voltage; When the value of the disturbance signal injected into the comparison capacitor is 0, the bottom plate of the comparison capacitor is connected to the positive reference voltage.

[0016] Compared with the prior art, the at least one technical solution adopted in the embodiment of the present invention can achieve the following beneficial effects: A disturbance injection circuit of the present invention injects a disturbance signal into a first injection capacitor and a second injection capacitor, so that a comparator performs a first comparison according to the injected disturbance signal and an input signal, and after the first comparison of the comparator is completed, the comparator threshold is adjusted according to the injected disturbance signal, and the disturbance signal is continuously injected into the comparison capacitor, so that the comparator performs a second comparison according to the disturbance signal injected into the comparison capacitor and the input signal, thereby obtaining a quantizer digital output according to the sum of the two comparison results, and performing an injection in a capacitor array of a first-stage integrator according to the quantizer digital output result, so that the capacitor array controls the capacitor array to be connected to a corresponding voltage according to the quantizer output result and the injection signal injected into the capacitor array, so that the quantizer can ensure that the residual voltage is less than a least significant bit within the full input range. The disturbance injection circuit of the present invention obtains two corresponding second digital output quantities by injecting two disturbance signals into a 1-bit quantizer twice. Under the joint action of the first digital output quantity and the two second digital output quantities, the array capacitors of the disturbance control capacitor array are connected to the corresponding voltages, thereby solving the problem that the suppression effect of the existing subtraction disturbance injection technology on the additional noise caused by the disturbance signal is significantly reduced when the resolution is 1-bit, and the quantization residual randomization effect is good. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 Subtract disturbance injection method for existing sigma-deltaADC; Figure 2 for Figure 1 The residual curve of the subtractive disturbance injection method is shown; Figure 3 For existing signal-related dither injection methods; Figure 4 for Figure 3 Residual curves for the methods shown; Figure 5 A circuit diagram of a disturbance injection circuit according to an embodiment of the present invention; Figure 6 This is a residual curve of a disturbance injection circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0019] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0020] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0021] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspect described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0022] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0023] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the examples can be practiced without these specific details.

[0024] The existing subtractive disturbance injection technology will greatly reduce the effect of suppressing the additional noise caused by dither when the quantizer resolution is 1-bit. To illustrate this problem, Figure 2The residual curve diagram of the 1-bit quantizer after the 2-bit (4 levels) subtractive disturbance injection technique is given. The injection amplitude is {-3 / 8Vr, -1 / 8Vr, 1 / 8Vr, 3 / 8Vr}, and Vr is the half-scale of the quantizer. The black solid line in the figure represents the residual curve of the ideal 1-bit quantizer without dither, and the 4 dotted lines of different shapes correspond to the residual curves of the quantizer output under different levels of dither injection. It can be seen that when the absolute value of the input amplitude exceeds 5 / 8Vr, the residual voltage after using dither will exceed the voltage range of half the least significant bit (LSB), resulting in an increase in quantization noise.

[0025] like Figure 2 As shown, the black solid line corresponds to the residual curve without any injection, so the 1-bit quantizer (i.e., comparator) flips at the input vi=0, and the residual curve jumps at vi=0. When the dither signal is 00, a jitter signal -3 / 8Vr is added to the input signal. At this time, the actual input signal of the 1-bit quantizer is vi-3 / 8Vr, so the original jump point at vi=0 is transferred to 3 / 8Vr, so the residual curve is replaced by a short dash line. Similarly, dither=01, 10, 11 correspond to the amplitudes of the added jitter signal of -1 / 8Vr, 1 / 8Vr, and 3 / 8Vr, respectively, which transfer the jump point at vi=0 to 1 / 8Vr, -1 / 8Vr, and -3 / 8Vr, respectively. The residual curves correspond to Figure 2 The dot line, single point and single short line, double point and single short line.

[0026] For a 1-bit quantizer, the output is 1 or 0, and the digital output value corresponds to 1 or -1 respectively. When jitter is added, the digital output will have decimals. Take the four different injection amounts of -3 / 8Vr, -1 / 8Vr, 1 / 8Vr, 3 / 8Vr as examples, and add 0.75, 0.25, -0.25, -0.75 to the original 1 and 0 outputs. The following is an example: For input Vi=0.3Vr, when no jitter is introduced, because the input Vi>0, the 1-bit quantizer output is 1, and the digital output is 1; the residual voltage is Vi-0.5Vr*1=-0.2Vr.

[0027] When the injection amount is -3 / 8Vr, vi-3 / 8Vr=-0.125Vr, which is less than 0, so the quantizer output is 0, and the digital output is -1 plus +0.75, so the digital output is -0.25; the residual voltage is Vi-0.5Vr*(-1)-3 / 8Vr=0.425Vr. When the injection amount is -1 / 8Vr, vi-1 / 8Vr=0.175Vr, which is greater than 0, so the quantizer output is 1, and the digital output is +0.25 based on 1, so the digital output is 1.25; the residual voltage is Vi-0.5Vr*1-1 / 8Vr=-0.325Vr.

[0028] When the injection amount is 1 / 8Vr, vi+1 / 8Vr=0.425Vr, which is greater than 0, so the quantizer output is 1, and the digital output is -0.25 added to 1, so the digital output is 0.75; the residual voltage is Vi-0.5Vr*1+1 / 8Vr=-0.075Vr.

[0029] When the injection amount is 3 / 8Vr, vi+3 / 8Vr=0.675Vr, which is greater than 0, so the quantizer output is 1, and the digital output is -0.75 added to 1, so the digital output is 0.25; the residual voltage is Vi-0.5Vr*1+3 / 8Vr=-0.175Vr.

[0030] In summary, for a fixed input vi = 0.3Vr, when no jitter is introduced, the output of the 1-bit quantizer is fixed to 1, and when 4 levels of jitter are introduced, the 1-bit quantizer has four possibilities: -0.25, 1.25, 0.75, and 0.25. The residual voltage is fixed to 0.2Vr when no jitter is introduced, and when 4 levels of jitter are introduced, there are four possibilities: 0.425Vr, -0.325Vr, -0.075Vr, and -0.175Vr. The values ​​of these four residual voltages correspond to Figure 2 The y coordinate values ​​of the four dotted lines at vi=0.3Vr. It should be noted that when the size of Vi is close to -Vr or Vr, Figure 2 It can be seen that the value of the residual voltage exceeds ±0.5Vr. At this time, the quantization noise of the 1-bit quantizer increases, deteriorating the SQNR.

[0031] Figure 3 An existing dither injection technique suitable for sigma-delta ADC with 1-bit quantizer is presented. Compared with the traditional subtractive perturbation injection scheme, Figure 3 The scheme shown in the figure additionally adds comparator CMP2, digital domain comparator DCMP1 and two switches. Comparator CMP1 and comparator CMP2 compare the quantizer input point with and without dither, and the comparison result is sent to comparator DCMP1 in the digital domain. When the output results of comparator CMP1 and comparator CMP2 are the same, the dither function is turned off, and when the output results of comparator CMP1 and comparator CMP2 are different, the dither function is turned on.

[0032] The residual voltage curve corresponding to this scheme is as follows Figure 4 As shown, the following uses 4 levels of dither injection as an example to explain the scheme. It can be seen that when the dither value is less than zero, only two levels of dither functions are turned on for input signals less than 0, and when the dither value is greater than zero, only the other two levels of dither functions are turned on for input signals greater than 0. Although this method can avoid the problem of increased quantization noise caused by the residual voltage exceeding one quantization LSB voltage, the dither method is related to the input signal and for a given input voltage, the number of dither levels is halved, which leads to a weakening of the randomization effect introduced by the dither.

[0033] Based on this, this specification embodiment proposes a processing solution: Figure 5 As shown, a disturbance injection circuit of the present invention, the disturbance unit injects a disturbance signal into the first injection capacitor C5 and the second injection capacitor C6, the disturbance signal and the input signal Vin are summed in the signal domain to obtain the first input voltage of the comparator, the comparator compares the first input voltage with the first comparator threshold for the first time, and outputs a first comparison result Q1, and then stores the first comparison result Q1 in the register; then the disturbance unit injects a disturbance signal into the comparison capacitor C4 and sums the disturbance signal injected into the comparison capacitor C4 and the input signal Vin in the signal domain to obtain the second input voltage of the comparator, the comparator compares the second input voltage with the second comparator threshold for the second time and outputs a second comparison result Q2, and then stores the second comparison result Q2 in the register, and finally the register outputs two second digital output quantities according to the first comparison result Q1 and the second comparison result Q2, so that the second digital output quantity cooperates with the first digital output Ddi quantity output by the disturbance unit to adjust the connection of the array capacitors in the capacitor array DWA in the loop filter, so that the quantizer can ensure that the residual voltage is less than a least significant bit within the full input range. The present invention has the advantages of small quantization noise and good quantization residual randomization effect at the cost of introducing extremely small additional hardware.

[0034] The present application is described in detail below in conjunction with the accompanying drawings.

[0035] Example 1 This embodiment takes 2-bit 4-level disturbance signal injection as an example to explain the present application in detail, and the 4-level disturbance signals are {-3 / 8Vr, -1 / 8Vr, 1 / 8Vr, 3 / 8Vr} respectively.

[0036] Here, 2-bit is the number of bits of the injection signal. In the example, a total of 4 levels of injection amount are used, so it can be written as 2-bit. The values ​​of the 4 levels of disturbance signals corresponding to the 2-bit disturbance signals are {-3 / 8Vr, -1 / 8Vr, 1 / 8Vr, 3 / 8Vr} respectively.

[0037] like Figures 5 and 6 As shown, a disturbance injection circuit of the present invention is applied to an analog-to-digital converter with a 1-bit quantizer, especially a sigma-delta analog-to-digital converter with a 1-bit quantizer. The disturbance injection circuit includes a loop filter 10 with a first-stage integrator, a 1-bit quantizer 20 and a disturbance unit 30. The loop filter 10 is connected to the 1-bit quantizer 20. The first-stage integrator includes a first sampling capacitor C1 and a capacitor array DWA. The first sampling capacitor C1 is used to obtain an input signal Vin. The disturbance unit 30 is used to output a first digital output quantity.

[0038] The first sampling capacitor C1 can be connected to the input signal Vin or the common mode voltage Vcm through a corresponding switch.

[0039] The quantization range of the 1-bit quantizer 20 is {-Vr, Vr}.

[0040] The loop filter 10 is used to obtain an input signal Vin and amplify and filter the input signal Vin.

[0041] The disturbance unit 30 is used to add a disturbance signal to the input signal Vin. As mentioned above, the disturbance signal injection amount of this embodiment includes four levels {-3 / 8Vr, -1 / 8Vr, 1 / 8Vr, 3 / 8Vr}.

[0042] Specifically, the 1-bit quantizer 20 includes a second sampling capacitor C3, a comparison capacitor C4, a first injection capacitor C5, a second injection capacitor C6, a comparator 21 and a register 22; the bottom plate of the second sampling capacitor C3 can be connected to the output end of the loop filter 10 and the common mode voltage Vcm through the sampling switch K4, the bottom plate of the comparison capacitor C4, the bottom plate of the first injection capacitor C5, and the bottom plate of the second injection capacitor C6 can be connected to the positive reference voltage Vrefp, the negative reference voltage Vrefn or the common mode voltage Vcm through the corresponding switches, and can obtain the disturbance signal injected by the disturbance unit 30 through the corresponding switches; the second sampling capacitor C3 can be connected to the output end of the loop filter 10 and the common mode voltage Vcm through the sampling switch K4, the bottom plate of the comparison capacitor C4, the bottom plate of the first injection capacitor C5, and the bottom plate of the second injection capacitor C6 can be connected to the positive reference voltage Vrefp, the negative reference voltage Vrefn or the common mode voltage Vcm through the corresponding switches, and can obtain the disturbance signal injected by the disturbance unit 30 through the corresponding switches; The top plate of capacitor C3, the top plate of comparison capacitor C4, the top plate of first injection capacitor C5, and the top plate of second injection capacitor C6 are all connected to the positive input terminal of comparator 21, the negative input terminal of comparator 21 is grounded, and the positive input terminal of comparator 21 is connected to the negative input terminal of comparator 21 through comparator input switch K3, the output terminal of comparator 21 is connected to register 22, and register 22 outputs the corresponding second digital output according to the output result of comparator 21. After the second digital output and the first digital output Ddi are superimposed, the array capacitors in control capacitor array DWA are connected to the positive reference voltage Vrefp or the negative reference voltage Vrefn.

[0043] The second sampling capacitor C3 is used to sample the output of the loop filter 10 . The output of the loop filter 10 is mainly the input signal Vin after being operationally amplified and filtered.

[0044] Wherein, the bottom plate of the second sampling capacitor C3 can be connected to the output end of the loop filter 10 or the common mode voltage Vcm according to requirements under the action of the sampling switch K4.

[0045] Specifically, the comparison capacitor C4 is connected to the positive reference voltage Vrefp, the negative reference voltage Vrefn or the common mode voltage Vcm through the comparison switch K5; the first injection capacitor C5 is connected to the positive reference voltage Vrefp, the negative reference voltage Vrefn or the common mode voltage Vcm through the first injection switch K6; the second injection capacitor C6 is connected to the positive reference voltage Vrefp, the negative reference voltage Vrefn or the common mode voltage Vcm through the second injection switch K7; the disturbance unit 30 injects the first disturbance signal di into the second injection capacitor C6 through the second injection switch K7 <0> The disturbance unit 30 injects the second disturbance signal di into the comparison capacitor C4 and the first injection capacitor C5 through the comparison switch K5 and the first injection switch K6 respectively. <1> .

[0046] Among them, the switches described in this application can all switch the corresponding capacitors to different voltages according to requirements.

[0047] For example, the comparison switch K5 can control the comparison capacitor C4 to be connected to any one of the positive reference voltage Vrefp, the negative reference voltage Vrefn, and the common mode voltage Vcm.

[0048] Furthermore, the comparator 21 generates a signal according to the input signal Vin, the second disturbance signal di injected into the first injection capacitor C5, and the input signal Vin. <1> , the first disturbance signal di injected into the second injection capacitor C6 <0> Output the first comparison result Q1; according to the input signal Vin, the second disturbance signal di injected into the comparison capacitor C4 <1> Output the second comparison result Q2; the register 22 can store the first comparison result Q1 and the second comparison result Q2, and output two second digital output quantities according to the first comparison result Q1 and the second comparison result Q2.

[0049] The first injection capacitor C5 is injected into the second disturbance signal di <1> When the second disturbance signal di <1> When the first injection capacitor C5 is connected to the positive reference voltage Vrefp through the first injection switch K6, the second injection capacitor C6 is connected to the positive reference voltage Vrefp when the first disturbance signal di <0> When the first disturbance signal di <0> When V is equal to 1, the second injection capacitor C6 is connected to the positive reference voltage Vrefp through the second injection switch K7.

[0050] Among them, in the second disturbance signal di <1> When the second disturbance signal di <1> When it is equal to 1, the comparison capacitor C4 is connected to the negative reference voltage Vrefn through the comparison switch K5.

[0051] Specifically, the second disturbance signal di is injected into the first injection capacitor C5 by the disturbance unit 30. <1> The second injection capacitor C6 is injected with the first disturbance signal di by the disturbance unit 30. <0> Afterwards, the first injection capacitor C5 injects the second disturbance signal di <1> Added to the input signal Vin, the second injection capacitor C6 converts the first disturbance signal di <0> Added to the input signal Vin, the first disturbance signal di <0> , the second disturbance signal di <1> The first input voltage of the comparator 21 is obtained by summing the first input voltage with the input signal Vin in the signal domain. At this time, the comparator 21 compares the first input voltage with the first comparator 21 threshold and outputs a first comparison result Q1.

[0052] The second disturbance signal di is injected into the comparison capacitor C4 by the disturbance unit 30. <1> After that, the input signal Vin and the second disturbance signal di injected into the comparison capacitor C4 <1> The sum is calculated in the signal domain, and the comparator 21 obtains the second input voltage. After the comparator 21 compares the second input voltage with the second comparator 21 threshold, the comparator 21 outputs a second comparison result Q2.

[0053] The threshold of the second comparator 21 is determined according to the second disturbance signal di injected into the comparison capacitor C4. <1> Make adjustments.

[0054] Therefore, the comparator 21 mainly compares the acquired input voltage with the corresponding comparator 21 threshold to obtain a comparison result, and then inputs the comparison result into the register 22 for temporary storage.

[0055] The register 22 is used to output two second digital output quantities corresponding to the two output results of the comparator 21 .

[0056] Since the output value of the comparator 21 is usually 1 or 0, the register 22 can output a corresponding second digital output value according to the comparison result of the comparator 21 .

[0057] Specifically, when the output result of the comparator 21 is 1, the output of the register 22 is 0; when the output of the comparator 21 is 0, the output of the register 22 is -1.

[0058] Furthermore, the capacitor array DWA includes a plurality of array capacitors C21 - C27 connected in parallel, and each array capacitor can be connected to the positive reference voltage Vrefp, the negative reference voltage Vrefn or the common mode voltage Vcm through a corresponding switch.

[0059] The array capacitor can adjust the number of connections between the array capacitor and the positive reference voltage Vrefp or the negative reference voltage Vrefn according to the value obtained by superimposing the two second digital output quantities and the first digital output Ddi quantity.

[0060] Furthermore, the loop filter 10 also includes an operational amplifier OTA, an integrating capacitor CINT and a back-end integrated unit, the positive input terminal of the operational amplifier OTA is grounded, the negative input terminal is respectively connected to the first sampling capacitor C1 and the capacitor array DWA, and the positive input terminal of the operational amplifier OTA is connected to the negative input terminal of the operational amplifier OTA through a corresponding switch; the integrating capacitor CINT is connected between the negative input terminal of the operational amplifier OTA and the output terminal of the operational amplifier OTA; the input terminal of the back-end integrated unit is connected to the output terminal of the operational amplifier OTA, and the output terminal of the back-end integrated unit is connected to the second sampling capacitor C3.

[0061] The disturbance signal injection circuit for the 1-bit quantizer 20 proposed in this embodiment injects the disturbance signal twice at the 1-bit quantizer and injects the disturbance signal once at the first-stage integrator of the loop filter through the D / A capacitor array. At the cost of introducing very little additional hardware circuits, the problem of the quantization residual exceeding one quantization LSB voltage caused by the traditional subtraction disturbance injection is solved, and at the same time, it has the advantage of good randomization effect.

[0062] Example 2 This embodiment provides a disturbance injection method, which is applied to the disturbance injection circuit as described in any one of the embodiments 1, including: Step S102, the bottom plate of the capacitor array DWA, the bottom plate of the comparison capacitor C4, the bottom plate of the first injection capacitor C5, and the bottom plate of the second injection capacitor C6 are all connected to the common mode voltage Vcm, and the input signal Vin is sampled through the first sampling capacitor C1, and the output of the loop filter 10 is sampled through the second sampling capacitor C3.

[0063] Specifically, in the first-stage integrator part, the switch between the positive input terminal and the negative input terminal of the operational amplifier OTA and the first switch are all closed, the bottom plate of the first sampling capacitor C1 tracks the input signal Vin, and the bottom plates of the array capacitors in the capacitor array DWA are all connected to the common-mode voltage Vcm; in the 1-bit quantizer 20 part, the comparator input switch K3 and the sampling switch K4 are closed, the bottom plate of the second sampling capacitor C3 tracks the output of the loop filter 10, and the bottom plates of the comparison capacitor C4, the first injection capacitor C5 and the second injection capacitor C6 are connected to the common-mode voltage Vcm.

[0064] Then the switch between the positive input terminal and the negative input terminal of the operational amplifier OTA and the comparator input switch K3 are simultaneously opened to complete the sampling of the input signal Vin by the first sampling capacitor C1 and the sampling of the output of the loop filter 10 by the second sampling capacitor C3.

[0065] The disturbance unit 30 outputs a 2-bit disturbance signal di<1:0> and a corresponding first digital output Ddi. The corresponding relationship between the value of the disturbance signal di<1:0>, the voltage injection amount of the disturbance signal di<1:0> and the first digital output Ddi is shown in the following table:

[0066] Wherein, Vr is the difference between the positive reference voltage Vrefp and the negative reference voltage Vrefn.

[0067] Step S104, connecting the bottom plate of the first sampling capacitor C1 to the common mode voltage Vcm, and connecting the bottom plate of the first injection capacitor C5 and the bottom plate of the second injection capacitor C6 to the positive reference voltage Vrefp or the negative reference voltage Vrefn according to the disturbance signal injected into the first injection capacitor C5 and the second injection capacitor C6, so as to sum the input signal Vin, the disturbance signal injected into the first injection capacitor C5 and the disturbance signal injected into the second injection capacitor C6 in the signal domain and obtain the first input voltage.

[0068] As shown in the figure, in the first stage integrator, the bottom plate of the first sampling capacitor C1 is connected to the common mode voltage Vcm, and at the same time in the 1-bit quantizer 20 part, the bottom plates of the first injection capacitor C5 and the second injection capacitor C6 are respectively connected according to di <1> and <0> The value of is connected to the positive reference voltage Vrefp or the negative reference voltage Vrefn.

[0069] The connection rule of the bottom plates of the first injection capacitor C5 and the second injection capacitor C6 is as follows: The second disturbance signal di injected into the first injection capacitor C5 <1> When the value of is 0, the bottom plate of the first injection capacitor C5 and the bottom plate of the second injection capacitor C6 are connected to the negative reference voltage Vrefn; the first disturbance signal di injected into the second injection capacitor C6 <0> When the value of is 1, the bottom plate of the first injection capacitor C5 and the bottom plate of the second injection capacitor C6 are connected to the positive reference voltage Vrefp.

[0070] By operating the first injection capacitor C5 and the second injection capacitor C6 in step S104, the sum of the input signal Vin and the disturbance signal {-3 / 8Vr, -1 / 8Vr, 1 / 8Vr, 3 / 8Vr} in the signal domain can be achieved. At this time, the first input voltage of the comparator 21 is Vi-3 / 8Vr, Vi-1 / 8Vr, Vi+1 / 8Vr, Vi+3 / 8Vr.

[0071] Step S106 , the comparator 21 obtains the first input voltage, and compares it with the threshold of the first comparator 21 , obtains a first comparison result Q1 , and sends the first comparison result Q1 to the register 22 for temporary storage.

[0072] After the first comparison, the comparator 21 outputs a first comparison result Q1. When the input of the comparator 21 is greater than zero, the first comparison result Q1 is output as 1, otherwise the first comparison result Q1 is output as 0, and then the first comparison result Q1 is sent to the register 22 for temporary storage.

[0073] Step S108 , the bottom plate of the comparison capacitor C4 is connected to the positive reference voltage Vrefp or the negative reference voltage Vrefn according to the value of the corresponding disturbance signal, so as to obtain the second input voltage by summing the input signal Vin and the disturbance signal injected into the comparison capacitor C4 in the signal domain.

[0074] The bottom plate of the comparison capacitor C4 is connected to the second disturbance signal di <1> The value is connected to the positive reference voltage Vrefp or the negative reference voltage Vrefn, and the rules are as follows: The second disturbance signal di injected into the comparison capacitor C4 <1> When the value of is 1, the bottom plate of the comparison capacitor C4 is connected to the negative reference voltage Vrefn; The second disturbance signal di injected into the comparison capacitor C4 <1> When the value of is 0, the bottom plate of the comparison capacitor C4 is connected to the positive reference voltage Vrefp.

[0075] In the second disturbance signal di <1> =1, indicating that the injection amount is 1 / 8Vr or 3 / 8Vr, and the residual curve is Figure 2 In the single point single short line, and double point single short line, step S108 connects the bottom plate of the comparison capacitor C4 to the negative reference voltage Vrefn, which is equivalent to introducing an injection amount of -Vr at the comparator input again, forming Figure 6 The above two dotted lines jump twice at 7 / 8Vr and 5 / 8Vr.

[0076] When the second disturbance signal di <1> =0, indicating that the injection amount is -1 / 8Vr or -3 / 8Vr, and the residual curve is Figure 2 The dotted line and short line in the figure, in this step, the bottom plate of c4 is connected to the positive reference voltage Vrefp, which is equivalent to introducing the injection amount of +Vr at the input of the comparator again, forming Figure 6 The two dotted lines above jump twice at -7 / 8Vr and -5 / 8Vr.

[0077] After the operation on the comparison capacitor C4 in step S108, corresponding to the injection amounts of {-3 / 8Vr, -1 / 8Vr, 1 / 8Vr, 3 / 8Vr}, the input voltages of the comparator are Vi-3 / 8Vr+Vr=Vi+5 / 8Vr, Vi-1 / 8Vr+Vr=Vi+7 / 8Vr, Vi+1 / 8Vr-Vr=Vi-7 / 8Vr, and Vi+3 / 8Vr-Vr=Vi-5 / 8Vr.

[0078] In step S110 , the comparator 21 obtains the second input voltage, and compares it with the threshold of the second comparator 21 to obtain a second comparison result Q2 , and sends the second comparison result Q2 to the register 22 for temporary storage.

[0079] In this step, the comparator 21 performs a second comparison and outputs a second comparison result Q2 . If the input of the comparator 21 is greater than zero, the second comparison result Q2 is equal to 1. Otherwise, the second comparison result Q2 is equal to 0. The second comparison result Q2 is temporarily stored in the register 22 .

[0080] In step S112 , the register 22 outputs two second digital output quantities according to the first comparison result Q1 and the second comparison result Q2 .

[0081] The register 22 converts the stored first comparison result Q1 and the second comparison result Q2 into two second digital output quantities (Do1, Do2), respectively, and ensures that the two second digital output quantities are output synchronously in time.

[0082] Specifically, when the comparison result is equal to 1, the second digital output quantity is equal to 1, and when the comparison result is equal to 0, the second digital output quantity is equal to -1.

[0083] Wherein, Do1 is a value corresponding to the first comparison result Q1, and Do2 is a value corresponding to the second comparison result Q2.

[0084] Step S114, superimposing the two second digital outputs with the first digital output Ddi output by the disturbance unit 30 to obtain a third digital output, and adjusting the bottom plate of the array capacitor in the capacitor array DWA to be connected to the positive reference voltage Vrefp or the negative reference voltage Vrefn according to the third digital output.

[0085] The two second digital output quantities and the first digital output quantity Ddi are summed to form a third digital output Dout, and the bottom plate of the array capacitor is connected to a positive reference voltage Vrefp or a negative reference voltage Vrefn according to the value of the third digital output Dout.

[0086] When the output of the loop filter 10 is within the range of the 1-bit quantizer, the dither injection technology proposed in the present invention can ensure that the value of the third digital output Dout is only one of the eight values ​​{-1.75, -1.25, -0.75, -0.25, 0.25, 0.75, 1.25, 1.75}. The relationship between the connection mode between the bottom plates of the array capacitors C21-C27 and Vrefp, Vrefn in the capacitor array DWA and Dout is shown in the following table:

[0087] When the first comparison result Q1=1 or 0, the second digital output D1 corresponding to the first comparison result Q1=1 or -1; when the second comparison result Q2=1 or 0, the second digital output D2 corresponding to the second comparison result Q2 is 1 or -1; and according to the agreement of the first step, when dither=00, 01, 10, 11, the digital output Ddi corresponding to dither is 0.75, 0.25, -0.25, -0.75 respectively. The final digital output is D1+D2+Ddi, which will be sent to the subsequent digital extraction filter as the output of the modulator.

[0088] Here are some examples: When Vi=0.3Vr, when dither=01, the result of the first step comparison of the quantizer is Q1=1, so D1=1, the result of the second step comparison of the quantizer is Q2=0, so D2=-1, the first digital output Ddi corresponding to dither is 0.25, so the third digital output is 1-1+0.25=0.25; 3 bottom plates in C21~C27 are connected to the negative reference voltage Vrefn, and 4 bottom plates are connected to the positive reference voltage Vrefp.

[0089] When Vi=0.9Vr, when dither=11, the result of the first step comparison of the quantizer is Q1=1, so D1=1, the result of the second step comparison of the quantizer is Q2=1, so D2=1, the first digital output corresponding to dither is Ddi=-0.75, so the third digital output is 1+1-0.75=1.25; one bottom plate in C21~C27 is connected to Vrefn, and six bottom plates are connected to Vrefp.

[0090] When Vi=0.9Vr, when dither=10, the result of the first step comparison of the quantizer is Q1=1, so D1=1, the result of the second step comparison of the quantizer is Q2=1, so D2=1, the first digital output corresponding to dither is Ddi=-0.25, so the third digital output is 1+1-0.25=1.75; all the bottom plates of C21~C27 are connected to Vrefp.

[0091] Figure 6 The residual voltage curve of the 1-bit quantizer 20 after adopting the dither injection technology proposed in the present invention is given. It can be seen that within the full-scale input range of (-Vr, Vr), the residual voltage is less than one quantization LSB, and for any input within the scale range, the four levels of dither are effective and have nothing to do with the size of the input signal Vin, and the randomization effect introduced by dither is excellent.

[0092] The dither injection method for the 1-bit quantizer 20 proposed in the present invention solves the problem that the quantization residual caused by the traditional subtraction disturbance injection exceeds one quantization LSB voltage at the cost of introducing very little additional hardware circuits, and has the advantage of good randomization effect.

[0093] In this specification, the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the product embodiment described later, since it corresponds to the method, the description is relatively simple, and the relevant parts can be referred to the partial description of the system embodiment.

[0094] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A disturbance injection circuit, characterized in that: The disturbance injection circuit comprises a capacitor array of a first-stage integrator in a loop filter, a 1-bit quantizer and a disturbance unit, the output of the loop filter is connected to the 1-bit quantizer, and the disturbance unit is used to output a first digital output quantity; The 1-bit quantizer includes a second sampling capacitor, a comparison capacitor, a first injection capacitor, a second injection capacitor, a comparator and a register; The bottom plate of the second sampling capacitor can be connected to the output terminal and the common mode voltage of the loop filter respectively through a sampling switch, and the bottom plate of the comparison capacitor, the bottom plate of the first injection capacitor, and the bottom plate of the second injection capacitor can all be connected to a positive reference voltage, a negative reference voltage, or a common mode voltage through corresponding switches, and can all obtain the disturbance signal injected by the disturbance unit through the corresponding switches; The top plate of the second sampling capacitor, the top plate of the comparison capacitor, the top plate of the first injection capacitor, and the top plate of the second injection capacitor are all connected to the positive input terminal of the comparator, the negative input terminal of the comparator is grounded, and the positive input terminal of the comparator is connected to the negative input terminal of the comparator through a comparator input switch, the output terminal of the comparator is connected to the register, and the register outputs a corresponding second digital output according to the output result of the comparator, and the second digital output and the first digital output are superimposed to control the array capacitor in the capacitor array to be connected to a positive reference voltage or a negative reference voltage.

2. The disturbance injection circuit according to claim 1, characterized in that: The comparison capacitor is connected to the positive reference voltage, the negative reference voltage or the common mode voltage through a comparison switch; The first injection capacitor is connected to the positive reference voltage, the negative reference voltage or the common mode voltage through a first injection switch; The second injection capacitor is connected to the positive reference voltage, the negative reference voltage or the common mode voltage through a second injection switch; The disturbance unit injects a first disturbance signal into the second injection capacitor through the second injection switch, and injects a second disturbance signal into the comparison capacitor and the first injection capacitor through the comparison switch and the first injection switch respectively; The comparator outputs a first comparison result according to an input signal, a second disturbance signal injected into the first injection capacitor, and the first disturbance signal injected into the second injection capacitor, and outputs a second comparison result according to the input signal and the second disturbance signal injected into the comparison capacitor; The register stores the first comparison result and the second comparison result, and outputs two second digital output quantities according to the first comparison result and the second comparison result.

3. The disturbance injection circuit according to claim 2, characterized in that: When the second disturbance signal is equal to 0, the first injection capacitor is connected to the negative reference voltage through the first injection switch; when the second disturbance signal is equal to 1, the first injection capacitor is connected to the positive reference voltage through the first injection switch; When the first disturbance signal is equal to 0, the second injection capacitor is connected to the negative reference voltage through the second injection switch; when the first disturbance signal is equal to 1, the second injection capacitor is connected to the positive reference voltage through the second injection switch.

4. The disturbance injection circuit according to claim 2, characterized in that: When the second disturbance signal is equal to 0, the comparison capacitor is connected to the positive reference voltage through the comparison switch, and when the second disturbance signal is equal to 1, the comparison capacitor is connected to the negative reference voltage through the comparison switch.

5. The disturbance injection circuit according to claim 2, characterized in that: When the comparator outputs a result of 1, the register outputs 0; when the comparator outputs a result of 0, the register outputs -1.

6. The disturbance injection circuit according to any one of claims 1 to 5, characterized in that: The capacitor array includes a plurality of array capacitors connected in parallel, and each of the array capacitors can be connected to the positive reference voltage, the negative reference voltage or the common mode voltage through a corresponding array switch.

7. The disturbance injection circuit according to claim 6, characterized in that: The loop filter further comprises: An operational amplifier, wherein the positive input terminal of the operational amplifier is grounded, the negative input terminal is connected to the first sampling capacitor and the capacitor array respectively, and the positive input terminal of the operational amplifier is connected to the negative input terminal of the operational amplifier through a corresponding operational amplifier input switch; an integrating capacitor connected between the negative input terminal of the operational amplifier and the output terminal of the operational amplifier; A back-end integrated unit, wherein the input end of the back-end integrated unit is connected to the output end of the operational amplifier, and the output end of the back-end integrated unit is connected to the second sampling capacitor.

8. A disturbance injection method, characterized in that: The disturbance injection circuit as claimed in any one of claims 1 to 7 comprises: Connecting the bottom plate of the capacitor array, the bottom plate of the comparison capacitor, the bottom plate of the first injection capacitor, and the bottom plate of the second injection capacitor to a common mode voltage, sampling the input signal through the first sampling capacitor, and sampling the output of the loop filter through the second sampling capacitor; Connecting the bottom plate of the first sampling capacitor to the common mode voltage, and connecting the bottom plate of the first injection capacitor and the bottom plate of the second injection capacitor to a positive reference voltage or a negative reference voltage according to the disturbance signal injected into the first injection capacitor and the second injection capacitor, so as to sum the input signal, the disturbance signal injected into the first injection capacitor, and the disturbance signal injected into the second injection capacitor in the signal domain and obtain a first input voltage; The comparator obtains the first input voltage, compares it with the first comparator threshold, obtains a first comparison result, and sends the first comparison result to a register for temporary storage; The bottom plate of the comparison capacitor is connected to a positive reference voltage or a negative reference voltage according to the value of the corresponding disturbance signal, so as to achieve the summation of the input signal and the disturbance signal injected into the comparison capacitor in the signal domain to obtain a second input voltage; The comparator obtains the second input voltage, compares it with the second comparator threshold, obtains a second comparison result, and sends the second comparison result to the register for temporary storage; The register outputs two second digital output quantities correspondingly according to the first comparison result and the second comparison result; The two second digital outputs are superimposed on the first digital output outputted by the disturbance unit to obtain a third digital output, and the bottom plate of the array capacitor in the capacitor array is adjusted to be connected to the positive reference voltage or the negative reference voltage according to the third digital output.

9. The disturbance injection method according to claim 8, characterized in that: The step of connecting the bottom plate of the first injection capacitor and the bottom plate of the second injection capacitor to the positive reference voltage or the negative reference voltage according to the disturbance signal injected into the first injection capacitor and the second injection capacitor comprises: When the value of the disturbance signal injected into the first injection capacitor and the second injection capacitor is 0, the bottom plate of the first injection capacitor and the bottom plate of the second injection capacitor are connected to the negative reference voltage; When the value of the disturbance signal injected into the first injection capacitor and the second injection capacitor is 1, the bottom plate of the first injection capacitor and the bottom plate of the second injection capacitor are connected to the positive reference voltage.

10. The disturbance injection method according to claim 8, characterized in that: The bottom plate of the comparison capacitor is connected to a positive reference voltage or a negative reference voltage according to the value of the corresponding disturbance signal, including: When the value of the disturbance signal injected into the comparison capacitor is 1, the bottom plate of the comparison capacitor is connected to the negative reference voltage; When the value of the disturbance signal injected into the comparison capacitor is 0, the bottom plate of the comparison capacitor is connected to the positive reference voltage.

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