Low-complexity radiation-proof TBEC codec circuit

Abstract

The invention provides a low-complexity radiation-proof TBEC codec circuit, and provides a TBEC codec multiplexing method controlled by an enable signal according to the characteristics that a traditional linear block code codec is subjected to low-complexity optimization and partial exclusive-OR logic operation circuits are the same in the encoding and decoding processes. And the circuit area and the resource consumption of the TBEC codec are effectively reduced under the condition of ensuring the error correction function. Through verification, the coding and decoding multiplexing method can be expanded to other linear block codes of different types.

Description

Technical Field

[0001] The present invention relates to the technical field of radiation-resistant ECC reinforcement design, and in particular to a low-complexity radiation-resistant TBEC codec circuit. Background Art

[0002] In space exploration and development, onboard microprocessors will face a complex space radiation environment. Radiated particles from the space radiation environment will cause single event upset (SEU) problems in storage units. Although SEU, as a soft error, will not cause permanent damage to storage devices, its probability of occurrence is higher than other types of faults, and because of the storage of erroneous information, it will cause temporary failures or even failure of electronic equipment. ECC (Error Correction Codes) technology is a system-level reinforcement technology specifically proposed for the single event upset problem of memory. It adds a certain number of redundant bits on the basis of the original information bits, and realizes the detection and correction of soft errors in the memory by encoding and decoding the stored information. In terms of system-level reinforcement, the memory usually uses Hamming code as a single error correction and double error detection code (SEC-DED), which can correct one-bit errors and detect two-bit errors, but cannot correct errors of more than two bits. With the continuous advancement of CMOS technology, multiple bit upsets (MBU) in memory are detected more and more frequently. Therefore, error correction codes with stronger correction capabilities are needed to reinforce and protect the memory, such as RS code, BCH code and matrix code. However, the encoding and decoding process will become more complicated, which will result in higher area, power consumption and latency of the memory.

[0003] Linear block codes are a type of error correction codes that protect packet data. They are suitable for protecting information stored in memory. Their coding characteristics can be defined by their generator matrix and parity check matrix. The encoding and decoding processes can be derived through the corresponding matrix multiplication operations. Due to the regular coding structure and the universal syndrome decoding method, the construction process of the parity check matrix of linear block codes can be realized with the help of search algorithms and automated design can be achieved. TBEC code is a powerful linear block code that can correct 3-bit burst errors, including 4 error modes. Current research mainly expands its functions to reduce its redundancy, and there is little research on the circuit structure of TBEC codecs. Therefore, when designing TBEC codecs, it is necessary to consider the circuit area and resource consumption, so as to design a TBEC codec with low complexity and excellent performance.

[0004] Therefore, it is necessary to propose a new technical solution to improve the above technical problems. Summary of the invention

[0005] In view of the defects in the prior art, an object of the present invention is to provide a low-complexity radiation-resistant TBEC codec circuit.

[0006] A low-complexity radiation-resistant TBEC codec circuit provided by the present invention includes: a data selection unit, a codec multiplexing unit, an error mode and error position confirmation unit, an error correction unit, and an error correction capability verification unit;

[0007] The data selection unit is connected to the codec multiplexing unit, the codec multiplexing unit is connected to the error mode and error position confirmation unit, the error mode and error position confirmation unit is connected to the error correction unit, and the error correction unit is connected to the error correction capability verification unit.

[0008] Preferably, the data selection unit is used to select input data;

[0009] The encoder / decoder multiplexing unit includes a data initialization module and a redundant bit Ci / syndrome S operation module, wherein the data initialization module initializes data according to the state of an enable signal En and sets different C[6:0] initial values ​​in an encoding state or a decoding state; the redundant bit Ci / syndrome S operation module calculates redundant bits Ci in an encoding state and calculates syndrome S in a decoding state by using an exclusive OR logic operation;

[0010] The error mode and error position confirmation unit is used to confirm the error mode and error position;

[0011] The error correction unit corrects the error according to the error mode and error position information;

[0012] The error correction capability verification unit verifies whether the error-corrected data is correct.

[0013] Preferably, when the enable signal En=0, the circuit is in an encoding state, selects to input 16 pre-coded data bits, passes through a coding and decoding multiplexing unit, and outputs 23 bits of coded data to be stored in a memory; when the enable signal En=1, the circuit is in a decoding state, selects to input 23 bits of data after a single particle flip occurs, passes through a coding and decoding multiplexing unit, an error mode and error position confirmation unit, an error correction unit, and an error correction capability verification unit, and outputs 16 correct data bits.

[0014] Preferably, the data initialization module initializes the data in the register to 0 in the encoding state, and initializes the data in the register to the 23-bit single-event upset data input from the previous level circuit in the decoding state.

[0015] Preferably, in the encoding state, the redundant bit Ci / syndrome S operation module uses 16-bit pre-coded data D[15:0] and C[6:0] data initialized to 0 to obtain 7-bit redundant bits C_out[22:16] through an exclusive OR logic operation; in the decoding state, the redundant bit Ci / syndrome S operation module uses 23-bit single-particle flipped data D_error[22:0] and C[6:0] data initialized to D_error[22:16] to obtain the 7-bit syndrome S[6:0] through an exclusive OR logic operation.

[0016] Preferably, the XOR logic operation complies with the parity check matrix regulation in the linear block code.

[0017] Preferably, the data initialization module is used to initialize data, and determines whether it is in the encoding state or the decoding state by using the En enable signal; if it is in the encoding state, the data in the register will be initialized to 0; if it is in the decoding state, the data in the register will be initialized to the 23-bit data after the single-particle flip occurs input from the previous level circuit.

[0018] Preferably, the redundant bit Ci / syndrome S calculation module calculates the redundant bit Ci or the syndrome S in the encoding state or the decoding state respectively by using the data initialized by the selector through an exclusive OR logic operation; wherein the exclusive OR logic relationship used to generate the 7-bit redundant bit C_out[22:16] when encoding the 16-bit pre-coded data D[15:0] is the same as the exclusive OR logic relationship used to generate the 7-bit syndrome S[6:0] when decoding the 23-bit single-particle flipped data D_error[22:0], and the exclusive OR logic relationship is:

[0019] C_out

[22] =C[6]⊕D

[15] ⊕D

[12] ⊕D

[11] ⊕D[9]⊕D[6]⊕D[1]⊕D[0];

[0020] C_out

[21] =C[5]⊕D

[14] ⊕D

[11] ⊕D

[10] ⊕D[8]⊕D[7]⊕D[6]⊕D[3];

[0021] C_out

[20] =C[4]⊕D

[13] ⊕D

[10] ⊕D[5]⊕D[4]⊕D[1];

[0022] C_out

[19] =C[3]⊕D

[15] ⊕D

[11] ⊕D[7]⊕D[4]⊕D[2];

[0023] C_out

[18] =C[5]⊕D

[14] ⊕D

[10] ⊕D[7]⊕D[3]⊕D[0];

[0024] C_out

[17] =C[1]⊕D

[13] ⊕D[9]⊕D[6]⊕D[4]⊕D[3]⊕D[1];

[0025] C_out

[16] =C[0]⊕D

[12] ⊕D[8]⊕D[5]⊕D[2].

[0026] Preferably, the data initialization module is controlled by the En enable signal, and different C[6:0] initial values ​​are set in the encoding state or the decoding state, and are substituted into the subsequent XOR logic operation to affect the final calculation result of the redundant bit Ci / correction sub-S operation module; when the encoding function is executed, the data initialization module is input with 16-bit pre-coded data D[15:0] and 7-bit "0" data 7'b0, En=0, and the output is C[6:0]=7'b0; when the decoding function is executed, the data initialization module is input with 23-bit single-particle flip data D_error[22:0] and 7-bit "0" data 7'b0, En=1, and the output is C[6:0]=D_error[22:16].

[0027] Preferably, the redundant bit Ci / syndrome S operation module substitutes different C[6:0] initial values ​​set by the previous level circuit in the encoding state or the decoding state into an exclusive OR logic operation to obtain the final calculation result of the redundant bit Ci / syndrome S; when the encoding function is executed, the redundant bit Ci / syndrome S operation module inputs 16-bit pre-encoded data D[15:0] and initialization data C[6:0]=7'b0, and outputs 23-bit encoded data C_out[22:0]; when the decoding function is executed, the redundant bit Ci / syndrome S operation module inputs 23-bit single-particle upset data D_error[22:0] and initialization data C[6:0]=D_error[22:16], and outputs a 7-bit syndrome S<6:0>; wherein the logical operation relationship of all 23 bits of data is as follows:

[0028] The operator XOR logic relationship of the first 7 bits of data C_out[22:16] follows the parity check matrix specification in the linear block code:

[0029]

[0030] Among them, when in the encoding state, C[6], C[5], C[4], C[3], C[2], C[1] and C[0] in all the right-hand expressions in the XOR logic relationship are initialized to 0, and XOR with 0 is equivalent to C[i] not participating in the operation; the remaining D[i] in the right-hand expression respectively corresponds to the value in the input 16-bit pre-coded data D[15:0]; the required 7-bit redundant bits C_out[22:16] are obtained by XOR logic operation, and are combined with the following 16-bit data bits to form a 23-bit coded output C_out[22:0]; when in the decoding state, C[6], C[5], C[4], C[3], C[2] in all the right-hand expressions in the XOR logic relationship are initialized to 0, and XOR with 0 is equivalent to C[i] not participating in the operation; the remaining D[i] in the right-hand expression respectively corresponds to the value in the input 16-bit pre-coded data D[15:0]; the required 7-bit redundant bits C_out[22:16] are obtained by XOR logic operation, and are combined with the following 16-bit data bits to form a 23-bit coded output C_out[22:0]; , C[1] and C[0] correspond to the data initialized to D_error

[22] , D_error

[21] , D_error

[20] , D_error

[19] , D_error

[18] , D_error

[17] and D_error

[16] after the single particle upset occurs; the remaining D[i] in the right formula corresponds to the value of the input 23-bit data D_error[22:0] after the single particle upset occurs; the required syndrome S is obtained by the XOR logic operation, and only the first 7 bits of data C_out[22:16] in the decoding state calculation of C_out are output as the 7-bit syndrome S[6:0];

[0031] The relationship of the last 16 bits of data is as follows: C_out

[15] =D

[15] ; C_out

[14] =D

[14] ; C_out

[13] =D

[13] ; C_out

[12] =D

[12] ; C_out

[11] =D

[11] ; C_out

[10] =D

[10] ; C_out[9]=D[9]; C_ out[8]=D[8]; C_out[7]=D[7]; C_out[6]=D[6]; C_out[5]=D[5]; C_out[4]=D[4]; C_out[3]=D[3]; C_out[2]=D[2]; C_out[1]=D[1]; C_out[0]=D[0].

[0032] Compared with the prior art, the present invention has the following beneficial effects:

[0033] 1. The present invention realizes the TBEC codec multiplexing method based on the same XOR logic operation, and controls the codec to realize the encoding function / decoding function through the enable signal En=“0” / “1”;

[0034] 2. The simulation results show that under the same setting conditions and using the same logic to design the TBEC codec, the LUT of the traditional TBEC codec is 63 and the Total Power is 11.872mW; the LUT of the low-complexity radiation-resistant TBEC codec of the present invention is 39 and the Total Power is 4.784mW; the present invention can effectively reduce the circuit area of ​​the TBEC codec, simplify the circuit structure, and ensure that the error correction capability remains unchanged;

[0035] 3. The codec multiplexing method of the present invention can be extended to other application scenarios of the same type of linear block codes. It is suitable for circuit multiplexing of any codec that implements coding redundant bit calculation and decoding syndrome calculation according to the XOR logic operation specified by the parity check matrix, thereby realizing low-complexity design of linear block code codecs. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0037] Figure 1 is a circuit structure block diagram of the present invention;

[0038] Figure 2 This is a circuit structure diagram of the encoding and decoding multiplexing unit;

[0039] Figure 3 A circuit diagram of the unit for confirming the error mode and error location;

[0040] Figure 4 Schematic diagram of the column vector of the parity check matrix;

[0041] Figure 5 This is the result diagram of encoding function simulation;

[0042] Figure 6 This is the decoding function simulation result diagram;

[0043] Figure 7 This is the functional flow chart of the low-complexity radiation-resistant TBEC codec. DETAILED DESCRIPTION

[0044] The present invention is described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, for those of ordinary skill in the art, several changes and improvements can also be made without departing from the concept of the present invention. These all belong to the protection scope of the present invention.

[0045] Embodiment 1:

[0046] Reference Figure 1 and Figure 2 According to the present invention, a low-complexity radiation-resistant TBEC codec circuit is provided, comprising: a data selection unit, a codec multiplexing unit, an error mode and error position confirmation unit, an error correction unit, and an error correction capability verification unit; the data selection unit is connected to the codec multiplexing unit, the codec multiplexing unit is connected to the error mode and error position confirmation unit, the error mode and error position confirmation unit is connected to the error correction unit, and the error correction unit is connected to the error correction capability verification unit.

[0047] Reference Figure 3 and Figure 4 The data selection unit is used to select input data; the encoder / decoder multiplexing unit includes a data initialization module and a redundant bit Ci / syndrome S operation module, wherein the data initialization module initializes data according to the state of the enable signal En, and sets different C[6:0] initial values ​​in the encoding state or the decoding state; the redundant bit Ci / syndrome S operation module uses an exclusive OR logic operation to calculate the redundant bit Ci in the encoding state and the syndrome S in the decoding state; the error mode and error position confirmation unit is used to confirm the error mode and error position; the error correction unit corrects the error according to the error mode and error position information; the error correction capability verification unit verifies whether the corrected data is correct.

[0048] When the enable signal En=0, the circuit is in the encoding state, selects to input 16 pre-coded data bits, passes through the encoding and decoding multiplexing unit, and outputs 23 bits of encoded data to be stored in the memory; when the enable signal En=1, the circuit is in the decoding state, selects to input 23 bits of data after single-particle flipping, passes through the encoding and decoding multiplexing unit, the error mode and error position confirmation unit, the error correction unit and the error correction capability verification unit, and outputs 16 correct data bits.

[0049] The data initialization module initializes the data in the register to 0 in the encoding state, and initializes the data in the register to the 23-bit data after the single particle flip occurs input from the previous level circuit in the decoding state.

[0050] In the encoding state, the redundant bit Ci / syndrome S operation module uses the 16-bit pre-coded data D[15:0] and the C[6:0] data initialized to 0 to obtain the 7-bit redundant bit C_out[22:16] through an XOR logic operation; in the decoding state, the 23-bit single-particle flip data D_error[22:0] and the C[6:0] data initialized to D_error[22:16] are used to obtain the 7-bit syndrome S[6:0] through an XOR logic operation. The XOR logic operation follows the parity check matrix regulations in the linear block code.

[0051] The data initialization module is used to initialize data. It uses the En enable signal to determine whether it is in the encoding state or the decoding state. If it is in the encoding state, the data in the register will be initialized to 0; if it is in the decoding state, the data in the register will be initialized to the 23-bit data after the single-particle flip occurs input from the previous level circuit.

[0052] The redundant bit Ci / syndrome S operation module calculates the redundant bit Ci or the syndrome S in the encoding state or the decoding state respectively by using the data initialized by the selector through an exclusive OR logic operation; wherein, the exclusive OR logic relationship used to generate the 7-bit redundant bit C_out[22:16] when encoding the 16-bit pre-coded data D[15:0] is the same as the exclusive OR logic relationship used to generate the 7-bit syndrome S[6:0] when decoding the 23-bit single-particle flipped data D_error[22:0], and the exclusive OR logic relationship is:

[0053] C_out

[22] =C[6]⊕D

[15] ⊕D

[12] ⊕D

[11] ⊕D[9]⊕D[6]⊕D[1]⊕D[0];

[0054] C_out

[21] =C[5]⊕D

[14] ⊕D

[11] ⊕D

[10] ⊕D[8]⊕D[7]⊕D[6]⊕D[3];

[0055] C_out

[20] =C[4]⊕D

[13] ⊕D

[10] ⊕D[5]⊕D[4]⊕D[1];

[0056] C_out

[19] =C[3]⊕D

[15] ⊕D

[11] ⊕D[7]⊕D[4]⊕D[2];

[0057] C_out

[18] =C[5]⊕D

[14] ⊕D

[10] ⊕D[7]⊕D[3]⊕D[0];

[0058] C_out

[17] =C[1]⊕D

[13] ⊕D[9]⊕D[6]⊕D[4]⊕D[3]⊕D[1];

[0059] C_out

[16] =C[0]⊕D

[12] ⊕D[8]⊕D[5]⊕D[2].

[0060] The data initialization module is controlled by the En enable signal, and different C[6:0] initial values ​​are set in the encoding state or the decoding state, and are substituted into the subsequent XOR logic operation to affect the final calculation result of the redundant bit Ci / correction sub-S operation module; when the encoding function is executed, the input of the data initialization module is 16-bit pre-coded data D[15:0] and 7-bit "0" data 7'b0, En=0, and the output is C[6:0]=7'b0; when the decoding function is executed, the input of the data initialization module is 23-bit single-particle flip data D_error[22:0] and 7-bit "0" data 7'b0, En=1, and the output is C[6:0]=D_error[22:16].

[0061] Reference Figure 5 and Figure 6 , the redundant bit Ci / syndrome S operation module substitutes the different C[6:0] initial values ​​set by the previous circuit in the encoding state or the decoding state into the XOR logic operation to obtain the final calculation result of the redundant bit Ci / syndrome S; when the encoding function is executed, the redundant bit Ci / syndrome S operation module inputs 16-bit pre-encoded data D[15:0] and the initialization data C[6:0]=7'b0, and outputs 23-bit encoded data C_out[22:0]; when the decoding function is executed, the redundant bit Ci / syndrome S operation module inputs 23-bit single-particle flip data D_error[22:0] and the initialization data C[6:0]=D_error[22:16], and outputs 7-bit syndrome S<6:0>; wherein the logical operation relationship of all 23-bit data is as follows:

[0062] The operator XOR logic relationship of the first 7 bits of data C_out[22:16] follows the parity check matrix specification in the linear block code:

[0063]

[0064] Among them, when in the encoding state, C[6], C[5], C[4], C[3], C[2], C[1] and C[0] in all the right-hand expressions in the XOR logic relationship are initialized to 0, and XOR with 0 is equivalent to C[i] not participating in the operation; the remaining D[i] in the right-hand expression respectively corresponds to the value in the input 16-bit pre-coded data D[15:0]; the required 7-bit redundant bits C_out[22:16] are obtained by XOR logic operation, and are combined with the following 16-bit data bits to form a 23-bit coded output C_out[22:0]; when in the decoding state, C[6], C[5], C[4], C[3], C[2] in all the right-hand expressions in the XOR logic relationship are initialized to 0, and XOR with 0 is equivalent to C[i] not participating in the operation; the remaining D[i] in the right-hand expression respectively corresponds to the value in the input 16-bit pre-coded data D[15:0]; the required 7-bit redundant bits C_out[22:16] are obtained by XOR logic operation, and are combined with the following 16-bit data bits to form a 23-bit coded output C_out[22:0]; , C[1] and C[0] correspond to the data initialized to D_error

[22] , D_error

[21] , D_error

[20] , D_error

[19] , D_error

[18] , D_error

[17] and D_error

[16] after the single particle upset occurs; the remaining D[i] in the right formula corresponds to the value of the input 23-bit data D_error[22:0] after the single particle upset occurs; the required syndrome S is obtained by the XOR logic operation, and only the first 7 bits of data C_out[22:16] in the decoding state calculation of C_out are output as the 7-bit syndrome S[6:0];

[0065] The relationship of the last 16 bits of data is as follows: C_out

[15] =D

[15] ; C_out

[14] =D

[14] ; C_out

[13] =D

[13] ; C_out

[12] =D

[12] ; C_out

[11] =D

[11] ; C_out

[10] =D

[10] ; C_out[9]=D[9]; C_ out[8]=D[8]; C_out[7]=D[7]; C_out[6]=D[6]; C_out[5]=D[5]; C_out[4]=D[4]; C_out[3]=D[3]; C_out[2]=D[2]; C_out[1]=D[1]; C_out[0]=D[0].

[0066] Embodiment 2:

[0067] Reference Figure 7 TBEC code is a linear block code capable of correcting 3-bit burst errors. It is more suitable for correcting the error mode caused by single particle upset and performing system-level ECC reinforcement design. The traditional TBEC codec is powerful, but has high redundancy, and the circuit area and resource consumption need to be optimized. Therefore, the purpose of the present invention is to design a radiation-resistant TBEC codec with low complexity and excellent performance, so as to seek an optimal design between hardware resource consumption and error correction function.

[0068] The circuit structure of the low-complexity radiation-resistant TBEC encoder / decoder comprises: a data selection unit, an encoder / decoder multiplexing unit, an error mode and error position confirmation unit, an error correction unit, and an error correction capability verification unit. The input signal of the present invention is 16 pre-coded data bits and 23 data bits after single particle flipping. When the enable signal En=0, the circuit is in the encoding state, selects the input 16 pre-coded data bits, passes through the encoder / decoder multiplexing unit, and outputs 23 coded data bits to be stored in the memory; when the enable signal En=1, the circuit is in the decoding state, selects the input 23 data bits after single particle flipping, passes through the encoder / decoder multiplexing unit, the error mode and error position confirmation unit, the error correction unit, and the error correction capability verification unit, and outputs 16 correct data bits.

[0069] The encoder / decoder multiplexing unit includes: a data initialization module and a redundant bit Ci / syndrome S operation module. The data initialization module is used to initialize the data, and determines whether it is in the encoding state or the decoding state by using the En enable signal. If it is in the encoding state, the data in the register will be initialized to 0; if it is in the decoding state, the data in the register will be initialized to the 23-bit single-particle flipped data input from the previous level circuit. The redundant bit Ci / syndrome S operation module uses the data initialized by the selector through an exclusive OR logic operation to calculate the redundant bit Ci or the syndrome S in the encoding state or the decoding state respectively. Among them, the exclusive OR logic relationship used to generate the 7-bit redundant bit C_out[22:16] when encoding the 16-bit pre-coded data D[15:0] is the same as the exclusive OR logic relationship used to generate the 7-bit syndrome S[6:0] when decoding the 23-bit single-particle flipped data D_error[22:0]. The exclusive OR logic relationship is:

[0070] C_out

[22] =C[6]⊕D

[15] ⊕D

[12] ⊕D

[11] ⊕D[9]⊕D[6]⊕D[1]⊕D[0];

[0071] C_out

[21] =C[5]⊕D

[14] ⊕D

[11] ⊕D

[10] ⊕D[8]⊕D[7]⊕D[6]⊕D[3];

[0072] C_out

[20] =C[4]⊕D

[13] ⊕D

[10] ⊕D[5]⊕D[4]⊕D[1];

[0073] C_out

[19] =C[3]⊕D

[15] ⊕D

[11] ⊕D[7]⊕D[4]⊕D[2];

[0074] C_out

[18] =C[5]⊕D

[14] ⊕D

[10] ⊕D[7]⊕D[3]⊕D[0];

[0075] C_out

[17] =C[1]⊕D

[13] ⊕D[9]⊕D[6]⊕D[4]⊕D[3]⊕D[1];

[0076] C_out

[16] =C[0]⊕D

[12] ⊕D[8]⊕D[5]⊕D[2];

[0077] The data initialization module is controlled by the En enable signal, and different C[6:0] initial values ​​are set in the encoding state or the decoding state, and are substituted into the subsequent XOR logic operation to affect the final calculation result of the redundant bit Ci / syndrome S operation module. When the encoding function is executed, the data initialization module inputs 16-bit pre-coded data D[15:0] and 7-bit "0" data 7'b0, En=0, and the output is C[6:0]=7'b0. When the decoding function is executed, the data initialization module inputs 23-bit single-particle flip data D_error[22:0] and 7-bit "0" data 7'b0, En=1, and the output is C[6:0]=D_error[22:16].

[0078] The redundant bit Ci / syndrome S operation module substitutes the different C[6:0] initial values ​​set by the data initialization module in the encoding state or the decoding state into the XOR logic operation to obtain the final calculation result of the redundant bit Ci / syndrome S. When the encoding function is executed, the redundant bit Ci / syndrome S operation module inputs 16-bit pre-coded data D[15:0] and the initialization data C[6:0]=7'b0, and the output is 23-bit coded data C_out[22:0]. When the decoding function is executed, the redundant bit Ci / syndrome S operation module inputs 23-bit single-particle flip data D_error[22:0] and the initialization data C[6:0]=D_error[22:16], and the output is 7-bit syndrome S<6:0>. The logical operation relationship of all 23 bits of data is as follows:

[0079] The operation of the first 7 bits of data C_out[22:16] conforms to the XOR logic relationship described in claim 2, and the XOR logic complies with the parity check matrix specification in the linear block code:

[0080]

[0081] Among them, when in the encoding state, C[6], C[5], C[4], C[3], C[2], C[1] and C[0] in all the right-hand expressions in the XOR logic relationship are initialized to 0, and XOR with 0 is equivalent to C[i] not participating in the operation. The remaining D[i] in the right-hand expression respectively corresponds to the value in the input 16-bit pre-coded data D[15:0]. The required 7-bit redundant bits C_out[22:16] are obtained through the XOR logic operation, and the 23-bit coded output C_out[22:0] is formed with the following 16-bit data bits. When in the decoding state, C[6], C[5], C[4], C[3], C[2], C[1] and C[0] in the XOR logic relationship are initialized to D_error

[22] , D_error

[21] , D_error

[20] , D_error

[19] , D_error

[18] , D_error

[17] and D_error

[16] in the data after the single particle upset respectively. The remaining D[i] in the right formula corresponds to the value of the 23-bit input data D_error[22:0] after the single particle upset respectively. The required syndrome S is obtained by XOR logic operation, and only the first 7 bits of data C_out[22:16] in the decoding state calculation are output as the 7-bit syndrome S[6:0].

[0082] The relationship of the last 16 bits of data is as follows: C_out

[15] =D

[15] ; C_out

[14] =D

[14] ; C_out

[13] =D

[13] ; C_out

[12] =D

[12] ; C_out

[11] =D

[11] ; C_out

[10] =D

[10] ; C_out[9]=D[9]; C_ out[8]=D[8]; C_out[7]=D[7]; C_out[6]=D[6]; C_out[5]=D[5]; C_out[4]=D[4]; C_out[3]=D[3]; C_out[2]=D[2]; C_out[1]=D[1]; C_out[0]=D[0].

[0083] The circuit structure block diagram of the low-complexity radiation-resistant TBEC encoder and decoder of the present invention is as follows: Figure 1 As shown, the input signal of the present invention is 16 pre-coded data bits and 23 bits of data after single particle flip occurs. When the enable signal En=0, the circuit is in the encoding state, selects to input the 16 pre-coded data bits, passes through the encoding and decoding multiplexing unit, and outputs 23 bits of encoded data to be stored in the memory; when the enable signal En=1, the circuit is in the decoding state, selects to input the 23 bits of data after single particle flip occurs, passes through the encoding and decoding multiplexing unit, the error mode and error position confirmation unit, the error correction unit and the error correction capability verification unit, and outputs 16 correct data bits.

[0084] Figure 2 The circuit structure diagram of the encoding and decoding multiplexing module is shown. Through the control of the En enable signal, different C[6:0] initial values ​​are set in the encoding state or the decoding state, and the redundant bit Ci / syndrome S operation module is substituted for the XOR logic operation to obtain the final calculation result of the redundant bit Ci / syndrome S operation module. When the encoding function is executed, the input is 16-bit pre-coded data D[15:0], the initialized data is C[6:0]=7'b0, and the output is 23-bit coded data C_out[22:0] after the XOR logic operation. When the decoding function is executed, the input is 23-bit single-particle flip data D_error[22:0], the initialized data is C[6:0]=D_error[22:16], and the output is 7-bit syndrome S[6:0] after the XOR logic operation.

[0085] In the decoding state, after the encoding and decoding multiplexing module outputs the 7-bit syndrome S[6:0], the syndrome S[6:0] is input into the error mode and error position confirmation unit to confirm the error mode and error position. Figure 3 The schematic diagram of the error mode and error position confirmation unit circuit. The syndrome Si corresponding to all error modes is used as a comparison table to compare the input 7-bit syndrome S[6:0] one by one. The syndrome Si corresponding to all error modes is calculated in MATLAB to generate a comparison table, and the operation logic performs an XOR logic operation according to the data position corresponding to the parity check matrix. Figure 4 As shown, the column vector of the parity check matrix corresponding to each data bit and redundant bit is represented by Hi, and there are 23 in total. For example, if D0 is flipped by one bit, the corresponding syndrome S0=H0; if D0 and D1 are flipped by two bits, the corresponding syndrome S1=H0⊕H1; if D0 and D2 are flipped by two bits, the corresponding syndrome S2=H0⊕H2; if D0, D1 and D2 are flipped by three bits, the corresponding syndrome S3=H0⊕H1⊕H2. Finally, all the error modes and error positions that the TBEC code can correct are obtained, a total of 64 7-bit syndromes Si[6:0]. When the input syndrome S[6:0] is the same as the control syndrome Si[6:0], the corresponding error mode occurs at the corresponding error position. The output data bit corresponding to the position where the error occurs is "1", and the output data bits corresponding to the remaining positions are "0", and the final output is a 16-bit correction code C_correct[15:0]. For example, if the comparison result shows that errors occur in D1, D2, and D3, the 3-bit data C_correct[3:1] in the correction code is "111", and the remaining bits are "0".

[0086] In the error correction unit, the input is the 16-bit correction code C_correct[15:0] and the 16-bit data bit D_error[15:0] after the single particle flip. C_correct[15:0] and D_error[15:0] are bit-wise XORed in the error correction unit. The correct bit data is XORed with "0" and maintained, and the error bit data is XORed with "1" and flipped to the correct data. The output is the 16-bit data D_out[15:0] with the correct decoding result.

[0087] In the error correction capability verification unit, the decoding result D_out<15:0> and the correct pre-coded data D<15:0> are input and an XOR operation is performed. If the 16-bit data is exactly the same, the output is 16b'0, which proves that the error correction function of the codec is correct.

[0088] Figure 5 The following is the result of the encoding function simulation. Among them, sel0 is the enable signal En, which is set to 0, and the encoder is in the encoding state. At this time, data is the input pre-coded data d, and c_out is the encoded output after encoding. The first 7 bits of c_out[22:0] "0011110" are the redundant bits after calculation, and the last 16 bits "0101101010001110" are the data bits.

[0089] Figure 6 The figure is the result of decoding function simulation. Among them, sel0 is the enable signal En, which is set to 1, and the encoder is in the decoding state. At this time, data is the input data d_error[22:0] after the single particle flip occurs, which is "00111100101110110001110", and the correction s[6:0] obtained after passing through the encoding and decoding multiplexing unit is "1010111". After passing through the error mode and error position confirmation unit, the output c_correct[15:0] is "0000011100000000", where the position where the data is "1" indicates that the corresponding data bit has a single particle flip, that is, D10, D9 and D8 in D15~D0 have three consecutive flips. Finally, the correct decoding output z[15:0] is "0101101010001110", and re is the output result of the error correction capability verification unit, all "0" indicates that the error correction capability is correct.

[0090] After simulation verification, the TBEC codec multiplexing method controlled by the enable signal is designed in the low-complexity radiation-resistant TBEC codec structure based on the characteristics of the same part of the XOR logic operation circuits in the encoding and decoding processes. It can be extended to the application scenarios of other linear block codes of the same type. It is suitable for circuit multiplexing of any codec that implements the calculation of coding redundant bits and the calculation of decoding syndromes according to the XOR logic operation specified by the parity check matrix, thereby realizing the low-complexity design of linear block code codecs.

[0091] Those skilled in the art may understand this embodiment as a more specific description of Embodiment 1.

[0092] Those skilled in the art know that, in addition to realizing the system and its various devices, modules, and units provided by the present invention in a purely computer-readable program code, it is entirely possible to realize the same functions in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers by logically programming the method steps. Therefore, the system and its various devices, modules, and units provided by the present invention can be considered as a hardware component, and the devices, modules, and units included therein for realizing various functions can also be regarded as structures within the hardware component; the devices, modules, and units for realizing various functions can also be regarded as both software modules for realizing the method and structures within the hardware component.

[0093] The above describes the specific embodiments of the present invention. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art can make various changes or modifications within the scope of the claims, which does not affect the essence of the present invention. In the absence of conflict, the embodiments of the present application and the features in the embodiments can be combined with each other arbitrarily.

Claims

1. A low-complexity radiation-resistant TBEC codec circuit, characterized in that: include: Data selection unit, codec multiplexing unit, error mode and error position confirmation unit, error correction unit, error correction capability verification unit; The data selection unit is connected to the codec multiplexing unit, the codec multiplexing unit is connected to the error mode and error position confirmation unit, the error mode and error position confirmation unit is connected to the error correction unit, and the error correction unit is connected to the error correction capability verification unit.

2. The low-complexity radiation-hardened TBEC codec circuit according to claim 1, characterized in that: The data selection unit is used to select input data; The encoder / decoder multiplexing unit includes a data initialization module and a redundant bit Ci / syndrome S operation module, wherein the data initialization module initializes data according to the state of an enable signal En and sets different C[6:0] initial values ​​in an encoding state or a decoding state; the redundant bit Ci / syndrome S operation module calculates redundant bits Ci in an encoding state and calculates syndrome S in a decoding state by using an exclusive OR logic operation; The error mode and error position confirmation unit is used to confirm the error mode and error position; The error correction unit corrects the error according to the error mode and error position information; The error correction capability verification unit verifies whether the error-corrected data is correct.

3. The low-complexity radiation-hardened TBEC codec circuit according to claim 2, characterized in that: When the enable signal En=0, the circuit is in the encoding state, selects to input 16 pre-coded data bits, passes through the encoding and decoding multiplexing unit, and outputs 23 bits of encoded data to be stored in the memory; when the enable signal En=1, the circuit is in the decoding state, selects to input 23 bits of data after single-particle flipping, passes through the encoding and decoding multiplexing unit, the error mode and error position confirmation unit, the error correction unit and the error correction capability verification unit, and outputs 16 correct data bits.

4. The low-complexity radiation-hardened TBEC codec circuit according to claim 2, characterized in that: The data initialization module initializes the data in the register to 0 in the encoding state, and initializes the data in the register to the 23-bit data after the single-particle flip occurs input from the previous level circuit in the decoding state.

5. The low-complexity radiation-hardened TBEC codec circuit according to claim 2, characterized in that: The redundant bit Ci / syndrome S operation module, in the encoding state, uses the 16-bit pre-coded data D[15:0] and the C[6:0] data initialized to 0 to obtain the 7-bit redundant bit C_out[22:16] through an exclusive OR logic operation; in the decoding state, uses the 23-bit single-particle flipped data D_error[22:0] and the C[6:0] data initialized to D_error[22:16] to obtain the 7-bit syndrome S[6:0] through an exclusive OR logic operation.

6. The low-complexity radiation-hardened TBEC codec circuit according to claim 2, characterized in that: The XOR logic operation complies with the parity check matrix specification in the linear block code.

7. The low-complexity radiation-hardened TBEC codec circuit according to claim 2, characterized in that: The data initialization module is used to initialize data, and determines whether it is in the encoding state or the decoding state by using the En enable signal; if it is in the encoding state, the data in the register will be initialized to 0; if it is in the decoding state, the data in the register will be initialized to the 23-bit data after the single particle flip occurs input from the previous level circuit.

8. The low-complexity radiation-hardened TBEC codec circuit according to claim 2, characterized in that: The redundant bit Ci / syndrome S calculation module calculates the redundant bit Ci or the syndrome S in the encoding state or the decoding state respectively by using the data initialized by the selector through an exclusive OR logic operation; wherein the exclusive OR logic relationship used to generate the 7-bit redundant bit C_out[22:16] when encoding the 16-bit pre-coded data D[15:0] is the same as the exclusive OR logic relationship used to generate the 7-bit syndrome S[6:0] when decoding the 23-bit single-particle flipped data D_error[22:0], and the exclusive OR logic relationship is: C_out[22]=C[6]⊕D[15]⊕D[12]⊕D[11]⊕D[9]⊕D[6]⊕D[1]⊕D[0]; C_out[21]=C[5]⊕D[14]⊕D[11]⊕D[10]⊕D[8]⊕D[7]⊕D[6]⊕D[3]; C_out[20]=C[4]⊕D[13]⊕D[10]⊕D[5]⊕D[4]⊕D[1]; C_out[19]=C[3]⊕D[15]⊕D[11]⊕D[7]⊕D[4]⊕D[2]; C_out[18]=C[5]⊕D[14]⊕D[10]⊕D[7]⊕D[3]⊕D[0]; C_out[17]=C[1]⊕D[13]⊕D[9]⊕D[6]⊕D[4]⊕D[3]⊕D[1]; C_out[16]=C[0]⊕D[12]⊕D[8]⊕D[5]⊕D[2].

9. The low-complexity radiation-hardened TBEC codec circuit according to claim 2, characterized in that: The data initialization module is controlled by the En enable signal, and different C[6:0] initial values ​​are set in the encoding state or the decoding state, and are substituted into the subsequent XOR logic operation to affect the final calculation result of the redundant bit Ci / syndrome S operation module; when the encoding function is executed, the data initialization module is input with 16-bit pre-coded data D[15:0] and 7-bit "0" data 7'b0, En=0, and the output is C[6:0]=7'b0; when the decoding function is executed, the data initialization module is input with 23-bit single-particle flip data D_error[22:0] and 7-bit "0" data 7'b0, En=1, and the output is C[6:0]=D_error[22:16].

10. The low-complexity radiation-hardened TBEC codec circuit according to claim 2, characterized in that: The redundant bit Ci / syndrome S operation module substitutes different C[6:0] initial values ​​set by the previous level circuit in the encoding state or the decoding state into the XOR logic operation to obtain the final calculation result of the redundant bit Ci / syndrome S; when the encoding function is executed, the redundant bit Ci / syndrome S operation module inputs 16-bit pre-encoded data D[15:0] and the initialization data C[6:0]=7'b0, and outputs 23-bit encoded data C_out[22:0]; when the decoding function is executed, the redundant bit Ci / syndrome S operation module inputs 23-bit single-particle upset data D_error[22:0] and the initialization data C[6:0]=D_error[22:16], and outputs 7-bit syndrome S<6:0>; wherein the logical operation relationship of all 23 bits of data is as follows: The operator XOR logic relationship of the first 7 bits of data C_out[22:16] follows the parity check matrix specification in the linear block code: Among them, when in the encoding state, C[6], C[5], C[4], C[3], C[2], C[1] and C[0] in all the right-hand expressions in the XOR logic relationship are initialized to 0, and XOR with 0 is equivalent to C[i] not participating in the operation; the remaining D[i] in the right-hand expression respectively corresponds to the value in the input 16-bit pre-coded data D[15:0]; the required 7-bit redundant bits C_out[22:16] are obtained by XOR logic operation, and are combined with the following 16-bit data bits to form a 23-bit coded output C_out[22:0]; when in the decoding state, C[6], C[5], C[4], C[3], C[2] in all the right-hand expressions in the XOR logic relationship are initialized to 0, and XOR with 0 is equivalent to C[i] not participating in the operation; the remaining D[i] in the right-hand expression respectively corresponds to the value in the input 16-bit pre-coded data D[15:0]; the required 7-bit redundant bits C_out[22:16] are obtained by XOR logic operation, and are combined with the following 16-bit data bits to form a 23-bit coded output C_out[22:0]; , C[1] and C[0] correspond to the data initialized to D_error[22], D_error[21], D_error[20], D_error[19], D_error[18], D_error[17] and D_error[16] after the single particle upset occurs; the remaining D[i] in the right formula corresponds to the value of the input 23-bit data D_error[22:0] after the single particle upset occurs; the required syndrome S is obtained by the XOR logic operation, and only the first 7 bits of data C_out[22:16] in the decoding state calculation of C_out are output as the 7-bit syndrome S[6:0]; The relationship of the last 16 bits of data is as follows: C_out[15] = D[15]; C_out[14] = D[14]; C_out[13] = D[13]; C_out[12] = D[12]; C_out[11] = D[11]; C_out[10] = D[10]; C_out[9] = D[9]; C_out[8] = D[8]; C_out[7] = D[7]; C_out[6] = D[6]; C_out[5] = D[5]; C_out[4] = D[4]; C_out[3] = D[3]; C_out[2] = D[2]; C_out[1] = D[1]; C_out[0] = D[0].

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