Digital parallel resonance induction heating control system structure and control method

Abstract

The invention discloses a digital parallel resonance induction heating control system structure and a control method, and relates to the technical field of circuit control. The power supply comprises a main circuit, a control circuit and a core control circuit which are connected in sequence, the main circuit comprises a thyristor rectifier bridge, a smoothing reactor, an IGBT inverter bridge and a parallel resonance circuit. The control circuit comprises an intermediate-frequency voltage zero-crossing circuit, a three-phase zero-crossing circuit, a protection circuit and a voltage and current detection circuit; wherein the thyristor rectifier bridge, the smoothing reactor, the IGBT inverter bridge and the parallel resonance circuit are connected in sequence; the parallel resonance circuit, the load and the intermediate-frequency voltage zero-crossing circuit are connected in sequence; and the core control circuit is also respectively connected with the thyristor rectifier bridge, the IGBT inverter bridge, the intermediate frequency voltage zero-crossing circuit, the three-phase zero-crossing circuit, the protection circuit and the voltage and current detection circuit. The control efficiency of the heating power supply can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit control, and in particular to a digital parallel resonant induction heating control system architecture and a control method. Background Art

[0002] In the prior art, although the digital parallel resonant induction heating power supply has been widely used in many industrial heating applications, its design still has some significant defects. The traditional digital parallel resonant induction heating power supply usually includes a main circuit, a control circuit and a core control circuit, wherein the main circuit is composed of a thyristor rectifier bridge, a smoothing reactor, an IGBT inverter bridge and a parallel resonant circuit. However, this structure shows certain limitations in practical applications. Since the frequency range of the digital phase-locked loop used is not large and cannot meet the requirements of multiple frequency loads, the prior art still has deficiencies in terms of frequency locking range, accuracy, response time and stability. Summary of the invention

[0003] The object of the present invention is to provide a digital parallel resonant induction heating control system structure and control method, which can improve the control efficiency of the heating power supply.

[0004] To achieve the above object, the present invention provides the following solutions:

[0005] A digital parallel resonant induction heating control system architecture, comprising: a main circuit, a control circuit and a core control circuit connected in sequence; the main circuit comprises a thyristor rectifier bridge, a smoothing reactor, an IGBT inverter bridge and a parallel resonant circuit; the control circuit comprises an intermediate frequency voltage zero-crossing circuit, a three-phase zero-crossing circuit, a protection circuit and a voltage and current detection circuit;

[0006] Among them, the thyristor rectifier bridge, the smoothing reactor, the IGBT inverter bridge and the parallel resonant circuit are connected in sequence; the thyristor rectifier bridge is also connected to the three-phase zero-crossing circuit; the parallel resonant circuit, the load and the intermediate frequency voltage zero-crossing circuit are connected in sequence; the core control circuit is also respectively connected to the thyristor rectifier bridge, the IGBT inverter bridge, the intermediate frequency voltage zero-crossing circuit, the three-phase zero-crossing circuit, the protection circuit, and the voltage and current detection circuit.

[0007] Optionally, the core control circuit adopts a dual-core DSP+FPGA architecture; wherein the dual-core DSP includes an A-core DSP and a B-core DSP; the A-core DSP and the B-core DSP are connected via an IPC, the A-core DSP is also connected to the FPGA and the voltage and current detection circuits, respectively, and communicates with the touch screen via a 485 communication interface; the B-core DSP is connected to the FPGA via an IIC; the FPGA is also connected to the protection circuit, the three-phase zero-crossing circuit, the thyristor rectifier bridge, the IGBT inverter bridge and the intermediate frequency voltage zero-crossing circuit, respectively.

[0008] Optionally, the FPGA includes an insulated gate bipolar transistor trigger complementary pulse terminal, and the insulated gate bipolar transistor trigger complementary pulse terminal is connected to the IGBT inverter bridge.

[0009] Optionally, the input end of the thyristor rectifier bridge is connected to a three-phase AC power supply, and the three-phase AC power supply is connected to a three-phase AC synchronization signal end of the FPGA through a three-phase AC synchronization signal generated by the three-phase zero-crossing circuit.

[0010] Optionally, a synchronous frequency division controlled digital phase-locked loop system is provided in the FPGA, and the synchronous frequency division controlled digital phase-locked loop system includes a frequency detector, a modulus counter, a phase counter and a synchronous frequency divider connected in sequence, and the frequency detector is also connected to the synchronous frequency divider through a synchronous controller; the output signal of the synchronous frequency divider is right-shifted by an angle of α and then input into the frequency detector.

[0011] Optionally, the phase and frequency detector is composed of two D flip-flops.

[0012] The present invention also provides a digital parallel resonant induction heating control system architecture control method, comprising:

[0013] When the system starts, DSP sends the phase difference α°, the starting frequency of the phase-locked loop, the maximum frequency of the phase-locked loop, the direct-through time and the double narrow pulse width time to FPGA through IIC. When the heating start signal is received and the external start signal is turned on, after 57ms, the inverter start signal is turned on, and the FPGA generates B-channel pulses and A-channel pulses and enters the direct-through mode. The direct-through time is set by DSP to FPGA. DSP controls the rectifier frequency to rise from 25kHz to 37kHz. When it rises to 37kHz within the direct-through time, the direct-through time ends, DSP opens the current loop, outputs the control rectifier frequency to FPGA, DSP sends a phase-locked signal, FPGA controls the inverter frequency to sweep from the starting frequency, and the inverter frequency increases to near the resonant frequency. After less than 8ms, when the intermediate frequency voltage is established, the oscillation judgment hardware circuit generates a pulse to FPGA. After receiving the oscillation judgment signal, FPGA opens the digital phase-locked loop to track the resonant frequency. If the phase lock is successful, FPGA sends a phase-locked success signal to DSP. DSP The FPGA detects the phase-locked phase after startup. If it is greater than 10% of the set value, it reports a phase-too-large fault. If it is less than 10% of the set value, it reports a phase-too-small fault. The fault code is sent from the FPGA to the DSP through the IIC. The FPGA outputs complementary pulses with overlapping time according to the output frequency of the phase-locked loop. The overlapping time is obtained by the FPGA table lookup. When a stop signal is received, the inverter frequency changes after stopping as follows: the inverter frequency maintains the resonant frequency within 7ms, and the frequency drops from the resonant frequency to the starting frequency from 7ms to 17ms. After 17ms, it is determined that the current is discharged cleanly. The DSP sends a signal to close the phase-locked loop. After receiving the signal, the FPGA turns off the inverter pulse. Both A and B are low level, waiting for the next phase-locked command input. After 30ms, the vibration signal is judged to be low level. When a fault is displayed, press the reset button to initialize the parameters, clear the fault code, and enter the waiting state; Fault handling: After the startup is completed, pull the inverter command and the shutdown command, the startup is not completed, and pull the rectification frequency to 25kHz.

[0014] Optionally, the control process when receiving the heating start signal is: the machine start button sends a signal, after the DSP debouncing program, a synchronization signal is sent to the FPGA, the dual-core DSP and the FPGA are started at the same time, and the dual-core DSP synchronously opens the timer.

[0015] According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0016] The present invention discloses a digital parallel resonant induction heating control system structure and control method, the power supply comprises a main circuit, a control circuit and a core control circuit connected in sequence; the main circuit comprises a thyristor rectifier bridge, a smoothing reactor, an IGBT inverter bridge and a parallel resonant circuit; the control circuit comprises an intermediate frequency voltage zero-crossing circuit, a three-phase zero-crossing circuit, a protection circuit and a voltage and current detection circuit; wherein the thyristor rectifier bridge, the smoothing reactor, the IGBT inverter bridge and the parallel resonant circuit are connected in sequence; the thyristor rectifier bridge is also connected to the three-phase zero-crossing circuit; the parallel resonant circuit, the load and the intermediate frequency voltage zero-crossing circuit are connected in sequence; the core control circuit is also respectively connected to the thyristor rectifier bridge, the IGBT inverter bridge, the intermediate frequency voltage zero-crossing circuit, the three-phase zero-crossing circuit, the protection circuit, and the voltage and current detection circuit. The present invention can improve the control efficiency of the heating power supply. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0018] Figure 1 It is a structural schematic diagram of the digital parallel resonant induction heating control system architecture of the present invention;

[0019] Figure 2 This is a connection diagram between DSP and FPGA in this embodiment;

[0020] Figure 3 Schematic diagram of timing control in this embodiment;

[0021] Figure 4 This is a structural diagram of a synchronous frequency division control phase-locked loop system in this embodiment;

[0022] Figure 5 : is a structural diagram of the frequency and phase detector in this embodiment;

[0023] Figure 6 Schematic diagram of the working principle of the phase counter in this embodiment;

[0024] Figure 7 This is a control diagram of step 1 in this embodiment;

[0025] Figure 8 This is a control diagram of step 2 in this embodiment;

[0026] Fig. 9 This is a control diagram of step 3 in this embodiment;

[0027] Fig.10This is a control diagram of step 5 in this embodiment;

[0028] Fig.11 This is a control diagram of step 7 in this embodiment;

[0029] Fig.12 This is a schematic diagram of how FPGA generates two complementary intermediate signals based on the phase-locked loop output signal in this embodiment. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] The object of the present invention is to provide a digital parallel resonant induction heating control system structure and control method, which can improve the control efficiency of the heating power supply.

[0032] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0033] like Figure 1-Figure 6 As shown, the present invention provides a digital parallel resonant induction heating control system architecture, including: a main circuit, a control circuit and a core control circuit connected in sequence; the main circuit includes a thyristor rectifier bridge, a smoothing reactor, an IGBT inverter bridge and a parallel resonant circuit; the control circuit includes an intermediate frequency voltage zero-crossing circuit, a three-phase zero-crossing circuit, a protection circuit and a voltage and current detection circuit.

[0034] Among them, the thyristor rectifier bridge, the smoothing reactor, the IGBT inverter bridge and the parallel resonant circuit are connected in sequence; the parallel resonant circuit, the load and the intermediate frequency voltage zero-crossing circuit are connected in sequence; the core control circuit is also respectively connected to the thyristor rectifier bridge, the IGBT inverter bridge, the intermediate frequency voltage zero-crossing circuit, the three-phase zero-crossing circuit, the protection circuit, and the voltage and current detection circuit.

[0035] As a further implementation method, the core control circuit is a dual-core DSP+FPGA architecture, which is composed of a microprocessor DSP chip (dual-core) and an FPGA chip. The DSP chip (A core) is connected to the touch screen and communicates with the touch screen through a 485 communication interface. It mainly sets voltage, current, power, phase, control parameters, and displays voltage, current, power, phase, etc. After comparing and calculating the voltage and current signals sampled by the A / D and the set voltage and current signals, the calculated rectifier pulses of different frequencies are sent to the FPGA for full-controlled rectification. The real-time overcurrent and real-time overvoltage signals during the startup process are sent to the FPGA for protection. The DSP chip (B core) is connected to the FPGA through IIC to perform operations such as parameter setting and returning fault codes. The DSP chip (A core) and the DSP chip (B core) communicate through IPC.

[0036] The FPGA input end is connected to the intermediate frequency voltage zero-crossing circuit, mainly to collect the zero-crossing pulse of the load voltage; the thyristor trigger pulse end of the FPGA chip is connected to the rectifier bridge, the rectifier bridge is connected to the smoothing reactor, the smoothing reactor is connected to the IGBT inverter bridge, the IGBT inverter bridge is connected to the parallel resonant circuit, the thyristor rectifier bridge input end is connected to the three-phase AC power supply AC, the three-phase AC power supply AC generates a three-phase AC synchronization signal through the three-phase zero-crossing circuit and is connected to the three-phase AC synchronization signal end of the FPGA chip; the IGBT (insulated gate bipolar transistor) trigger complementary pulse end of the FPGA chip is connected to the IGBT inverter bridge.

[0037] Based on the above power control system structure, the corresponding control principle is provided:

[0038] like Figure 2 and Figure 3As shown, when the system starts, DSP sends the phase difference α°, the starting frequency of the phase-locked loop, the maximum frequency of the phase-locked loop, the direct-through time and the double narrow pulse width time to FPGA through IIC. When the heating start signal is received (sent by the machine start button, after the DSP de-bouncing program, a synchronization signal is sent to FPGA, DSP and FPGA are started at the same time, and DSP turns on the timer), after the external start signal is turned on, after 57ms, the inverter start signal is turned on, and FPGA generates B-channel pulse (high level) and A-channel pulse (low level) to enter the direct-through mode. The direct-through time can be set by DSP to FPGA. DSP controls the rectifier frequency to rise from 25kHz to 37kHz, and rises linearly during the direct-through time. When it rises to 37kHz, the direct-through time ends. When the DSP opens the current loop, the output controls the rectifier frequency to the FPGA, the DSP sends a phase-locked signal, the FPGA controls the inverter frequency to sweep from the starting frequency, and the inverter frequency increases to near the resonant frequency. After less than 8ms, when the intermediate frequency voltage (greater than the threshold) is established, the vibration determination hardware circuit generates a pulse (vibration determination signal) to the FPGA. After receiving the vibration determination signal, the FPGA opens the digital phase-locked loop to track the resonant frequency. If the phase-lock is judged to be successful, the FPGA sends a phase-lock success signal to the DSP. The DSP makes a judgment based on the vibration determination signal and the phase-lock success signal. If both are successful, a heating success signal is sent. If the phase-lock is unsuccessful, a relock is performed. If the relock times reach the set times and are still unsuccessful, the FPGA sends a phase-lock failure signal to the DSP and pulls the inverter at the same time. After the startup is completed, the FPGA detects the phase-locked phase. If it is greater than 10% of the set value, it reports a phase-excess fault. If it is less than 10% of the set value, it reports a phase-excess fault. The fault code is sent from the FPGA to the DSP through the IIC. The FPGA outputs complementary pulses with overlapping time according to the output frequency of the phase-locked loop. The overlapping time is obtained by the FPGA after looking up the table. After receiving the stop signal, the rectifier frequency is pulled to 25kHz. The inverter frequency changes after stopping as follows: the inverter frequency maintains the resonant frequency within 7ms, and the frequency drops from the resonant frequency to the starting frequency during 7ms-17ms (this is determined by the phase-locked loop, because it is not closed, the inductor is discharged, and there is still current at this time). When the current is discharged (about 17ms), the DSP sends a signal to close the phase-locked loop. After receiving it, the FPGA turns off the inverter pulse. Both A and B are low levels, waiting for the next phase-locked command input. After 30ms, the vibration signal is low. When there is a fault display, press the reset button to initialize the parameters, clear the fault code, and enter the state where it can be started. Fault handling: After the startup is completed, the inverter command is the same as the shutdown command. If the startup is not completed, just pull the rectifier frequency to 25kHz.

[0039] Among them, since the rectifier circuit of the parallel resonant circuit is connected in series with a smoothing reactor, it is equivalent to a constant current source power supply, and open circuit is not allowed. In order to avoid the current source open circuit, the two pairs of switch tubes in the same bridge arm need to set a certain overlap time when they are in action. The idea of ​​achieving the overlap time is, for example Fig.12 As shown, FPGA first generates two complementary intermediate signals according to the phase-locked loop output signal, signal1 is the phase-locked loop output signal, signal2 is the complementary signal of the phase-locked loop, after FPGA detects the falling edge of signal1, it delays for a period of time (overlapping time) and turns off to generate signal3, similarly, after FPGA detects the falling edge of signal2, it delays for a period of time (overlapping time) and turns off to generate signal4, thus obtaining signal3 and signal4 with overlapping time, which are respectively transmitted to the upper and lower pairs of switch tubes of the same bridge arm of the inverter.

[0040] With the development of programmable digital integrated circuits, digital phase-locked loops designed with programmable logic devices (FPGAs) are easier to develop, and have better volume, power consumption, accuracy, and anti-interference performance than other methods. In order to solve the problem of narrow capture range of traditional digital phase-locked loops, a design method for a fully digital phase-locked loop with synchronous frequency division coefficients is proposed to track the input signal in real time and quickly.

[0041] The basic structure of the synchronous frequency division control digital phase-locked loop system based on FPGA is as follows: Figure 4 As shown, where u i is the input signal (tracked signal), u0 is the phase-locked loop output signal, A1 is the phase lead error signal, A2 is the phase lag error signal, B1 is the carry signal, B2 is the borrow signal, u d is the output signal of the phase counter, and N1 is the synchronous frequency division coefficient output by the synchronous controller. In order to achieve output leading input, the parallel resonant circuit works in a weak capacitive state, that is, the current leads the voltage by a certain angle, and the output signal u0 is shifted right by an angle α before being input into the frequency detector and phase detector.

[0042] The digital frequency detector is composed of two D flip-flops. The structure of the phase detector is shown in Figure 5 The output signal of the frequency detector is determined by the input signal. i and u after phase shift o When the phase difference and frequency difference are zero, the output error signal is zero. Assume that the input signal u i Phase advance u o After the phase shift, the phase lead error signal A1 generates a rising edge. o When the rising edge of the phase-shifted signal arrives, the phase lag error signal A2 generates a rising edge. At this time, the output of the NAND gate is 0, and the trigger output is cleared. Then A1 and A2 output low levels, and the high level width of A1 represents ui Signal advance u o The phase error of the signal after phase shifting. Similarly, when u i The signal lags behind u o The high level width of the positive pulse signal output by the phase lag error signal A2 represents u i Signal lag o The phase error of the signal after phase shifting.

[0043] When the phase lead error signal A1 is high, the counter starts counting. When the count reaches 4, the counter is cleared, a carry pulse is sent, and the carry signal B1 generates a high level pulse of 1 clock cycle. Similarly, when the phase lag error signal A2 is high, when the count reaches 4, the counter is cleared, a borrow pulse is sent, and the borrow signal B2 generates a high level pulse of 1 clock cycle. When both the phase lead error signal and the phase lag error signal are low, the counter does not work.

[0044] The working waveform of the phase counter is shown in Figure 6 The working principle is: by adjusting the clock signal U c The frequency division signal U is obtained by dividing the frequency by two t , when the signal U t When it is high, the phase counter outputs the signal U d is low level; when the signal U t When it is low, the clock signal U c Negate and get U d Signal; when the system has a B2 borrow pulse, t The signal inserts a positive pulse to make the signal U d When the system has a B1 carry pulse, a negative pulse is inserted into the Ut signal to make the signal U d The phase lead of the system is i and u o The frequency or phase of the phase-shifted signal is inconsistent, that is, there is an error signal. The system will continuously generate borrow pulse signals or carry pulse signals, and the phase counter adjusts the output signal frequency and phase through these pulse signals. o The phase-shifted signal tracks the input signal u i , reaching steady state, that is, the output signal leads the input signal by α°. When there is no carry and borrow pulse, the phase counter is essentially a system clock divider.

[0045] like Figure 7-Figure 11The rectification process shown in the figure has the following inputs: 1. Zero-crossing signals of each phase in the three phases, divided into positive and negative, so there are 6 signals in total; 2. High-frequency pulses (25kHz~160kHz) that adjust the phase shift position of the output pulse. Output: 6 double narrow pulses.

[0046] The overall system implementation steps include:

[0047] Step 1: First obtain the natural commutation point position through the zero-crossing signal.

[0048] Step 2: Determine the position and angle at which the pulse is to be output through externally given high-frequency pulses.

[0049] Step 3: Determine the output pulse width through the internal count value or pulse.

[0050] Step 4: Through the first three steps, three single pulses will be obtained, corresponding to the three phases.

[0051] Step 5: The three single pulses will be compared with the corresponding two zero-crossing signals respectively, and each single pulse will obtain two single pulses corresponding to different positive half-cycles and negative half-cycles.

[0052] Step 6: Through step 5, 6 single pulses corresponding to each phase can be obtained to control 6 thyristors respectively.

[0053] Step 7: Combine two adjacent paths. There are 6 combinations, and 6 double narrow pulses are obtained.

[0054] In addition, for each sub-module included in the system (frequency divider U301; synchronization signal generators U101, U102, U103; phase shift position processors U104, U105, U106; pulse width processors U107, U108, U109; other gate circuits), the specific settings are as follows:

[0055] Frequency Divider U301

[0056] Input: External clock frequency.

[0057] Output: Based on the clock frequency and the frequency division factor, output other frequency pulses.

[0058] Principle: Count the number of rising edges and flip the level.

[0059] Synchronous signal generator U101, U102, U103

[0060] Input: 6 zero-passing signals f and fi, each two of which correspond to a submodule. A and AF correspond to U101, generating the natural commutation point signal of phase A. B and BF correspond to U102, generating the natural commutation point signal of phase B. C and CF correspond to U103, generating the natural commutation point signal of phase C.

[0061] Output: Three natural commutation point signals.

[0062] Principle: Two zero-crossing signals are generated through an AND gate. The rising and falling edges of the two signals are taken respectively to obtain the natural commutation point signal.

[0063] Phase shift position processor U104, U105, U106

[0064] Input: 1. Three-way natural commutation point signal res; 2. Pulse phase-shift input signal clk.

[0065] Output: Phase shift position output signal.

[0066] Principle: Taking the rising edge of the natural commutation point signal as the reference, count according to the frequency of the clk signal. The larger the frequency, the smaller the count value. A count value is fixed inside the chip. After the rising edge of the clk signal, the two count values ​​are compared. When the two count values ​​are equal, a pulse is output. When the frequency is higher, the count values ​​will be equal faster, so the angle of the output pulse will be smaller. That is, when the frequency is the largest, the phase shift angle ≈ 0, that is, the pulse output will be near the natural commutation point.

[0067] Dual narrow pulse width processor U107, U108, U109

[0068] Input: phase shift position output signal clk, externally determined pulse width high frequency signal r.

[0069] Output: three single pulses out1.

[0070] Principle: Based on the rising edge of the clk signal, the external pulse r or internal count. Output low level before the arrival of the clk signal, take the rising edge of the clk signal as the starting point, output high level and start counting, until the count value is consistent with the internal count, output low level, thus generating a pulse.

[0071] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0072] This article uses specific examples to illustrate the principles and implementation methods of the present invention. The above examples are only used to help understand the core idea of ​​the present invention. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A digital parallel resonant induction heating control system architecture, characterized in that: include: A main circuit, a control circuit and a core control circuit connected in sequence; the main circuit includes a thyristor rectifier bridge, a smoothing reactor, an IGBT inverter bridge and a parallel resonant circuit; the control circuit includes an intermediate frequency voltage zero-crossing circuit, a three-phase zero-crossing circuit, a protection circuit and a voltage and current detection circuit; Among them, the thyristor rectifier bridge, the smoothing reactor, the IGBT inverter bridge and the parallel resonant circuit are connected in sequence; the parallel resonant circuit, the load and the intermediate frequency voltage zero-crossing circuit are connected in sequence; the core control circuit is also respectively connected to the thyristor rectifier bridge, the IGBT inverter bridge, the intermediate frequency voltage zero-crossing circuit, the three-phase zero-crossing circuit, the protection circuit, and the voltage and current detection circuit.

2. The digital parallel resonant induction heating control system architecture according to claim 1 is characterized in that: The core control circuit adopts a dual-core DSP+FPGA architecture; wherein the dual-core DSP includes an A-core DSP and a B-core DSP; the A-core DSP and the B-core DSP are connected via an IPC, the A-core DSP is also connected to the FPGA and the voltage and current detection circuits respectively, and communicates with the touch screen via a 485 communication interface; the B-core DSP is connected to the FPGA via an IIC; the FPGA is also connected to the protection circuit, the three-phase zero-crossing circuit, the thyristor rectifier bridge, the IGBT inverter bridge and the intermediate frequency voltage zero-crossing circuit respectively.

3. The digital parallel resonant induction heating control system architecture according to claim 2 is characterized in that: The FPGA includes an insulated gate bipolar transistor trigger complementary pulse end, and the insulated gate bipolar transistor trigger complementary pulse end is connected to the IGBT inverter bridge.

4. The digital parallel resonant induction heating control system architecture according to claim 2, characterized in that: The input end of the thyristor rectifier bridge is connected to a three-phase AC power supply, and the three-phase AC power supply is connected to the three-phase AC synchronization signal end of the FPGA through the three-phase AC synchronization signal generated by the three-phase zero-crossing circuit.

5. The digital parallel resonant induction heating control system architecture according to claim 2, characterized in that: The FPGA is provided with a synchronous frequency division control digital phase-locked loop system, which includes a frequency detector, a modulus counter, a phase counter and a synchronous frequency divider connected in sequence, and the frequency detector is also connected to the synchronous frequency divider through a synchronous controller; the output signal of the synchronous frequency divider is right-shifted by an angle α and then input into the frequency detector.

6. The digital parallel resonant induction heating control system architecture according to claim 5, characterized in that: The frequency and phase detector is composed of two D flip-flops.

7. A digital parallel resonant induction heating control system architecture control method, characterized in that: include: When the system starts, DSP sends the phase difference α°, the starting frequency of the phase-locked loop, the maximum frequency of the phase-locked loop, the direct-through time and the double narrow pulse width time to FPGA through IIC. When the heating start signal is received and the external start signal is turned on, after 57ms, the inverter start signal is turned on, and the FPGA generates B-channel pulses and A-channel pulses and enters the direct-through mode. The direct-through time is set by DSP to FPGA. DSP controls the rectifier frequency to rise from 25kHz to 37kHz. When it rises to 37kHz within the direct-through time, the direct-through time ends, DSP opens the current loop, outputs the control rectifier frequency to FPGA, DSP sends a phase-locked signal, FPGA controls the inverter frequency to sweep from the starting frequency, and the inverter frequency increases to near the resonant frequency. After less than 8ms, when the intermediate frequency voltage is established, the oscillation judgment hardware circuit generates a pulse to FPGA. After receiving the oscillation judgment signal, FPGA opens the digital phase-locked loop to track the resonant frequency. If the phase lock is successful, FPGA sends a phase-locked success signal to DSP. DSP The FPGA detects the phase-locked phase after startup. If it is greater than 10% of the set value, it reports a phase-too-large fault. If it is less than 10% of the set value, it reports a phase-too-small fault. The fault code is sent from the FPGA to the DSP through the IIC. The FPGA outputs complementary pulses with overlapping time according to the output frequency of the phase-locked loop. The overlapping time is obtained by the FPGA table lookup. When a stop signal is received, the inverter frequency changes after stopping as follows: the inverter frequency maintains the resonant frequency within 7ms, and the frequency drops from the resonant frequency to the starting frequency from 7ms to 17ms. After 17ms, it is determined that the current is discharged cleanly. The DSP sends a signal to close the phase-locked loop. After receiving the signal, the FPGA turns off the inverter pulse. Both A and B are low level, waiting for the next phase-locked command input. After 30ms, the vibration signal is judged to be low level. When a fault is displayed, press the reset button to initialize the parameters, clear the fault code, and enter the waiting state; Fault handling: After the startup is completed, pull the inverter command and the shutdown command, the startup is not completed, and pull the rectification frequency to 25kHz.

8. The digital parallel resonant induction heating control system architecture control method according to claim 7, characterized in that: The control process when receiving the heating start signal is: the machine start button sends a signal, after the DSP debouncing program, a synchronization signal is sent to the FPGA, the dual-core DSP and the FPGA are started at the same time, and the dual-core DSP synchronously opens the timer.

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