Method for increasing process window of peripheral logic region
By forming an etch stop layer on the hard mask layer and stably stopping it on it during the grinding process, the thickness difference and load effect problems caused by inaccurate grinding stop in the prior art are solved, and the process window expansion and thickness uniformity improvement of the peripheral logic region are achieved.
Patent Information
- Application Number
- CN202510101106.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-22
- Publication Date
- 2025-04-25
AI Technical Summary
The prior art cannot accurately grasp the EPD when the grinding stops, resulting in a difference in the thickness of the hard mask layer between the wafer and the wafer, poor loading effect, insufficient etching windows of the peripheral logic region and floating gate polysilicon layer, difficult to cover, resulting in residues and damage, which brings difficulties to the platform's Inline control.
By forming an etch stop layer on the hard mask layer and stably stopping on the etch stop layer during the grinding process, the thickness difference and load effect are improved by chemical mechanical planarizing grinding, removing the protruding parts of the etch stop layer and the hard mask layer, and expanding the process window of the peripheral logic region.
It is achieved to stabilize the etch stop layer during the grinding process, avoid the impact of etching unevenness caused by the front layer, improve the difference in grinding thickness and load effect, and create a relatively stable front layer for the peripheral logic region, with good thickness uniformity, and increase the etching window of the peripheral logic region and the control gate polysilicon layer.
Smart Images
Figure CN119893999A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of semiconductor technology, and in particular to a method for increasing a process window of a peripheral logic area. Background Art
[0002] A method for manufacturing a flash memory device in the prior art includes:
[0003] Step 1, providing a substrate 201, the substrate 201 includes a storage area, a carrier area and a peripheral logic area, and forming a stacked structure on the storage area and the peripheral logic area, the stacked structure is composed of a coupling layer 202, a floating gate polysilicon layer 204, an inter-electrode dielectric layer 205, a control gate polysilicon layer 206, and a hard mask layer 207 stacked in sequence from bottom to top, and the material of the hard mask layer 207 is oxide;
[0004] Step 2: A word line trench is formed on the hard mask layer 207 on the storage area and the stacked structure thereunder. A sidewall structure 209 is formed on the sidewall of the word line trench. A tunnel oxide layer 210 is formed in the word line trench. Then, a word line polysilicon layer 208 is formed to fill the word line trench. Figure 1 The structure shown;
[0005] Step 4: Grind the word line polysilicon layer 208 onto the hard mask layer 207 to form a Figure 2 The structure shown;
[0006] Step 5: remove the hard mask layer 207 of the peripheral logic region and the stacked structure thereunder to form a peripheral logic region polysilicon layer 211 located on the peripheral logic region.
[0007] This method stops grinding on the hard mask layer 207 and cannot capture the EPD (grinding stop end point). There are problems such as poor load effect within the wafer and from wafer to wafer (for example, there are differences in the thickness of the hard mask layer 207 in the storage area and the peripheral logic area on the same wafer, and there are differences in the thickness of the hard mask layer 207 between different wafers). The etching windows of the peripheral logic area and the floating gate polysilicon layer 204 and the control gate polysilicon layer 206 are insufficient and difficult to cover, resulting in residues and damage. The difference in load effect leads to the need to establish regional connections between the storage area and the peripheral logic area for different products, which brings difficulties to the platform Inline (online) management and control.
[0008] In order to solve the above problems, a new method for increasing the process window of the peripheral logic area needs to be proposed. Summary of the invention
[0009] In view of the shortcomings of the prior art mentioned above, the purpose of the present invention is to provide a method for increasing the process window of the peripheral logic area, so as to solve the problem in the prior art that the difference in load effect causes different products to establish regional connections between the storage area and the peripheral logic area, which brings difficulties to the platform Inline (online) management and control.
[0010] To achieve the above-mentioned object and other related objects, the present invention provides a method for increasing a process window of a peripheral logic region, comprising:
[0011] Step 1, providing a substrate, wherein the substrate comprises a storage area, a carrier area and a peripheral logic area, and forming a stacked structure on the storage area and the peripheral logic area, wherein the stacked structure consists of a coupling layer, a floating gate polysilicon layer, an inter-electrode dielectric layer, a control gate polysilicon layer, and a hard mask layer stacked in sequence from bottom to top;
[0012] Step 2: forming an etch stop layer on the hard mask layer;
[0013] Step 3, forming a word line trench on the etch stop layer on the storage area and the stacked structure thereunder, forming a tunnel oxide layer in the word line trench, and then forming a word line polysilicon layer filling the word line trench and covering the etch stop layer;
[0014] Step 4, grinding the word line polysilicon layer onto the etch stop layer;
[0015] Step 5: remove the etch stop layer, remove the protruding portion of the word line polysilicon layer relative to the hard mask layer, and remove the hard mask layer of the peripheral logic area and the control gate polysilicon layer and the floating gate polysilicon layer thereunder.
[0016] Preferably, in step 1, shallow trench isolation is formed on the substrate to define an active area.
[0017] Preferably, the coupling layer in step one is an oxide layer.
[0018] Preferably, the inter-electrode dielectric layer in step one is an ONO layer, and the ONO layer consists of a first oxide layer, a nitride layer, and a second oxide layer stacked in sequence from bottom to top.
[0019] Preferably, the material of the hard mask layer in step 1 is silicon dioxide.
[0020] Preferably, the hard mask layer in step one is formed by furnace thermal oxidation.
[0021] Preferably, the material of the etching stop layer in step 2 is silicon nitride.
[0022] Preferably, the method for forming the word line groove in step three includes: etching the etch stop layer of the storage area and the hard mask layer thereunder to form a first trench; forming a first sidewall structure in the first trench, the first sidewall structure covering the sidewall of the first trench; etching the control gate polysilicon layer and the inter-electrode dielectric layer at the bottom wall of the first trench to form a second trench; forming a second sidewall structure in the second trench, the second sidewall structure covering part of the sidewall of the second trench; etching the floating gate polysilicon layer and the coupling layer at the bottom wall of the second trench to form a third trench; forming the tunneling oxide layer, the tunneling oxide layer covering the bottom wall and sidewall of the third trench.
[0023] Preferably, the grinding method in step 4 is chemical mechanical planarization grinding.
[0024] Preferably, in step five, the etch stop layer is removed by wet etching.
[0025] Preferably, in step five, a phosphoric acid solution is used to remove the etching stop layer.
[0026] Preferably, in step five, the etch stop layer is removed while removing the reference sidewall on the back side of the wafer.
[0027] Preferably, in step five, a thermal oxidation method is used to remove the protruding portion of the word line polysilicon layer relative to the hard mask layer.
[0028] Preferably, in step five, a non-patterned etching method is used to remove the protruding portion of the word line polysilicon layer relative to the hard mask layer.
[0029] Preferably, in step five, the hard mask layer of the peripheral logic region and the control gate polysilicon layer and the floating gate polysilicon layer thereunder are removed by dry etching.
[0030] As described above, the method of increasing the process window of the peripheral logic area of the present invention has the following beneficial effects:
[0031] The present invention can stably stop on the etch stop layer by controlling the grinding. The front hard mask layer is grown in a furnace tube and has a smooth pattern, which avoids the influence of etching unevenness caused by the front layer, improves the grinding thickness difference and load effect, and creates a relatively stable front layer with good thickness uniformity. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Figure 1 A schematic diagram of depositing a word line polysilicon layer in the prior art is shown;
[0033] Figure 2 A schematic diagram of polishing a word line polysilicon layer in the prior art is shown;
[0034] Figure 3 A schematic diagram showing the etching and removal of the stacked structure of the peripheral logic region and the formation of the polysilicon layer of the peripheral logic region in the prior art;
[0035] Figure 4 Shown is a schematic diagram of the process flow of the present invention;
[0036] Figure 5 It is a schematic diagram of forming an etch stop layer according to the present invention;
[0037] Figure 6 A schematic diagram showing the position of the word line polysilicon layer formed by opening the etch stop layer and the hard mask layer of the present invention;
[0038] Figure 7 Shown is a schematic diagram of depositing a word line polysilicon layer according to the present invention;
[0039] Figure 8 Shown is a schematic diagram of the polishing word line polysilicon layer of the present invention;
[0040] Fig. 9 It is a schematic diagram of removing the etch stop layer according to the present invention. DETAILED DESCRIPTION
[0041] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0042] See also Figure 4 The present invention provides a method for increasing a process window of a peripheral logic area, comprising:
[0043] Step 1, providing a substrate 101, the substrate 101 includes a storage area, a carrier area and a peripheral logic area, and forming a stacked structure on the storage area and the peripheral logic area, the stacked structure consisting of a coupling layer 102, a floating gate polysilicon layer 104, an inter-electrode dielectric layer 105, a control gate polysilicon layer 106, and a hard mask layer 107 stacked in sequence from bottom to top;
[0044] In some embodiments, a shallow trench isolation 103 is formed on the substrate 101 in step 1 to define an active region.
[0045] In some embodiments, the coupling layer 102 in step 1 is an oxide layer.
[0046] In some embodiments, the inter-electrode dielectric layer 105 in step 1 is an ONO layer, and the ONO layer is composed of a first oxide layer, a nitride layer, and a second oxide layer stacked in sequence from bottom to top.
[0047] In some embodiments, the material of the hard mask layer 107 in step 1 is silicon dioxide.
[0048] In some embodiments, the hard mask layer 107 in step 1 is formed by furnace thermal oxidation, which has better thickness stability and the height of the memory cell can be defined by adjusting the thickness of the layer.
[0049] Step 2: forming an etch stop layer 108 on the hard mask layer 107 to form Figure 5 In the structure shown, in the subsequent grinding of the word line polysilicon layer 111, the chemical mechanical planarization grinding can stably stop on the etch stop layer 108, which significantly improves the thickness difference and load effect of the chemical mechanical planarization grinding, creates a relatively stable front layer for the peripheral logic area, and the front layer thickness uniformity between different wafers is good;
[0050] In some embodiments, the material of the etch stop layer 108 in step 2 is silicon nitride. The etch stop layer 108 can be formed by chemical vapor deposition or furnace deposition.
[0051] Step 3: forming a word line trench on the etch stop layer 108 on the storage area and the stacked structure thereunder, forming a sidewall structure 109 on the sidewall of the word line trench, forming a tunnel oxide layer 110 in the word line trench, and then forming a word line polysilicon layer 111 filling the word line trench and covering the etch stop layer 108, forming a Figure 7 The structure shown;
[0052] In some embodiments, the method for forming the word line trench in step three includes: etching the etch stop layer 108 of the storage area and the hard mask layer 107 thereunder to form a first trench, forming a first trench as shown in FIG. Figure 6 The structure shown in FIG. 1 is a structure in which a first sidewall structure is formed in the first trench, and the first sidewall structure covers the sidewall of the first trench; the control gate polysilicon layer 106 and the inter-electrode dielectric layer 105 at the bottom wall of the first trench are etched to form a second trench; a second sidewall structure is formed in the second trench, and the second sidewall structure covers part of the sidewall of the second trench; the floating gate polysilicon layer 104 and the coupling layer 102 at the bottom wall of the second trench are etched to form a third trench; a tunneling oxide layer 110 is formed, and the tunneling oxide layer 110 covers the bottom wall and sidewall of the third trench.
[0053] Step 4: Grind the word line polysilicon layer 111 onto the etch stop layer 108 to form Figure 8 The structure shown;
[0054] In some embodiments, the polishing method in step 4 is chemical mechanical planarization polishing. Chemical mechanical planarization polishing can stably stop on the etch stop layer 108, significantly improve the thickness range and loading effect of chemical mechanical planarization polishing, and create a relatively stable front layer for etching with good thickness uniformity.
[0055] Step 5: Remove the etching stop layer 108 to form Fig. 9 In the structure shown, the protruding portion of the word line polysilicon layer 111 relative to the hard mask layer 107 is removed, and the hard mask layer 107 of the peripheral logic area and the control gate polysilicon layer 106 and the floating gate polysilicon layer 104 thereunder are removed.
[0056] In some embodiments, in step five, the etch stop layer 108 is removed by wet etching.
[0057] In some embodiments, in step five, a phosphoric acid solution is used to remove the etch stop layer 108 .
[0058] In some embodiments, in step 5, the reference sidewalls on the back of the wafer are removed while the etch stop layer 108 is removed. This process does not add a SIN removal process, and also saves the process steps of adjusting the height of the non-peripheral logic area by wet etching, thereby increasing the window for etching the peripheral logic area and the control gate polysilicon layer 106 and the floating gate polysilicon layer 104.
[0059] In some embodiments, in step five, a thermal oxidation method is used to remove the protruding portion of the word line polysilicon layer 111 relative to the hard mask layer 107 .
[0060] In some embodiments, in step five, a blanket etching method is used to remove the protruding portion of the word line polysilicon layer 111 relative to the hard mask layer 107 .
[0061] In some embodiments, in step five, the hard mask layer 107 of the peripheral logic region and the control gate polysilicon layer 106 and the floating gate polysilicon layer 104 thereunder are removed by dry etching.
[0062] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0063] In summary, the present invention can stably stop on the etch stop layer by controlling the grinding, the front hard mask layer is furnace-grown and has a flat pattern, avoiding the influence of etching unevenness caused by the front layer, improving the grinding thickness difference and load effect, and creating a relatively stable front layer with good thickness uniformity. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.
[0064] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for increasing a process window of a peripheral logic region, characterized in that: At least: Step 1, providing a substrate, wherein the substrate comprises a storage area, a carrier area and a peripheral logic area, and forming a stacked structure on the storage area and the peripheral logic area, wherein the stacked structure consists of a coupling layer, a floating gate polysilicon layer, an inter-electrode dielectric layer, a control gate polysilicon layer, and a hard mask layer stacked in sequence from bottom to top; Step 2: forming an etch stop layer on the hard mask layer; Step 3, forming a word line trench on the etch stop layer on the storage area and the stacked structure thereunder, forming a tunnel oxide layer in the word line trench, and then forming a word line polysilicon layer filling the word line trench and covering the etch stop layer; Step 4, grinding the word line polysilicon layer onto the etch stop layer; Step 5: remove the etch stop layer, remove the protruding portion of the word line polysilicon layer relative to the hard mask layer, and remove the hard mask layer of the peripheral logic area and the control gate polysilicon layer and the floating gate polysilicon layer thereunder.
2. The method for increasing the process window of the peripheral logic area according to claim 1, characterized in that: In step 1, shallow trench isolation is formed on the substrate to define an active area.
3. The method for increasing the process window of the peripheral logic area according to claim 1, characterized in that: The coupling layer in step 1 is an oxide layer.
4. The method for increasing the process window of the peripheral logic area according to claim 1, characterized in that: The inter-electrode dielectric layer in step 1 is an ONO layer, and the ONO layer is composed of a first oxide layer, a nitride layer, and a second oxide layer stacked in sequence from bottom to top.
5. The method for increasing the process window of the peripheral logic area according to claim 1, characterized in that: The material of the hard mask layer in step 1 is silicon dioxide.
6. The method for increasing the process window of the peripheral logic area according to claim 5, characterized in that: The hard mask layer in step 1 is formed by furnace thermal oxidation.
7. The method for increasing the process window of the peripheral logic area according to claim 1, characterized in that: The material of the etching stop layer in step 2 is silicon nitride.
8. The method for increasing the process window of the peripheral logic area according to claim 1, characterized in that: The method for forming the word line trench in step 3 includes: etching the etch stop layer of the storage area and the hard mask layer thereunder to form a first trench; forming a first sidewall structure in the first trench, wherein the first sidewall structure covers the sidewall of the first trench; etching the control gate polysilicon layer and the inter-electrode dielectric layer at the bottom wall of the first trench to form a second trench; A second sidewall structure is formed in the second trench, and the second sidewall structure covers a portion of the sidewall of the second trench; the floating gate polysilicon layer and the coupling layer at the bottom wall of the second trench are etched to form a third trench; and the tunneling oxide layer is formed, and the tunneling oxide layer covers the bottom wall and sidewall of the third trench.
9. The method for increasing the process window of the peripheral logic area according to claim 1, characterized in that: The grinding method in step 4 is chemical mechanical planarization grinding.
10. The method for increasing the process window of the peripheral logic area according to claim 1, characterized in that: In step five, the etch stop layer is removed by wet etching.
11. The method for increasing the process window of the peripheral logic area according to claim 10, characterized in that: In step five, the etching stop layer is removed using a phosphoric acid solution.
12. The method for increasing the process window of the peripheral logic area according to claim 10, characterized in that: In step five, the etching stop layer is removed while removing the reference sidewall on the back side of the wafer.
13. The method for increasing the process window of the peripheral logic area according to claim 1, characterized in that: In step five, a thermal oxidation method is used to remove the protruding portion of the word line polysilicon layer relative to the hard mask layer.
14. The method for increasing the process window of the peripheral logic area according to claim 1, characterized in that: In step five, a non-patterned etching method is used to remove the protruding portion of the word line polysilicon layer relative to the hard mask layer.
15. The method for increasing the process window of the peripheral logic area according to claim 1, characterized in that: In step five, the hard mask layer of the peripheral logic area and the control gate polysilicon layer and the floating gate polysilicon layer thereunder are removed by dry etching.