Semiconductor device

Abstract

The invention relates to a semiconductor device. The semiconductor device may include: a first memory block including at least one first string connected between at least one first bit line and a first common source line; a second memory block including at least one second string connected between at least one second bit line and a second common source line; and a bit line connection circuit connected between the first bit line and the second bit line and configured to electrically connect or disconnect the first bit line and the second bit line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0141815, filed on October 23, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to a three-dimensional integrated circuit technology, and more particularly, to a three-dimensional semiconductor device technology. Background Art

[0004] Recently, as consumer demands for smaller size, lower power consumption, and high performance electronic devices continue to rise, further improvements in semiconductor device technology are required to provide semiconductor devices capable of storing information and meeting these demands for various electronic devices such as computers and portable communication devices.

[0005] For two-dimensional (2D) semiconductor devices, it is becoming increasingly difficult and expensive to reduce the size of semiconductor devices and increase their data storage capacity, because integrating more memory cells in the same 2D area requires reducing the width of metal lines to a very difficult level. Generally speaking, further reducing the width of metal lines requires solving the problems of manufacturing equipment, very high investment costs, and very long development cycles.

[0006] Therefore, semiconductor devices having a three-dimensional structure have been proposed and are currently being actively researched and developed. Summary of the invention

[0007] Embodiments of the present disclosure provide an improved 3D semiconductor device (hereinafter referred to as a semiconductor device).

[0008] According to an embodiment of the present disclosure, a semiconductor device is provided, which includes: a first storage block, including at least one first string connected between at least one first bit line and a first common source line; a second storage block, including at least one second string connected between at least one second bit line and a second common source line; and a bit line connection circuit, connected between the first bit line and the second bit line and configured to electrically connect or electrically separate the first bit line and the second bit line.

[0009] In an embodiment of the present disclosure, a semiconductor device may include: a first memory device including at least one first string connected between at least one first bit line and a first common source line; and a second memory device including at least one second string connected between at least one second bit line and a second common source line. One of the first memory device and the second memory device may include a bit line connection circuit configured to electrically connect or electrically separate the first bit line and the second bit line.

[0010] These and other features and advantages of the embodiments of the present disclosure will become apparent to those skilled in the art from the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1A and Figure 1B is a diagram for describing a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 2A and Figure 2B is a diagram describing a semiconductor device according to another embodiment of the present disclosure.

[0013] Figure 3A and Figure 3B is a diagram for describing a semiconductor device according to still another embodiment of the present disclosure.

[0014] Figure 4 and Figure 5 is a diagram for describing a semiconductor device according to still another embodiment of the present disclosure. DETAILED DESCRIPTION

[0015] Various embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. The accompanying drawings are schematic diagrams of various embodiments (and intermediate structures). As such, variations in the illustrated configurations and shapes, for example due to manufacturing techniques and / or tolerances, are to be expected. Therefore, the described embodiments should not be interpreted as limited to the specific configurations and shapes shown herein, but may include deviations in configurations and shapes without departing from the spirit and scope of the present disclosure as defined in the appended claims.

[0016] The present invention is described herein with reference to the cross-sectional views and / or plan views of the embodiments of the present disclosure. However, the embodiments of the present disclosure should not be construed as limiting the inventive concept. Although some embodiments of the present disclosure have been shown and described, it will be appreciated by those skilled in the art that these embodiments may be modified without departing from the principles and spirit of the present disclosure.

[0017] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the spirit and scope of the present disclosure, the first element described below may also be referred to as the second or third element.

[0018] It will be further understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly on the other element, directly connected or coupled to the other element, or one or more intermediate elements may be present. Furthermore, the connection / coupling may not be limited to a physical connection, but may also include a non-physical connection, such as a wireless connection.

[0019] In addition, it will also be understood that when an element is referred to as being “between” two elements, it can be the only element between the two elements, or one or more intervening elements may also be present.

[0020] When a first element is referred to as being "over" a second element, it refers not only to a case where the first element is directly formed on the second element but also to a case where a third element is present between the first and second elements. When a first element is referred to as being "on" a second element, it refers to a case where the first element is directly formed on the second element.

[0021] It should be appreciated that the drawings are simplified schematic diagrams of the described devices and may not include well-known details in order to avoid obscuring aspects of the present invention.

[0022] It should also be noted that features present in one embodiment may be used with one or more features of another embodiment without departing from the scope of the present disclosure.

[0023] It should also be noted that like reference numerals denote like elements throughout the various drawings.

[0024] Below, in the accompanying drawings, a direction perpendicular to the top surface of the substrate is defined as a third direction III, and two directions parallel to the top surface of the substrate and intersecting each other are defined as a first direction I and a second direction II, respectively. The substrate may correspond to a single-layer or multi-layer substrate. The second direction II may correspond to an extension direction of a word line, and the first direction I may correspond to an extension direction of a bit line. The first direction I and the second direction II may intersect each other substantially perpendicularly. In the accompanying drawings, the direction indicated by the arrow and the direction opposite thereto represent the same direction.

[0025] The terminology used herein is for describing particular embodiments only and is not intended to limit the scope of the present disclosure.

[0026] As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0027] It will be further understood that when used in this specification, the terms "comprising", "including", "comprising" and "comprising" specify the presence of the stated elements and do not exclude the presence or addition of one or more other elements. As used herein, the term "and / or" includes any and all combinations of one or more of the listed associated items.

[0028] Unless otherwise defined, in view of the present disclosure, all terms used herein including technical and scientific terms have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs.

[0029] It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of this disclosure and the relevant art, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0030] Hereinafter, embodiments according to the technical concept of the present disclosure are described with reference to the accompanying drawings.

[0031] Embodiments of the present disclosure provide a semiconductor device capable of adjusting its data storage capacity or data processing speed as needed.

[0032] If necessary, the performance of the semiconductor device may be adjusted by increasing the data storage capacity of the semiconductor device or improving the data processing speed of the semiconductor device.

[0033] Figure 1A and Figure 1B is a diagram for describing a semiconductor device according to an embodiment of the present disclosure.

[0034] Figure 1A is a perspective view showing a memory block of a semiconductor device. Figure 1B is shown along Figure 1A A cross-sectional view of a plane defined by a first direction I and a third direction III in FIG. The third direction III is a direction perpendicular to the plane defined by the first direction I and the second direction II.

[0035] Reference Figure 1A and Figure 1B , it is shown that the memory block includes two selection lines DSL and SSL, seven word lines WL1 to WL7, and three bit lines BL1, BL2, and BL3, but this is only for convenience of description and the present disclosure is not limited thereto.

[0036] The memory block may be formed above the substrate SUB. The memory block may be formed in a direction perpendicular to the substrate SUB (e.g., a third direction III). The substrate SUB may be a polysilicon layer doped to have a first conductivity type (e.g., P-type). The substrate SUB may be made of a semiconductor material such as at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (AlGaAs), or any combination thereof.

[0037] Common source lines CSL extending in the second direction II may be formed on the substrate SUB. The common source lines CSL may be doped with second conductive type impurities (eg, N-type impurities).

[0038] A plurality of insulating layers IL and a plurality of gate electrodes GE may be alternately stacked on the substrate SUB along a third direction III. In addition, a plurality of gate electrodes GE may be formed to extend in a second direction II. The gate electrodes GE correspond to the word lines WL1 to WL7 and the selection lines DSL and SSL. The insulating layer IL and the gate electrodes GE may be stacked above the substrate SUB in an alternating manner with one insulating layer IL between every two consecutive gate electrodes GE. Therefore, the plurality of gate electrodes GE may include a source selection line SSL, a plurality of word lines WL1 to WL7, and a drain selection line DSL.

[0039] A plurality of pillars P may be formed to extend through a plurality of insulating layers IL and a plurality of gate electrodes GE along a third direction III. Each of the plurality of pillars P may be formed to be connected to a substrate SUB. Each of the plurality of pillars P may include a surface layer S and an inner layer I formed in the surface layer S. The surface layer S of each pillar P may be formed to surround the inner layer I. The surface layer S of each pillar P may include a silicon material doped with a first conductive type impurity. The surface layer S may be used as a channel region. For example, the surface layer S of each pillar P may include a channel layer and a storage layer. The channel layer may include a semiconductor layer having a polycrystalline state, and an embodiment may include a polycrystalline silicon layer. The storage layer may be formed to surround the channel layer. The storage layer may include a blocking layer, a charge trapping layer, and a tunnel insulating layer. The tunnel insulating layer may be formed to surround the channel layer. The charge trapping layer may be formed to surround the tunnel insulating layer. In addition, the blocking layer may be formed to surround the charge trapping layer. The tunnel insulating layer may include an oxide layer. The charge trapping layer may include a nitride layer. The blocking layer may include an oxide layer. The pillars P may also be referred to as a vertical channel structure. The inner layer I of each column P may include an insulating material such as silicon oxide or an air gap. In addition, the size of the channel hole in each column P may decrease toward the substrate SUB. A plurality of contacts CT may be formed between each column P and the bit lines BL1, BL2, and BL3, and the bit lines and strings may be electrically connected. For example, a plurality of contacts CT may electrically connect the inner layer I serving as the channel function of each column P to each of the bit lines BL1, BL2, and BL3.

[0040] The string may be electrically connected between each of the plurality of bit lines BL1, BL2, and BL3 and each common source line CSL. The string may include a storage layer and a channel layer included in an inner layer I of a column P and a plurality of transistors connected in series with each transistor including a gate electrode GE. For example, a transistor electrically connected to the common source line CSL among the plurality of transistors connected in series may be referred to as a source selection transistor SST. In addition, a transistor connected to each of the bit lines BL1, BL2, and BL3 among the plurality of transistors connected in series may be referred to as a drain selection transistor DST. The remaining transistors of the plurality of transistors except the source selection transistor SST and the drain selection transistor DST may be referred to as a unit transistor. In the embodiment according to the present disclosure, Figure 1A and Figure 1B , seven word lines WL1 to WL7 are shown. Therefore, the remaining transistors as unit transistors can also be referred to as seven memory cells MC1 to MC7. That is, the source selection transistor SST refers to a transistor having a gate connected to the source selection line SSL. The drain selection transistor DST refers to a transistor having a gate connected to the drain selection line DSL. The memory cell (i.e., the unit transistor) refers to a transistor having a gate connected to a word line.

[0041] Therefore, the semiconductor device according to the embodiment of the present disclosure may include a plurality of strings, each string including a plurality of memory cells connected in series between a plurality of bit lines and a common source line.

[0042] The semiconductor device constructed as described above according to an embodiment of the present disclosure can control a string connected to a selected bit line by selecting at least one of the plurality of bit lines. The plurality of memory cells MC1 to MC7 included in the string connected to the selected bit line can perform a programming operation, an erasing operation, and a reading operation by controlling the plurality of word lines WL1 to WL7.

[0043] Figure 2A and Figure 2B is a diagram describing a semiconductor device according to another embodiment of the present disclosure.

[0044] Reference Figure 2A and Figure 2B ,Apart from Figure 1A and Figure 1B In addition to the semiconductor device shown in FIG. 1 , the semiconductor device according to another embodiment of the present disclosure may further include a bit line connection circuit BLCC. Figure 1A and Figure 1B Components shown duplicate component descriptions.

[0045] The bit line connection circuit BLCC may be formed above the plurality of bit lines BL1, BL2, and BL3. The plurality of bit lines BL1, BL2, and BL3 may be electrically connected to the bit line connection circuit BLCC through a plurality of first bit line contacts BCT1. In addition, a plurality of second bit line contacts BCT2 may be formed on the bit line connection circuit BLCC.

[0046] The bit line connection circuit BLCC may include a plurality of switches SW electrically connecting or separating the plurality of first bit line contacts BCT1 and the plurality of second bit line contacts BCT2 .

[0047] For example, refer to Figure 2A , a plurality of first bit line contacts BCT1 may be formed between a bit line BL3 and a bit line connection circuit BLCC. That is, a plurality of first bit line contacts BCT1 may be formed below the bit line connection circuit BLCC. In addition, a plurality of second bit line contacts BCT2 may be formed above the bit line connection circuit BLCC. For example, the bit line connection circuit BLCC may include a plurality of switches SW3-1, SW3-2, and SW3-3 that electrically connect or electrically separate the plurality of first bit line contacts BCT1 and the plurality of second bit line contacts BCT2.

[0048] In addition, refer to Figure 2B , a plurality of first bit line contacts BCT1 may be formed between the plurality of bit lines BL1, BL2, and BL3 and the bit line connection circuit BLCC. As described above, a plurality of first bit line contacts BCT1 may be formed below the bit line connection circuit BLCC, and a plurality of second bit line contacts BCT2 may be formed above the bit line connection circuit BLCC.

[0049] The bit line connection circuit BLCC may include at least one of switches SW1 - 3 , SW2 - 3 , and SW3 - 3 connecting or separating first and second bit line contacts BCT1 and BCT2 respectively connected to the bit lines BL1 , BL2 , and BL3 .

[0050] exist Figure 2A In FIG. 1 , the bit line connection circuit BLCC is shown to include three switches SW3 - 1 , SW3 - 2 , and SW3 - 3 connected to one bit line BL3 . Figure 2B , the bit line connection circuit BLCC is shown to include switches SW1-3, SW2-3, and SW3-3 connected to three bit lines BL1, BL2, and BL3, respectively. Therefore, three switches are connected to one bit line, and the total number of switches connected to the three bit lines is 9. Therefore, according to the illustrated embodiment, the bit line connection circuit BLCC may include 9 switches. However, it should be understood that the above description is merely an example according to the embodiment, and the embodiments of the present disclosure are not limited thereto.

[0051] Figure 3A and Figure 3B is a diagram for describing a semiconductor device according to still another embodiment of the present disclosure.

[0052] Reference Figure 3A and Figure 3B , in the semiconductor device, the first memory block BLKA may be formed on a lower side of the bit line connection circuit BLCC, and the second memory block BLKB may be formed on an upper side of the bit line connection circuit BLCC.

[0053] The first storage block BLKA may include at least one first string StringA controlled by a first source selection line SSLA, a plurality of first word lines WL1A to WL7A, and a first drain selection line DSLA. For example, the at least one first string StringA may be connected between a first common source line CSLA and a first bit line BLA1. The first storage block BLKA may include a plurality of first bit lines BLA1, BLA2, and BLA3. For example, the at least one first string StringA may be connected between each of the plurality of first bit lines BLA1, BLA2, and BLA3 and the common source line CSLA.

[0054] The second storage block BLKB may include at least one second string StringB controlled by a second source selection line SSLB, a plurality of first word lines WL1B to WL7B, and a second drain selection line DSLB. For example, at least one second string StringB may be connected between a second common source line CSLB and a second bit line BLB1. The second storage block BLKB may include a plurality of second bit lines BLB1, BLB2, and BLB3. For example, at least one second string StringB may be connected between each of the plurality of second bit lines BLB1, BLB2, and BLB3 and the common source line CSLB.

[0055] A plurality of first bit line contacts BCT1 may be connected between the bit line connection circuit BLCC and the plurality of first bit lines BLA1, BLA2, and BLA3. In addition, a plurality of second bit line contacts BCT2 may be connected between the bit line connection circuit BLCC and the plurality of second bit lines BLB1, BLB2, and BLB3.

[0056] The bit line connection circuit BLCC may include at least one switch SW that electrically connects or separates each of the plurality of first bit lines BLA1, BLA2, and BLA3 and each of the plurality of second bit lines BLB1, BLB2, and BLB3. The detailed description of the structure of the bit line connection circuit BLCC will be described in detail. Figure 2A and Figure 2B A detailed description of the structure of the bit line connection circuit BLCC is given instead.

[0057] According to another embodiment of the present disclosure, the semiconductor device constructed as described above can electrically connect or electrically separate at least one first string StringA of the first storage block BLKA and at least one second string StringB of the second storage block BLKB through the bit line connection circuit BLCC. That is, when the first string StringA and the second string StringB are electrically separated, the semiconductor device can perform operations such as programming operations, erasing operations, or reading operations on the memory cells connected to one of the first string StringA and the second string StringB. In addition, when the first string StringA and the second string StringB are electrically connected, the semiconductor device can perform operations such as programming operations, erasing operations, or reading operations on the memory cells connected to the first string StringA and the second string StringB.

[0058] Therefore, the semiconductor device according to another embodiment of the present disclosure can electrically connect the bit lines BLA1, BLA2, and BLA3 of the first memory block BLKA with the bit lines BLB1, BLB2, and BLB3 of the second memory block BLKB through the bit line connection circuit BLCC, thereby operating the two memory blocks BLKA and BLKB as one memory block. Therefore, the data storage capacity of the semiconductor device can be increased.

[0059] In addition, the semiconductor device according to another embodiment of the present disclosure can electrically separate the bit lines BLA1, BLA2, and BLA3 of the first memory block BLKA from the bit lines BLB1, BLB2, and BLB3 of the second memory block BLKB through the bit line connection circuit BLCC, so that only one of the first memory block BLKA and the second memory block BLKB can be operated at any time. Since the load in the line is reduced compared to the operation in which the two memory blocks BLKA and BLKB are operated together as one memory block, the electrical separation of the two memory blocks BLKA and BLKB allows the data processing speed of the semiconductor device to be significantly improved.

[0060] Figure 4 and Figure 5 is a diagram for describing a semiconductor device according to still another embodiment of the present disclosure.

[0061] Figure 4 and Figure 5 A semiconductor device is shown in which two memory devices MDA and MDB formed in different wafers are connected through bonding pads BPA and BPB. For example, one of the two memory devices MDA and MDB may include a bit line connection circuit BLCC.

[0062] Reference Figure 4The first memory device MDA may include at least one first bit line BLA1, at least one first string StringA connected to the first bit line BLA1, a bit line connection circuit BLCC connected to the first bit line BLA1 through at least one first bit line contact BCT1, and at least one first bonding pad BPA connected to the bit line connection circuit BLCC through at least one second bit line contact BCT2.

[0063] The second memory device MDB may include at least one second bit line BLB1, at least one second string StringB connected to the second bit line BLB1, and at least one second bonding pad BPB formed on the second bit line BLB1. For example, the first memory device MDA and the second memory device MDB may be memory devices formed in different wafers.

[0064] The first memory device MDA and the second memory device MDB may be connected through at least one of the first bonding pad BPA and the second bonding pad BPB.

[0065] According to another embodiment of the present disclosure, the semiconductor device constructed as described above can electrically connect or electrically separate the first string StringA of the first memory device MDA and the second string StringB of the second memory device MDB through the bit line connection circuit BLCC. That is, when the first string StringA and the second string StringB are electrically separated, the semiconductor device can perform operations such as programming operations, erasing operations, or reading operations on the memory cells connected to one of the first string StringA and the second string StringB. In addition, when the first string StringA and the second string StringB are electrically connected, the semiconductor device can perform operations such as programming operations, erasing operations, or reading operations on the memory cells connected to the first string StringA and the second string StringB.

[0066] Therefore, the semiconductor device according to another embodiment of the present disclosure can electrically connect the bit line BLA of the first memory device MDA and the bit line BLB of the second memory device MDB through the bit line connection circuit BLCC, thereby operating the two memory devices MDA and MDB as one memory device. Therefore, the data storage capacity of the semiconductor device can be increased.

[0067] In addition, the semiconductor device according to another embodiment of the present disclosure can electrically separate the bit line BLA of the first memory device MDA and the bit line BLB of the second memory device through the bit line connection circuit BLCC, so that only one of the first memory device MDA and the second memory device MDB is operated. Therefore, compared with the case where the two memory devices MDA and MDB are operated as one memory device, the load in the line or between the lines can be reduced by electrically separating the two memory devices MDA and MDB, thereby improving the data processing speed of the semiconductor device.

[0068] Reference Figure 5 , the first memory device MDA may include at least one first bit line BLA, at least one first string StringA connected to the first bit line BLA, and at least one first bonding pad BPA formed on the first bit line BLA.

[0069] The second memory device MDB may include at least one second bit line BLB, at least one second string StringB connected to the second bit line BLB, a bit line connection circuit BLCC connected to the second bit line BLB through at least one second bit line contact BCT2, and at least one second bonding pad BPB connected to the bit line connection circuit BLCC through at least one first bit line contact BCT1. For example, the first memory device MDA and the second memory device MDB may be memory devices formed in different wafers.

[0070] The first memory device MDA and the second memory device MDB may be connected through at least one of the pair of the first bonding pad BPA and the second bonding pad BPB.

[0071] According to another embodiment of the present disclosure, the semiconductor device constructed as described above can electrically connect or electrically separate at least one first string StringA of the first memory device MDA and at least one second string StringB of the second memory device MDB through the bit line connection circuit BLCC. That is, when the first string StringA and the second string StringB are electrically separated, the semiconductor device can perform operations such as programming operations, erasing operations, or reading operations on the memory cells connected to one of the first string StringA and the second string StringB. In addition, when the first string StringA and the second string StringB are electrically connected, the semiconductor device can perform operations such as programming operations, erasing operations, or reading operations on the memory cells connected to the first string StringA and the second string StringB.

[0072] Therefore, the semiconductor device according to another embodiment of the present disclosure can electrically connect the bit line BLA of the first memory device MDA and the bit line BLB of the second memory device MDB through the bit line connection circuit BLCC, thereby operating the two memory devices MDA and MDB as one memory device. Therefore, the data storage capacity of the semiconductor device can be increased.

[0073] In addition, the semiconductor device according to another embodiment of the present disclosure can electrically separate the bit line BLA of the first memory device MDA and the bit line BLB of the second memory device MDB through the bit line connection circuit BLCC, so that only one of the first memory device MDA and the second memory device MDB is operated. Therefore, compared with the case where the two memory devices MDA and MDB are operated as one memory device, the load between the lines can be reduced by electrically separating the two memory devices MDA and MDB, thereby improving the data processing speed of the semiconductor device.

[0074] Although the embodiments according to the technical concept of the present disclosure have been described above with reference to the accompanying drawings, the embodiments are provided only to describe the embodiments according to the concept of the present disclosure, and the present disclosure is not limited to these embodiments. Without departing from the technical concept and scope of the present disclosure defined in the attached claims, a person of ordinary skill in the art to which the present disclosure belongs may replace, modify and change the embodiments in various ways. Such replacements, modifications and changes may be considered to belong to the scope of the present invention. Therefore, the scope of the present disclosure should not be limited to the above-mentioned embodiments, but should include equivalents thereof.

[0075] In the above-described embodiments, all operations may be selectively performed or some operations may be omitted. In each embodiment, operations may not necessarily be performed in the order described and operations may be rearranged. The embodiments disclosed in this specification and the accompanying drawings are merely examples to promote understanding of the present disclosure, and the present disclosure is not limited thereto. That is, it should be apparent to those skilled in the art that various modifications may be made based on the technical scope of the present disclosure.

[0076] Embodiments of the present disclosure have been described in the drawings and the specification. Although specific terms are used herein, these are only for describing embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-described embodiments and many variations may exist within the scope of the present disclosure. It should be apparent to those skilled in the art that, in addition to the embodiments disclosed herein, various modifications may also be made based on the technical scope of the present disclosure. In addition, the embodiments may be combined to form additional embodiments.

Claims

1. A semiconductor device comprising: A first memory block including at least one first string connected between at least one first bit line and a first common source line; a second memory block including at least one second string connected between at least one second bit line and a second common source line; as well as The bit line connection circuit is connected between the first bit line and the second bit line and electrically connects or separates the first bit line and the second bit line.

2. The semiconductor device according to claim 1, wherein Each of the first string and the second string includes a plurality of memory cells.

3. The semiconductor device according to claim 1, wherein The bit line connection circuit includes at least one switch that electrically connects or separates the first bit line and the second bit line.

4. The semiconductor device according to claim 1, wherein The bit line connection circuit is disposed above the first memory block, and The second memory block is disposed above the bit line connection circuit.

5. A semiconductor device comprising: A first memory device including at least one first string connected between at least one first bit line and a first common source line; as well as a second memory device including at least one second string connected between at least one second bit line and a second common source line, One of the first memory device and the second memory device includes a bit line connection circuit for electrically connecting or disconnecting the first bit line and the second bit line.

6. The semiconductor device according to claim 5, wherein: The first string and the second string each include a plurality of memory cells.

7. The semiconductor device according to claim 5, wherein: The bit line connection circuit includes at least one switch that electrically connects or separates the first bit line and the second bit line.

8. The semiconductor device according to claim 5, wherein: The first memory device and the second memory device are formed in different wafers.

9. The semiconductor device according to claim 8, wherein: The second memory device is disposed above the first memory device, and The first memory device and the second memory device are connected by at least one bonding pad.

10. A semiconductor device comprising: a plurality of memory blocks, each memory block comprising at least one string connected between at least one bit line and a first common source line; as well as A plurality of bit line connection circuits, each of which electrically connects or disconnects at least two of the plurality of memory blocks by electrically connecting at least one bit line of one memory block with at least one bit line of another memory block.

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