Chalcogenide-based memory device and electronic apparatus including same

Abstract

A chalcogenide-based memory device capable of implementing a multi-level memory and an electronic apparatus including the chalcogenide-based memory device are provided. The memory device includes: a first electrode and a second electrode arranged to be spaced apart from each other; and a memory layer disposed between the first electrode and the second electrode, and including a plurality of memory material layers having different threshold voltages from each other. Each of the plurality of memory material layers includes a chalcogenide-based material, has a bi-directional threshold switching (OTS) characteristic, and is configured to have a threshold voltage that varies according to a polarity and an intensity of an applied voltage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0143247 filed in the Korean Intellectual Property Office on October 24, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] One or more embodiments relate to a chalcogenide-based memory device for implementing a multi-level memory and an electronic device including the chalcogenide-based memory device. Background Art

[0004] In accordance with the trend toward lighter, thinner and smaller electronic devices and electrical appliances, the demand for high integration of memory devices has also increased. In a memory device having a cross-point structure, word lines and bit lines cross each other vertically, and a memory cell is arranged at each intersection area. The above structure has a memory cell with a small planar size. Typically, a memory cell in a memory device having a cross-point structure includes a 2-terminal selector and a memory device connected in series to prevent and / or reduce the flow of sneak current between adjacent memory cells. As a result, the aspect ratio of a unit memory cell increases, so the manufacturing process of the memory cell becomes complicated, and there is a limitation in increasing the memory capacity of the memory device. Summary of the invention

[0005] A chalcogenide-based memory device for implementing a multi-level memory and an electronic device including the chalcogenide-based memory device are provided.

[0006] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments of the disclosure.

[0007] According to at least one embodiment, a memory device is provided, comprising a first electrode and a second electrode spaced apart from each other, and a memory layer between the first electrode and the second electrode, the memory layer comprising a plurality of memory material layers having threshold voltages different from each other, and wherein each of the plurality of memory material layers comprises a chalcogenide-based material having an o-threshold switching (OTS) characteristic and is configured to have a threshold voltage that varies according to the polarity and magnitude of an applied voltage.

[0008] Each of the plurality of memory material layers may include a chalcogenide element including at least one of Se and Te and at least one of Ge, As, and Sb.

[0009] At least one of the plurality of memory material layers may further include at least one of In, Al, C, B, Sr, Ga, O, N, Si, Ca, P, and S.

[0010] The multiple memory material layers may have different threshold voltages according to their composition or composition and thickness.

[0011] The plurality of memory material layers may be arranged perpendicular to the first electrode and the second electrode and electrically connected to each other in parallel.

[0012] When in a plan view, a plurality of memory material layers may be arranged parallel to each other.

[0013] When in a plan view, the plurality of memory material layers may be arranged in concentric circles.

[0014] When the number of the plurality of memory material layers is n, the memory device may be configured to implement 2*(n+1) level states.

[0015] Each of the plurality of memory material layers may be configured to achieve a low threshold voltage state and a high threshold voltage state by using write voltage pulses of different polarities.

[0016] According to another embodiment, a memory device includes: a plurality of memory cells, and each memory cell includes a first electrode and a second electrode spaced apart from each other; and a memory layer between the first electrode and the second electrode, the memory layer including a plurality of memory material layers having different threshold voltages, and wherein each of the plurality of memory material layers includes a chalcogenide-based material, has an o-threshold switching (OTS) characteristic, and is configured to have a threshold voltage that varies according to the polarity and magnitude of an applied voltage.

[0017] Each of the plurality of memory material layers may include a chalcogenide element including at least one of Se or Te and at least one of Ge, As, or Sb.

[0018] Each of the plurality of memory material layers may further include at least one of In, Al, C, B, Sr, Ga, O, N, Si, Ca, P, or S.

[0019] The multiple memory material layers may have different threshold voltages according to their composition or composition and thickness.

[0020] The plurality of memory material layers may be arranged perpendicular to the first electrode and the second electrode and electrically connected to each other in parallel.

[0021] When the number of the plurality of memory material layers is n, the memory cell may be configured to implement 2*(n+1) level states.

[0022] Each of the plurality of memory material layers may be configured to achieve a low threshold voltage state and a high threshold voltage state by using write voltage pulses of different polarities.

[0023] The memory device may include a plurality of bit lines extending in a first direction and a plurality of word lines extending in a second direction crossing the first direction, and the plurality of memory cells are respectively disposed at points where the plurality of bit lines and the plurality of word lines cross each other.

[0024] The memory device may include a plurality of word planes extending along a plane including the first direction and the second direction and arranged to be spaced apart from each other in the third direction, and vertical bit lines passing through the plurality of word planes and extending in the third direction, and the memory layer may be disposed between the vertical bit lines and each of the word planes.

[0025] Multiple memory material layers may be stacked in the third direction.

[0026] According to another embodiment, an electronic device includes the above-mentioned memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent through the following description in conjunction with the accompanying drawings, in which:

[0028] Figure 1 is a cross-sectional view of a memory device according to at least one embodiment;

[0029] Figure 2 is a graph showing an example of voltage-current characteristics of a memory layer in a memory device according to at least one embodiment;

[0030] Figure 3A is a graph illustrating an example of bias voltages for performing a set operation and a read operation in a memory device according to at least one embodiment;

[0031] Figure 3B is a graph showing an example of bias voltages for performing a reset operation and a read operation in a memory device according to at least one embodiment;

[0032] Figure 4 is a graph showing an example of voltage-current characteristics according to polarity magnitudes of a write voltage applied to a memory layer during a reset operation of a memory device according to at least one embodiment;

[0033] Figure 5is a graph showing changes in a reset threshold voltage and a set threshold voltage according to a write voltage applied to a memory layer in a memory device according to at least one embodiment;

[0034] Fig. 6A is a cross-sectional view schematically showing a memory device according to another embodiment;

[0035] Figure 6B yes Fig. 6A A plan view of a memory layer;

[0036] Figure 7 yes Fig. 6A A circuit diagram of a memory device;

[0037] Figure 8 Is to show about Fig. 6A A graph of an example of voltage-current characteristics of each of the first, second, and third memory material layers shown in;

[0038] Fig. 9 It is shown that Fig. 6A A graph of voltage-current characteristics of a memory layer of the first, second and third memory material layers shown in FIG.

[0039] Fig.10 is shown when applied to Fig. 6A A diagram of resistance states of first, second and third memory material layers when a write voltage of a memory device is less than a first threshold voltage;

[0040] Fig.11 is shown when applied to Fig. 6A A diagram of resistance states of first, second and third memory material layers when a write voltage of a memory device is greater than a first threshold voltage and less than a second threshold voltage;

[0041] Fig.12 is shown when applied to Fig. 6A A diagram of resistance states of the first, second and third memory material layers when a write voltage of the memory device is greater than a second threshold voltage and less than a third threshold voltage;

[0042] Fig.13 is shown when applied to Fig. 6A A diagram of resistance states of first, second and third memory material layers when a write voltage of a memory device is greater than a third threshold voltage;

[0043] Fig.14 It shows that Fig.10 The diagram shows that when the write voltage is less than the first threshold voltage, the first memory material layer can achieve two resistance states according to the bias voltage;

[0044] Fig.15It is a display manufacturing Fig. 6A FIG. 1 is a diagram of an example of a method for a memory device as shown in FIG. 1 ;

[0045] Fig.16 It shows the manufacturing Fig. 6A FIG. 1 is another example of a method for a memory device;

[0046] Fig.17A is a schematic cross-sectional view of a memory device according to another embodiment;

[0047] Fig. 17B yes Fig.17A A plan view of a memory layer;

[0048] Fig.18 is a perspective view schematically showing a memory device according to another embodiment;

[0049] Fig.19 It is shown Fig.18 a diagram of an enlarged view of a memory cell in a memory device of FIG.

[0050] Fig. 20 is shown for selection Fig.18 A plan view of an example of the operation of a particular memory cell in a memory device;

[0051] Fig.21 is a perspective view schematically illustrating a memory device according to at least one embodiment;

[0052] Fig. 22 It is schematically shown Fig.21 A cross-sectional view of a structure of a memory cell in a memory device;

[0053] Fig.23 is a conceptual diagram schematically illustrating an example device architecture that can be applied to an electronic device;

[0054] Fig.24 is a block diagram of a memory system according to at least one embodiment; and

[0055] Fig.25 is a block diagram illustrating a neuromorphic device and an external device connected to the neuromorphic device according to at least one embodiment. DETAILED DESCRIPTION

[0056] Reference will now be made in detail to embodiments, examples of which are shown in the accompanying drawings, wherein the same reference numerals always represent the same elements. In this regard, the present embodiment may have different forms and should not be construed as being limited to the description set forth herein. Therefore, the embodiments are described below only by reference to the accompanying drawings to explain various aspects. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items. Expressions such as "at least one of..." modify the entire element list when following the element list, rather than modifying the individual elements in the list. When the term "about" or "substantially" is used in conjunction with numerical and / or geometric terms in this specification, it is intended that the associated numerical values ​​include manufacturing tolerances (e.g., ±10%) around the numerical values. In addition, whether or not numerical and / or geometric terms are modified to "about" or "substantially", it should be understood that these values ​​should be interpreted as including manufacturing or operating tolerances (e.g., ±10%) around the numerical and / or geometric values.

[0057] Hereinafter, one or more embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals represent the same components, and the sizes of the components in the accompanying drawings may be exaggerated for ease of explanation. The embodiments of the present disclosure can be modified in various ways and can be embodied in many different forms.

[0058] When a layer, film, region or panel is referred to as being "on" another element, it may be directly on / below / at the left / right side of another layer or substrate, or there may be an intermediate layer. In addition, it will also be understood that spatially relative terms, such as "above", "top", etc., are intended to cover different orientations of the device in use or operation other than the orientation depicted in the figure, and the device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative terms used herein are interpreted accordingly. Unless there is a clearly different meaning in the context, expressions used in the singular include expressions in the plural. It will be further understood that when a part is referred to as "including" another component, the part may not exclude another component, but may further include another component, unless the context indicates otherwise.

[0059] The use of the term "above" and similar indicative terms may correspond to both the singular and the plural. Furthermore, the steps of all methods described herein can be performed in any suitable order unless otherwise indicated herein or clearly contradicted by context.

[0060] In addition, the terms "... unit", "... module" used in this document specify a unit for processing at least one function or operation, and this can be implemented as a processing circuit, such as hardware or software or a combination of hardware and software. For example, the processing circuit can more specifically include but is not limited to a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc. The processing circuit may include electrical components such as at least one of a transistor, a resistor, a capacitor, etc. and / or an electronic circuit including the components.

[0061] Furthermore, the connecting lines or connectors shown in the figures are intended to represent example functional relationships and / or physical or logical couplings between the various elements. It should be noted that many alternative or additional functional relationships, physical connections or logical connections may be present in a practical device.

[0062] The use of any and all examples, or exemplary language provided herein, is intended merely to better illuminate the present disclosure and does not pose a limitation on the scope of the present disclosure unless otherwise claimed.

[0063] Figure 1 is a cross-sectional view schematically illustrating a memory device 10 according to at least one embodiment.

[0064] refer to Figure 1 , the memory device 10 may include a first electrode 11 , a second electrode 12 spaced apart from the first electrode 11 so as to face the first electrode 11 , and a memory layer 13 disposed between the first electrode 11 and the second electrode 12 .

[0065] The first electrode 11 and the second electrode 12 may apply a voltage to the memory layer 13. To this end, the first electrode 11 and the second electrode 12 may each include a conductive material such as a metal, a conductive metal nitride, a conductive metal oxide, and / or a combination thereof. For example, the first electrode 11 and the second electrode 12 may each include at least one of titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium carbon nitride (TiCN), titanium carbon silicon nitride (TiCSiN), tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), tungsten silicide (WSi), titanium tungsten (TiW), molybdenum nitride (MoN), niobium nitride (NbN), titanium boron nitride (TiBN), zirconium silicon nitride (ZrN), or the like. The invention relates to a novel nanostructured carbon nitride (N-2O3), a tungsten ...

[0066] The memory layer 13 may be configured to have a bidirectional threshold switching (OTS) characteristic, which has a high resistance state when a voltage less than a threshold voltage is applied, and has a low resistance state when a voltage greater than the threshold voltage is applied. In addition, the memory layer 13 may have a memory characteristic in which the threshold voltage is shifted, for example, according to the polarity and strength of a bias voltage applied thereto. Therefore, the memory layer 13 may have a self-selective memory characteristic, by which a memory function and a selector function can be performed using only a single material.

[0067] The memory layer 13 may include a chalcogenide-based material. For example, the memory layer 13 may include a chalcogenide element including at least one of Se and Te and at least one of Ge, As, and Sb. In addition, the memory layer may also include at least one of In, Al, C, B, Sr, Ga, O, N, Si, Ca, P, and S. For example, the memory layer 13 may include at least one of GeAsSe, GeAsSeIn, GeAsSeSIn, GeAsSeSb, GeAsSeTe, GeAsSeAl, GeAsSeAlIn, GeSbSe, GeSbSeN, and / or the like.

[0068] Figure 2 is a graph showing an example of voltage-current characteristics of the memory layer 13 in the memory device 10 according to at least one embodiment.

[0069] refer to Figure 2 , the memory layer 13 may have one of a first state (LVS; low-Vth state) in which the threshold voltage is relatively low and a second state (HVS; high-Vth state) in which the threshold voltage is relatively high. For example, in the first state, the threshold voltage of the memory layer 13 may be a first voltage V1, and in the second state, the threshold voltage of the memory layer 13 may be a second voltage V2 greater than the first voltage V1.

[0070] When the memory layer 13 is in the first state, when a voltage less than the first voltage V1 is applied to the memory layer 13, current rarely flows between both ends of the memory layer 13, and when a voltage greater than the first voltage V1 is applied to the memory layer 13, the memory layer 13 is turned on and current flows through the memory layer 13. In addition, when the memory layer 13 is in the second state, when a voltage less than the second voltage V2 is applied to the memory layer 13, current rarely flows between both ends of the memory layer 13, and when a voltage greater than the second voltage V2 is applied to the memory layer 13, the memory layer 13 is turned on and current flows through the memory layer 13.

[0071] Therefore, a voltage between the first voltage V1 and the second voltage V2 may be selected as the read voltage VR. When the memory layer 13 is in the first state and the read voltage VR is applied to the memory layer 13, current flows through the memory layer 13, and at this time, the value of the data stored in the memory layer 13 may be defined as "1". When the memory layer 13 is in the second state and the read voltage VR is applied to the memory layer 13, current rarely flows through the memory layer 13, and at this time, the value of the data stored in the memory layer 13 may be defined as "0". In other words, when measuring the current flowing through the memory layer 13 while the read voltage VR is applied to the memory layer 13, the value of the data stored in the memory layer 13 may be read.

[0072] In addition, when the memory layer 13 is in the first state and a negative bias voltage is applied to the memory layer 13, the threshold voltage of the memory layer 13 increases, and the memory layer 13 can be converted to the second state, for example, by phase change. For example, when a negative third voltage V3 is applied to the memory layer 13, the memory layer 13 can be converted to the second state. The above operation may be referred to as a reset operation. In addition, when the memory layer 13 is in the second state and a positive (+) bias voltage greater than the second voltage V2 is applied to the memory layer 13, the threshold voltage of the memory layer 13 decreases, and the memory layer 13 can be converted to the first state. The above operation may be referred to as a set operation. The difference between the second voltage V2 (e.g., the reset threshold voltage) and the first voltage V1 (e.g., the set threshold voltage) corresponds to the memory window.

[0073] Figure 3Ais a graph showing an example of bias voltages for a set operation and a read operation in the memory device 10 according to at least one embodiment. Figure 3A , a positive bias voltage greater than or equal to the second voltage V2 may be applied to the memory layer 13 in a set operation. Then, the threshold voltage of the memory layer 13 may be transformed into the first voltage V1. Thereafter, in a read operation, a positive read voltage VR between the first voltage V1 and the second voltage V2 may be applied to the memory layer 13. When the read voltage VR is applied, the memory layer 13 may be turned on.

[0074] Figure 3B is a graph showing an example of bias voltages for reset and read operations in memory device 10 according to at least one embodiment. Figure 3B , in a reset operation, a negative bias voltage (i.e., a third voltage V3) may be applied to the memory layer 13. The absolute value of the third voltage V3 may be equal to the second voltage V2, or may be slightly less than or greater than the second voltage V2. Then, the threshold voltage of the memory layer 13 may be shifted to the second voltage V2 which is greater than the first voltage V1. Thereafter, in a read operation, a positive read voltage VR between the first voltage V1 and the second voltage V2 may be applied to the memory layer 13. When the read voltage VR is applied, the memory layer 13 may be turned off.

[0075] As described above, the memory layer 13 of the memory device 10 may have an OTS characteristic and simultaneously have a memory characteristic of changing a threshold voltage. Specifically, the threshold voltage of the memory layer 13 may shift according to the polarity of a bias voltage applied to the memory layer 13. In this viewpoint, the memory device 10 may be a self-selecting memory device having a polarity-dependent threshold voltage shift characteristic.

[0076] Figure 4 is a graph showing an example of voltage-current characteristics according to the polarity magnitude of a write voltage applied to the memory layer 13 during a reset operation of the memory device 10 according to an embodiment. Figure 4 In FIG. 1 , “B” indicates the voltage-current characteristic when the (-) polarity of the write voltage is greater than “A”. Figure 4 , as the magnitude of the (-) polarity in the write voltage applied to the memory layer 13 increases, the threshold voltage increases and the resistance also increases.

[0077] Figure 5 is a graph showing changes in a reset threshold voltage and a set threshold voltage according to a write voltage applied to a memory layer 13 in a memory device 10 according to an embodiment. Figure 5 In the example, a write voltage of positive (+) polarity is used to measure the set threshold voltage, and a write voltage of negative (-) polarity is used to measure the reset threshold voltage. Figure 5, as the write voltage applied to the memory layer 13 increases, the reset threshold voltage RESET Vth is saturated.

[0078] exist Figure 1 In the memory device 10, there is a limitation in realizing multi-level by controlling the write voltage due to the saturation effect of the threshold voltage occurring in the memory layer 13. In addition, the chalcogenide-based material forming the memory layer 13 may show a characteristic shift over time due to amorphous stability, and it is difficult to realize multi-level due to the characteristic shift.

[0079] Fig. 6A is a cross-sectional view schematically illustrating a memory device 100 according to at least one embodiment. Figure 6B yes Fig. 6A FIG. 1 is a plan view of a memory layer 130 .

[0080] refer to Fig. 6A and Figure 6B The memory device 100 includes a first electrode 110 and a second electrode 120 spaced apart from each other, and a memory layer 130 disposed between the first electrode 110 and the second electrode 120. The first electrode 110 and the second electrode 120 are respectively connected to Figure 1 The first electrode 11 and the second electrode 12 shown in FIG. 1 are the same (and / or substantially similar), and a detailed description thereof is omitted.

[0081] The memory layer 130 includes a first memory material layer 131, a second memory material layer 132, and a third memory material layer 133 arranged between the first electrode 110 and the second electrode 120. The first memory material layer 131, the second memory material layer 132, and the third memory material layer 133 may be arranged perpendicular to the first electrode 110 and the second electrode 120. When viewed from a plane, the first memory material layer 131, the second memory material layer 132, and the third memory material layer 133 may be arranged parallel to each other. Each of the first memory material layer 131, the second memory material layer 132, and the third memory material layer 133 may have a self-selective memory characteristic, which is configured like Figure 1 In other words, each of the first memory material layer 131, the second memory material layer 132, and the third memory material layer 133 may have a bidirectional threshold switching (OTS) characteristic and may be configured to have a threshold voltage that varies according to the polarity and strength of an applied voltage.

[0082] Each of the first memory material layer 131, the second memory material layer 132, and the third memory material layer 133 may include a chalcogenide-based material. For example, each of the first memory material layer 131, the second memory material layer 132, and the third memory material layer 133 may include a chalcogenide element, which includes at least one of Se and Te and at least one of Ge, As, and Sb. In addition, each of the first memory material layer 131, the second memory material layer 132, and the third memory material layer 133 may also include at least one of In, Al, C, B, Sr, Ga, O, N, Si, Ca, P, and S. For example, each of the first memory material layer 131, the second memory material layer 132, and the third memory material layer 133 may include at least one of GeAsSe, GeAsSeIn, GeAsSeSIn, GeAsSeSb, GeAsSeTe, GeAsSeAl, GeAsSeAlIn, GeSbSe, GeSbSeN, and / or the like. However, one or more embodiments are not limited thereto.

[0083] The first memory material layer 131, the second memory material layer 132, and the third memory material layer 133 may be formed to have different threshold voltages from each other. For example, the first memory material layer 131 has a first threshold voltage Vth1, the second memory material layer 132 has a second threshold voltage Vth2, and the third memory material layer 133 has a third threshold voltage Vth3. The first memory material layer 131, the second memory material layer 132, and the third memory material layer 133 having different threshold voltages may be formed by adjusting the composition or the composition and thickness of the chalcogenide-based material having the self-selective memory characteristic.

[0084] Figure 7 yes Fig. 6A 1 is a schematic circuit diagram of a memory device 100. Figure 7 , the first memory material layer 131 , the second memory material layer 132 , and the third memory material layer 133 forming the memory layer 130 may be electrically connected in parallel to each other between the first electrode 110 and the second electrode 120 .

[0085] Figure 8 Is to show about Fig. 6A Graphs showing examples of voltage-current characteristics of each of the first, second, and third memory material layers 131, 132, and 133 shown in FIG. Figure 8 , C1 represents the voltage-current characteristic of the first storage material layer 131 , C2 represents the voltage-current characteristic of the second storage material layer 132 , and C3 represents the voltage-current characteristic of the third storage material layer 133 .

[0086] refer to Figure 8 , the first memory material layer 131 has a first threshold voltage Vth1, the second memory material layer 132 has a second threshold voltage Vth2 greater than the first threshold voltage Vth1, and the third memory material layer 133 has a third threshold voltage Vth3 greater than the second threshold voltage Vth2. Additionally, Fig. 9 shows including Figure 8 an example of the voltage-current characteristics of the memory layer 130 including the first, second, and third memory material layers 131, 132, and 133 as shown.

[0087] Hereinafter, a method of implementing a multi-level memory by using the memory device 100 is described. Hereinafter, it is assumed that the first memory material layer 131 has a first threshold voltage Vth1, the second memory material layer 132 has a second threshold voltage Vth2 greater than the first threshold voltage Vth1, and the third memory material layer 133 has a third threshold voltage Vth3 greater than the second threshold voltage Vth2 (i.e., Vth1 < Vth2 < Vth3).

[0088] Fig.10 is a diagram showing Fig. 6A the resistance states of the first memory material layer 131, the second memory material layer 132, and the third memory material layer 133 when the write voltage applied to the

[0089] Referring to Fig.10 , when the write voltage Vw applied between the first electrode 110 and the second electrode 120 is less than the first threshold voltage Vth1 (Vw < Vth1), the first memory material layer 131, the second memory material layer 132, and the third memory material layer 133 are non-conductive and maintain the set state. Hereinafter, the resistance states of the first memory material layer 131, the second memory material layer 132, and the third memory material layer 133 may be R1, R2, and R3, respectively.

[0090] Fig.11 is a diagram showing Fig. 6A the resistance states of the first memory material layer 131, the second memory material layer 132, and the third memory material layer 133 when the write voltage applied to the

[0091] Referring to Fig.11, when the write voltage Vw applied between the first electrode 110 and the second electrode 120 is greater than the first threshold voltage Vth1 and less than the second threshold voltage Vth2 (Vth1 < Vw < Vth2), the first memory material layer 131 conducts and forms a reset state. Here, the resistance state of the first memory material layer 131 can be R4. Additionally, the second and third memory material layers 132 and 133 are not conducted and remain in the set state. Here, the resistance states of the second memory material layer 132 and the third memory material layer 133 can be R2 and R3, respectively. Therefore, the resistance states of the first memory material layer 131, the second memory material layer 132, and the third memory material layer 133 can be R4, R2, and R3, respectively.

[0092] Fig.12 is a diagram showing when applied to Fig. 6A the memory device 100, when the write voltage Vw is greater than the second threshold voltage Vth2 and less than the third threshold voltage Vth3, of the resistance states of the first memory material layer 131, the second memory material layer 132, and the third memory material layer 133.

[0093] Refer to Fig.12 , when the write voltage Vw applied between the first electrode 110 and the second electrode 120 is greater than the second threshold voltage Vth2 and less than the third threshold voltage Vth3 (Vth2 < Vw < Vth3), the first memory material layer 131 and the second memory material layer 132 conduct and form a reset state. Here, the resistance states of the first memory material layer 131 and the second memory material layer 132 can be R4 and R5, respectively. Additionally, the third memory material layer 133 is not conducted and remains in the set state. Here, the resistance state of the third memory material layer 133 can be R3. Therefore, the resistance states of the first memory material layer 131, the second memory material layer 132, and the third memory material layer 133 can be R4, R5, and R3, respectively.

[0094] Fig.13 is a diagram showing when applied to Fig. 6A the memory device 100, when the write voltage Vw is greater than the third threshold voltage Vth3, of the resistance states of the first memory material layer 131, the second memory material layer 132, and the third memory material layer 133.

[0095] Refer to Fig.13, when the write voltage Vw applied between the first electrode 110 and the second electrode 120 is greater than the third threshold voltage Vth3 (Vw > Vth3), the first memory material layer 131, the second memory material layer 132, and the third memory material layer 133 conduct and form a reset state. Hereinafter, the resistance states of the first memory material layer 131, the second memory material layer 132, and the third memory material layer 133 may be R4, R5, and R6, respectively.

[0096] Reference Figures 10 to 13 , when the memory layer 130 includes the first memory material layer 131, the second memory material layer 132, and the third memory material layer 133 having different threshold voltages from each other, the memory layer 130 may indicate four resistance states according to the write voltage Vw.

[0097] Fig.14 is a diagram showing that when the write voltage Vw as Fig.10 shown is less than the first threshold voltage Vth1 (Vw < Vth1), the first memory material layer 131 can achieve two resistance states according to the bias voltage.

[0098] Reference Fig.14 , when the write voltage Vw is less than the first threshold voltage Vth1 and the first threshold voltage Vth1 becomes the first voltage V1 of positive polarity, the first memory material layer 131 maintains the set state as described above. Here, the resistance state of the first storage material layer 131 is R1. In addition, when the write voltage Vw is less than the first threshold voltage Vth1 and the first threshold voltage Vth1 becomes the second voltage V2 of negative voltage, the first memory material layer 131 can form an intermediate state between the set state and the reset state. Here, the resistance state of the first storage material layer 131 is R1'. As described above, when the write voltage Vw is less than the first threshold voltage Vth1, the first memory material layer 131 can achieve two resistance states R1 and R1' according to the bias voltage.

[0099] Similarly, when the write voltage Vw is greater than the first threshold voltage Vth1 of the first memory material layer 131 and less than the second threshold voltage Vth2 (Vth1 < Vw < Vth2), the second memory material layer 132 can achieve two resistance states R2 and R2' according to the bias voltage. In addition, when the write voltage Vw is greater than the second threshold voltage Vth2 and less than the third threshold voltage Vth3 (Vth2 < Vw < Vth3), the third memory material layer 133 can achieve two resistance states R3 and R3' according to the bias voltage. Further, when the write voltage Vw is greater than the third threshold voltage Vth3 (Vw > Vth3), the third memory material layer 133 can achieve two resistance states R6 and R6' according to the bias voltage.

[0100] As described above, when the memory layer 130 includes the first memory material layer 131, the second memory material layer 132, and the third memory material layer 133 having different threshold voltages, eight resistance states may be realized. Therefore, the memory device 100 according to the embodiment may realize a multi-level memory.

[0101] In addition, in the above description, the memory layer 130 includes three memory material layers 131, 132, and 133 having different threshold voltages. However, one or more embodiments are not limited to this example, and the memory layer 130 may include two, four, or more memory material layers. When the memory layer 130 includes n different memory material layers, the memory layer 130 may achieve 2*(n+1) resistance states.

[0102] Fig.15 It shows the manufacturing Fig. 6A FIG. 1 is a diagram of an example method of implementing a memory device 100 as shown in FIG. Fig.15 , a first electrode 110, a memory layer 130, and a second electrode 120 are sequentially deposited on a substrate 101, and the deposited layers are entirely etched by using an etching mask (not shown) to form a pillar-structured memory device 100.

[0103] Fig.16 It shows the manufacturing Fig. 6A FIG. 1 is a diagram of another example method of a memory device 100 shown in FIG. Fig.16 , a dielectric layer 150 is formed on a substrate 101, and then a trench of a certain length is formed in the dielectric layer 150. Here, the trench may be formed to expose the upper surface of the substrate 101. Next, the first electrode 110 and the memory layer 130 are deposited from the bottom of the trench. Next, after a planarization process is performed on the upper portion of the memory layer 130, the second electrode 120 is formed on the upper surface of the planarized memory layer, and the memory device 100 may be formed. Thereafter, the substrate 101 and the dielectric layer 150 may be removed.

[0104] Fig.17A is a cross-sectional view schematically illustrating a memory device 200 according to at least one embodiment. Fig. 17B yes Fig.17A Hereinafter, differences from the above-described embodiment will be described.

[0105] The memory layer 230 is disposed between the first electrode 110 and the second electrode 120, and the memory layer 230 includes a first memory material layer 231, a second memory material layer 232, and a third memory material layer 233 having threshold voltages different from each other. The first memory material layer 231, the second memory material layer 232, and the third memory material layer 233 may be arranged perpendicular to the first electrode 110 and the second electrode 120. Here, when viewed from a plane, the first memory material layer 231, the second memory material layer 232, and the third memory material layer 233 may be arranged as concentric circles. In detail, the second memory material layer 232 is disposed to surround the side surface of the third memory material layer 233, and the first memory material layer 231 may be disposed to surround the side surface of the second memory material layer 232. The first memory material layer 231, the second memory material layer 232, and the third memory material layer 233 are electrically connected to each other in parallel between the first jaw 110 and the second jaw 120. The first, second, and third memory material layers 231 , 232 , and 233 are described above, and a detailed description is omitted. Fig.18 is a perspective view schematically illustrating a memory device 300 according to at least one embodiment. Fig.19 It is a hint Fig.18 FIG. 3 is a diagram of an enlarged view of one memory cell MC in a memory device 300 .

[0106] refer to Fig.18 and Fig.19 , the memory device 300 may have a three-dimensional (3D) cross-point structure. For example, the memory device 300 may include a plurality of bit lines BL extending in a first direction (i.e., an x-axis direction), a plurality of word lines WL extending in a second direction (i.e., a y-axis direction) intersecting the first direction, and a plurality of memory cells MC disposed at points where the plurality of bit lines BL and the plurality of word lines WL intersect each other.

[0107] Each of the plurality of memory cells MC may correspond to, for example Fig. 6A In detail, the lower electrode 310 and the upper electrode 320 may correspond to Fig. 6A The memory layer 330 may include a plurality of memory material layers 331, 332, and 333 having different threshold voltages. The memory layer 330 may correspond to Fig. 6A 1. Thus, the memory layer 330 may have the same Fig. 6A The memory layer 130 in the memory device 100 has the same characteristics as those of the memory layer 130. In addition, each of the plurality of memory cells MC may correspond to Fig.17A The memory device 200 shown in FIG.

[0108] In this structure, the memory cell MC can be driven by the potential difference between the word line WL and the bit line BL connected to both ends of each memory cell MC. Therefore, each memory cell MC can implement the multi-level memory as described above.

[0109] Fig. 20 is shown for selection Fig.18 FIG. 3 is a plan view of an example of operation of a certain memory cell MC in the memory device 300 .

[0110] refer to Fig. 20 , the memory device 300 may further include a row decoder 360 that selectively supplies a voltage to a plurality of word lines WL and a column decoder 370 that selectively supplies a voltage to a plurality of bit lines BL. When a voltage V is applied to a selected memory cell sMC among a plurality of memory cells MC, the row decoder 360 may provide the voltage V to the word line WL connected to the selected memory sMC and provide a voltage V / 2 to the other word lines WL. Here, the column decoder 370 may provide a voltage of 0V to the bit line BL connected to the selected memory sMC and provide a voltage of V / 2 to the other bit lines BL.

[0111] Then, the potential difference between the word line WL and the bit line BL of the selected memory cell sMC is V. On the other hand, the potential difference between the word line WL supplied with the voltage V / 2 and the bit line BL supplied with the voltage V / 2 is 0V. Therefore, the voltage is not applied to the unselected memory cell uMC arranged between the word line WL and the bit line BL not connected to the selected memory cell sMC. In addition, the voltage V / 2 can be applied to both ends of the semi-selected memory cell hMC connected to the same word line WL as the word line of the selected memory cell sMC or the same bit line BL as the bit line of the selected memory cell sMC. Each of the multiple memory cells MC is a self-selection memory device as described above, and therefore, even when the voltage V / 2 is applied, the semi-selected memory cell hMC adjacent to the selected memory cell sMC will not be turned on, and therefore, sneak current rarely occurs.

[0112] Fig.21 is a perspective view schematically illustrating a memory device 400 according to at least one embodiment.

[0113] refer to Fig.21, the memory device 400 may include a plurality of word planes WP, the plurality of word planes WP extending along a plane including a first direction and a second direction and spaced apart from each other along a third direction (i.e., a z-axis direction) intersecting the first direction and the second direction, a plurality of vertical bit lines VBL extending in the third direction and arranged two-dimensionally along the first direction and the second direction. And a plurality of memory cell strings MCS, the plurality of memory cell strings MCS extending in the third direction while surrounding the surface of the plurality of vertical bit lines VBL. The plurality of memory cell strings MCS may also be arranged two-dimensionally in the first direction and the second direction like the plurality of vertical bit lines VBL. Each of the plurality of memory cell strings MCS and each of the plurality of vertical bit lines VBL may be arranged to pass through the plurality of word planes WP in the third direction. Each memory cell string MCS may include a plurality of memory layers ( Fig. 22 of 430).

[0114] Fig. 22 It is schematically shown Fig.21 FIG. 4 is a cross-sectional view of the structure of a memory cell in the memory device 400 .

[0115] refer to Fig. 22 The word plane WP and the memory layer 430 and the vertical bit line VBL surrounded by the word plane WP may form a memory cell. Here, the memory layer 430 may be provided to surround the side surface of the vertical bit line VBL. The word plane WP and the vertical bit line VBL may correspond to Fig. 6A The memory layer 430 may include a plurality of memory material layers 431, 432, and 433 having different threshold voltages. The memory layer 430 may correspond to Fig. 6A Memory layer 130 of memory device 100 is shown in FIG.

[0116] The memory device 100 , 200 , 300 , or 400 according to the above-described embodiments may be used to store data in various electronic devices. Fig.23 is a conceptual diagram schematically illustrating a device architecture applied to an electronic device according to at least one embodiment.

[0117] refer to Fig.23, the cache memory 1510, the ALU 1520, and the control unit 1530 may configure the central processing unit 1500, and the cache memory 1510 may include a static random access memory (SRAM). Separately from the CPU 1500, a main memory 1600 and an auxiliary storage 1700 may be provided. The main memory 1600 may include a DRAM device, and the auxiliary storage 1700 may include the above-mentioned memory device 100 or 200. In some cases, an input / output device 2500 may be provided. In some cases, the device architecture may be implemented in the form that a computing unit device and a memory unit device are adjacent to each other in one chip without distinguishing subunits.

[0118] The memory devices 100 , 200 , 300 , and 400 according to the embodiments may be implemented as a chip-type memory block to be used as a neuromorphic computing platform or to construct a neural network.

[0119] Fig.24 is a block diagram of a memory system 1600 according to at least one embodiment.

[0120] refer to Fig.24 , the memory system 1600 may include a memory controller 1601 and a memory device 1602. The memory controller 1601 performs a control operation on the memory device 1602. For example, the memory controller 1601 may provide the memory device 1602 with a command CMD for performing a program (or record), read, and / or erase operation on an address ADD of the memory device 1602. In addition, data for a program operation and read data may be transmitted between the memory controller 1601 and the memory device 1602.

[0121] The memory device 1602 may include a memory cell array 1610 and a voltage generator 1620. The memory cell array 1610 may include a plurality of memory cells and may include the memory device 100, 200, 300, or 400, according to at least one embodiment.

[0122] The memory controller 1601 may include a processing circuit, such as hardware including a logic circuit, a combination of hardware / software (such as software executed by a processor), or a combination thereof. For example, the processing circuit may specifically include a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc., but is not limited thereto. The memory controller 1601 may operate in response to a request from a host (not shown) and may access the memory device 1602 to control the control operation (e.g., recording / reading operation) as described above, and therefore, the memory controller 1601 may be converted into a dedicated controller. The memory controller 1601 may generate an address ADD and a command CMD for performing a program / read / erase operation on the memory cell array 1610. In addition, in response to a command from the memory controller 1601, the voltage generator 1620 (e.g., a power supply circuit) may generate a voltage control signal for controlling a voltage level of a word line so as to perform data programming or data reading on the memory cell array 1610.

[0123] In addition, the memory controller 1601 may perform a determination operation on the data read from the memory device 1602. For example, based on the data read from the memory cell, the number of on cells and / or the number of off cells may be determined. The memory device 1602 may provide a pass / fail signal (P / F) to the memory controller 1601 based on the determination result on the read data. The memory controller 1601 may control the write / read operation of the memory cell array 1610 with reference to the pass / fail signal (P / F).

[0124] Fig.25 is a block diagram illustrating a neuromorphic device 1700 and an external device connected to the neuromorphic device according to at least one embodiment.

[0125] refer to Fig.25 , the neuromorphic device 1700 may include a processing circuit 1710 and / or an on-chip memory 1720. The neuromorphic device 1700 may include the memory device 100, 200, 300, or 400 according to an embodiment.

[0126] In some embodiments, the processing circuit 1710 may be configured to control functions for driving the neuromorphic device 1700. For example, the processing circuit 1710 may be configured to control the neuromorphic device 1700 by executing a program stored in the on-chip memory 1720. In some embodiments, the processing circuit 1710 may include hardware (such as a logic circuit), a hardware / software combination (such as a processor that executes software), or a combination thereof. For example, the processor may include, but is not limited to, a CPU, a graphics processing unit (GPU), an application processor (AP) included in the neuromorphic device 1700, an ALU, a digital signal processor, a microcomputer, an FPGA, a SoC, a programmable logic unit, a microprocessor, an ASIC, etc. In some embodiments, the processing circuit 1710 may be configured to read / record various data about the external device 1730 and / or execute the neuromorphic device 1700 by using the read / recorded data. In some embodiments, the external device 1730 may include an external memory and / or a sensor array having an image sensor (e.g., a CMOS image sensor circuit).

[0127] In some embodiments, Fig.25 The neuromorphic device 1700 can be applied to a machine learning system. The machine learning system can use various artificial neural network organizations and processing models, such as convolutional neural networks (CNNs), deconvolutional neural networks, repetitive neural networks (RNNs) that selectively include long short-term memory (LSTM) units and / or gated recurrent units (GRUs), stacked neural networks (SNNs), state-space dynamic neural networks (SSDNNs), deep belief networks (DBNs), generative adversarial networks (GANs), and / or restricted Boltzmann machines (RBMs).

[0128] Alternatively and / or additionally, such a machine learning system may include other types of machine learning models, such as linear and / or logistic regression, statistical clustering, Bayesian classification, deterministic trees, dimensionality reduction such as principal component analysis, expert systems, and / or random forests; or combinations thereof. Machine learning models may be used to provide various services and / or applications. For example, image classification services, user authentication services based on biometric information or biometric data, advanced driver assistance system (ADAS) services, voice assistance services, automatic speech recognition (ASR) services, etc. may be performed by electronic devices.

[0129] According to the memory device of the embodiment, the memory layer includes multiple memory material layers, the multiple memory material layers include chalcogenide-based materials and have different threshold voltages, and each of the memory material layers has OTS characteristics and is formed to have a threshold voltage that varies depending on the polarity and intensity of the applied voltage, and therefore, a multi-level memory can be effectively implemented.

[0130] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for the purpose of limitation. The description of features or aspects within each embodiment should generally be considered to be applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope defined by the appended claims.

Claims

1. A memory device, comprising: a first electrode and a second electrode spaced apart from each other; as well as a memory layer between the first electrode and the second electrode, the memory layer including a plurality of memory material layers having threshold voltages different from each other, Each of the plurality of memory material layers comprises: Chalcogenide-based materials, Has an OTS (Two-Way Threshold Switching) feature and Configured to have a threshold voltage that varies with the polarity and magnitude of an applied voltage. 2 . The memory device of claim 1 , wherein each of the plurality of memory material layers comprises a chalcogenide element comprising at least one of Se and Te and at least one of Ge, As, or Sb.

3. The memory device of claim 2, wherein at least one of the plurality of memory material layers further comprises at least one of In, Al, C, B, Sr, Ga, O, N, Si, Ca, P, or S. 4 . The memory device according to claim 1 , wherein the plurality of memory material layers have threshold voltages different from each other according to compositions thereof or the compositions and thicknesses. 5 . The memory device of claim 1 , wherein the plurality of memory material layers are perpendicular to the first electrode and the second electrode and are electrically connected in parallel to each other.

6. The memory device of claim 5, wherein the plurality of memory material layers are parallel to each other when in plan view.

7. The memory device of claim 5, wherein the plurality of memory material layers are in concentric circles when in a plan view.

8. The memory device according to claim 5, wherein: When the number of the plurality of memory material layers is n, 2*(n+1) level states are realized. 9 . The memory device of claim 1 , wherein each of the plurality of memory material layers is configured to use write voltage pulses of different polarities to achieve a low threshold voltage state and a high threshold voltage state.

10. A memory device comprising: a plurality of memory cells, wherein each of the memory cells comprises: A first electrode and a second electrode spaced apart from each other; and a memory layer between the first electrode and the second electrode, the memory layer including a plurality of memory material layers having threshold voltages different from each other, Each of the plurality of memory material layers includes a chalcogenide-based material, has an on-the-fly threshold switching (OTS) characteristic, and is configured to have a threshold voltage that varies with the polarity and magnitude of an applied voltage. 11 . The memory device of claim 10 , wherein each of the plurality of memory material layers comprises a chalcogenide element including at least one of Se or Te and at least one of Ge, As, or Sb.

12. The memory device of claim 11, wherein at least one of the plurality of memory material layers further comprises at least one of In, Al, C, B, Sr, Ga, O, N, Si, Ca, P, or S. 13 . The memory device according to claim 10 , wherein the plurality of memory material layers have different threshold voltages from each other according to compositions thereof or the compositions and thicknesses. 14 . The memory device of claim 10 , wherein the plurality of memory material layers are perpendicular to the first electrode and the second electrode and are electrically connected in parallel to each other. 15 . The memory device of claim 14 , wherein when the number of the plurality of memory material layers is n, the memory cell is configured to implement 2*(n+1) level states. 16 . The memory device of claim 10 , wherein each of the plurality of memory material layers is configured to use write voltage pulses of different polarities to achieve a low threshold voltage state and a high threshold voltage state.

17. The memory device of claim 10, further comprising: a plurality of bit lines extending in a first direction, and a plurality of word lines extending in a second direction intersecting the first direction, The plurality of memory cells are respectively arranged at points where the plurality of bit lines and the plurality of word lines intersect each other.

18. The memory device of claim 10, further comprising: a plurality of word planes extending along a plane including the first direction and the second direction and spaced apart from each other in a third direction, and a vertical bit line, the vertical bit line passing through the plurality of word planes and extending in the third direction, The memory layer is between the vertical bit lines and each word plane. The memory device of claim 18 , wherein the plurality of memory material layers are stacked in the third direction.

20. An electronic device comprising the memory device according to claim 10.

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