Preparation method of deep trench capacitor and deep trench capacitor

Abstract

The invention relates to the technical field of semiconductor devices of integrated circuits, in particular to a preparation method of a deep trench capacitor and the deep trench capacitor. The preparation method comprises the following steps: etching a substrate to obtain a deep groove substrate; performing heat treatment on the deep groove substrate to obtain the deep groove substrate; performing primary atomic layer deposition treatment on the deep trench substrate by using a nitrogen source and a titanium source in an inert gas atmosphere to obtain a first deep trench substrate; performing secondary atomic layer deposition treatment on the first deep trench substrate by using an oxygen source and an aluminum source in an inert gas atmosphere to obtain a second deep trench substrate; and performing primary atomic layer deposition treatment on the second deep trench substrate by using a nitrogen source and a titanium source in an inert gas atmosphere to obtain the deep trench capacitor. According to the preparation method, the deep groove capacitor which is uniform in thickness distribution and comprises the lower electrode layer, the dielectric layer and the upper electrode layer can be prepared, the coverage degree of each layered structure is relatively high, and the deep groove capacitor with the yield of 98% or above can be obtained.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices of integrated circuits, and in particular to a method for preparing a deep trench capacitor and a deep trench capacitor. Background Art

[0002] Deep Trench Capacitor (DTC) has a higher capacitance density than traditional capacitors, especially in applications with certain height and volume restrictions. DTC still has very high stability and extremely low leakage current under higher bias voltage. Based on these characteristics, DTC plays a vital role in some industrial fields. With the widespread application of DTC in fields such as RF filtering and integrated circuit decoupling, how to improve the capacitance density of DTC has become a research hotspot at this stage. DTC devices are generally composed of metal electrodes and dielectric layers with high dielectric constant (k). DTC devices need to alternately deposit metal electrode layers and high-k dielectric layers in their trenches multiple times through physical vapor deposition (PVD) process, and finally form parallel capacitors through metal interconnection, thereby further improving the capacitance density.

[0003] However, due to the poor step coverage capability of the PVD process, the metal electrode layer and the dielectric layer deposited by the PVD process are not smooth and uniform, thus affecting the yield of the product. Summary of the invention

[0004] The present application provides a method for preparing a deep trench capacitor and a deep trench capacitor to solve the following technical problem: how to improve the flatness of a metal electrode layer and a dielectric layer of a deep trench capacitor.

[0005] In a first aspect, an embodiment of the present application provides a method for preparing a deep trench capacitor, the method comprising:

[0006] The substrate is etched to obtain a deep groove substrate;

[0007] The deep groove substrate is subjected to heat treatment to obtain a deep groove substrate containing a protective layer;

[0008] Using a nitrogen source and a titanium source in an inert gas atmosphere, the deep trench substrate containing the protective layer is subjected to a first atomic layer deposition process to obtain a first deep trench substrate containing a lower electrode layer;

[0009] Using an oxygen source and an aluminum source in an inert gas atmosphere, subjecting the first deep trench substrate to a second atomic layer deposition process to obtain a second deep trench substrate comprising a dielectric layer and a lower electrode layer;

[0010] The second deep trench substrate is subjected to the first atomic layer deposition process using the nitrogen source and the titanium source in an inert gas atmosphere to obtain a deep trench capacitor including an upper electrode layer, a dielectric layer and a lower electrode layer.

[0011] Optionally, the temperature of the first atomic layer deposition process is 445°C to 455°C.

[0012] Optionally, the temperature of the second atomic layer deposition process is 245°C to 255°C.

[0013] Optionally, the introduction time t1 of the titanium source and the introduction time t2 of the nitrogen source satisfy the relationship: t1:t2≥0.1:10.

[0014] Optionally, the titanium source includes titanium tetrachloride and / or titanium tetraisopropoxide; and / or

[0015] The nitrogen source includes ammonia and / or nitrogen.

[0016] Optionally, the introduction time t3 of the aluminum source and the introduction time t4 of the oxygen source satisfy the relationship: t3:t4≥0.08:0.03.

[0017] Optionally, the aluminum source is trimethylaluminum; and / or

[0018] The oxygen source includes at least one of: water, ozone and oxygen.

[0019] Optionally, the inert gas atmosphere includes a nitrogen atmosphere and a group zero element gas atmosphere.

[0020] In a second aspect, the present application provides a deep trench capacitor, which is prepared by the preparation method described in the first aspect, and includes a substrate and a composite functional layer covering the surface of the substrate, the composite functional layer includes a protective layer, a lower electrode layer, a dielectric layer and an upper electrode layer, the protective layer is arranged on the surface of the substrate, the lower electrode layer is arranged on the surface of the protective layer, the dielectric layer is arranged on the surface of the lower electrode layer, and the upper electrode layer is arranged on the surface of the dielectric layer.

[0021] Optionally, the thickness of the protective layer is 250nm-280nm, the thickness of the upper electrode layer is 5nm-10nm, the thickness of the dielectric layer is 35nm-45nm, and the thickness of the lower electrode layer is 5nm-10nm.

[0022] The above technical solution provided by the embodiment of the present application has the following advantages compared with the prior art:

[0023] A method for preparing a deep trench capacitor provided in an embodiment of the present application, the method firstly performs a heat treatment on the surface of a deep trench substrate to form a uniform protective layer by self-heating growth on the surface of the deep trench substrate, and then forms a lower electrode layer, a dielectric layer and an upper electrode layer on the surface of the formed protective layer by a first atomic layer deposition treatment and a second atomic layer deposition treatment respectively. Based on the self-limiting surface reaction characteristics of the atomic layer deposition treatment, the surface of the protective layer can form a uniformly distributed single-molecule layer of the lower electrode layer, the dielectric layer and the upper electrode layer in sequence. In addition, based on the high diffusion efficiency characteristics of the atomic layer deposition treatment, for a deep trench capacitor with multiple different trench depths, multiple atomic layer deposition treatments can also form a lower electrode layer, a dielectric layer and an upper electrode layer with uniform thickness in the trench of the deep trench capacitor, thereby improving the flatness of the metal electrode layer and the dielectric layer of the trench capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0025] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0026] Figure 1 A schematic diagram of a process for preparing a deep trench capacitor provided in an embodiment of the present application;

[0027] Figure 2 A schematic diagram of the structure of a deep trench capacitor provided in an embodiment of the present application;

[0028] Among them, 1 is substrate, 2 is lower electrode layer, 3 is dielectric layer, 4 is upper electrode layer, and 5 is protective layer. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0030] Various embodiments of the present application may be presented in the form of a range; it should be understood that the description in the form of a range is only for convenience and brevity and should not be understood as a rigid limitation on the scope of the present application; therefore, it should be considered that the range description has specifically disclosed all possible sub-ranges and single numerical values ​​within the range; for example, it should be considered that the range description from 1 to 6 has specifically disclosed sub-ranges, such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., as well as single numbers within the range, such as 1, 2, 3, 4, 5 and 6, which applies regardless of the range; in addition, whenever a numerical range is indicated in this document, it is meant to include any cited number (fractional or integer) within the indicated range.

[0031] In this document, the terms including "including" and "including" mean "including but not limited to". Relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. "And / or" describes the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone; where A and B can be singular or plural. "At least one" means one or more, and "plurality" means two or more; "at least one", "at least one of the following" or similar expressions, refers to any combination of these items, including any combination of single or plural items; for example, "at least one of a, b, or c", or "at least one of a, b, and c" can all mean: a, b, c, ab (i.e., a and b), ac, bc, or abc, where a, b, and c can be single or multiple. "Parts" such as parts by weight and parts by mass indicate the proportional relationship between the components. In the proportional relationship involved in this article, the parameters that need to be described by proportion should be understood as the first term of the proportional formula in the order of description, and the proportional numbers should be understood as the second term of the proportional formula. For example, if the mass ratio of substance A, substance B and substance C is 1:2:3, then substance A, substance B and substance C should correspond to the proportional numbers in the proportional formula in the order of description, that is, the mass of substance A: the mass of substance B: the mass of substance C = 1:2:3.

[0032] Unless otherwise specified, various raw materials, reagents, instruments and equipment used in this article can be purchased from the market or prepared by existing methods.

[0033] Figure 1 A schematic diagram of a process for preparing a deep trench capacitor provided in an embodiment of the present application is exemplarily shown;

[0034] like Figure 1 As shown, an embodiment of the present application provides a method for preparing a deep trench capacitor, the method comprising:

[0035] S1. Etching the substrate to obtain a deep trench substrate;

[0036] S2. The deep groove substrate is heat treated to obtain a deep groove substrate containing a protective layer;

[0037] S3. Performing a first atomic layer deposition process on the deep trench substrate containing the protective layer using a nitrogen source and a titanium source in an inert gas atmosphere to obtain a first deep trench substrate containing a lower electrode layer;

[0038] S4. Using an oxygen source and an aluminum source in an inert gas atmosphere, the first deep trench substrate is subjected to a second atomic layer deposition process to obtain a second deep trench substrate containing a dielectric layer and a lower electrode layer;

[0039] S5. Using the nitrogen source and the titanium source in an inert gas atmosphere, the second deep trench substrate is subjected to the first atomic layer deposition process to obtain a deep trench capacitor comprising an upper electrode layer, a dielectric layer and a lower electrode layer.

[0040] It should be noted that the temperature of the heat treatment is 900℃~1200℃, which promotes the formation of a silicon oxide protective layer of sufficient thickness on the surface of the deep trench substrate; the atmosphere used for the heat treatment can be oxygen or water vapor; according to the oxidation atmosphere of the heat treatment, the oxidation process of the heat treatment can be divided into dry oxidation or wet oxidation. Dry oxidation: using pure oxygen (O2) as the atmosphere, suitable for the growth of thinner oxide layers, usually with a slower growth rate, suitable for high-quality oxide layers. Wet oxidation: using a mixed gas of oxygen and water vapor (H2O), suitable for the rapid growth of thicker oxide layers, while wet oxidation can achieve a higher growth rate at a lower temperature, suitable for thicker silicon dioxide layers.

[0041] It should be noted that the etching can be performed according to the deep trench requirement of the deep trench capacitor.

[0042] It should be noted that before using the substrate, the substrate needs to be thoroughly cleaned to remove surface impurities and organic matter to ensure the quality of the oxide layer.

[0043] It should be noted that both the first atomic layer deposition process and the second atomic layer deposition process can achieve highly uniform and conformal thin film coverage on complex three-dimensional structures, and this three-dimensional conformality means that the upper electrode layer, the dielectric layer and the lower electrode layer are uniformly deposited inside and outside the high aspect ratio structure (such as deep trenches or through holes), and the thickness remains consistent along all directions of the structure.

[0044] It should be noted that the first atomic layer deposition process and the second atomic layer deposition process have the following advantages in the process of preparing the layered structure of the deep trench capacitor:

[0045] 1. Self-limiting reaction: The atomic layer deposition process mainly involves the alternating introduction of precursors and co-reactants, and the occurrence of self-limiting surface reactions on the surface of the protective layer, and each self-limiting surface reaction will form a monolayer of deposited film. This self-limiting feature ensures that the target film can grow evenly on the surface of the complex trench structure of the deep trench capacitor, avoiding the uneven thickness problem that may occur in traditional chemical vapor deposition or physical vapor deposition processes.

[0046] 2. Effective diffusion of precursors: During the atomic layer deposition process, the precursor molecules can effectively diffuse and penetrate deep into the high aspect ratio trench structure of the deep trench capacitor; based on the characteristics of the atomic layer deposition process, as long as sufficient precursor pulse time is provided, the precursor can be evenly distributed in the deep trench structure or hole structure of the deep trench capacitor to ensure that the deposition reaction can occur on the entire surface of the deep trench capacitor. Through the above mechanism, the atomic layer deposition process can achieve high-quality thin film deposition on the complex three-dimensional structure of the deep trench capacitor, so that the preparation method can be widely used in semiconductor device manufacturing, nanotechnology and materials science.

[0047] It should be noted that the present application embodiment provides a method for preparing a deep trench capacitor, the principle of which is mainly based on the characteristics of atomic layer deposition (ALD) technology. The following is a detailed explanation:

[0048] (1) Heat treatment to form a protective layer:

[0049] First, the surface of the deep trench substrate is heat treated to form a uniform protective layer by self-heating growth on the surface of the deep trench substrate. This step may help prevent impurity contamination during subsequent deposition and provide a good substrate for the deposition of electrode layers and dielectric layers.

[0050] (2) Atomic layer deposition process:

[0051] Subsequently, an atomic layer deposition process is performed on the surface of the formed protective layer. Atomic layer deposition is a highly accurate self-limiting surface reaction technology that can sequentially form uniformly distributed monomolecular layers on the substrate surface. Therefore, the lower electrode layer is formed by the first atomic layer deposition process; then, the dielectric layer is formed by the second atomic layer deposition process; and finally, the upper electrode layer is formed by another atomic layer deposition process. In addition, the self-limiting surface reaction characteristics of atomic layer deposition ensure that each layer is uniformly distributed and the thickness is precisely controllable. This is crucial for forming high-quality electrode and dielectric layers in deep trenches.

[0052] (3) Improve flatness:

[0053] Based on the high diffusion efficiency of the atomic layer deposition process, even in a deep trench capacitor with multiple different trench depths, multiple atomic layer deposition processes can form a lower electrode layer, a dielectric layer, and an upper electrode layer with uniform thickness in the trench of the deep trench capacitor. This not only improves the flatness of the metal electrode layer and the dielectric layer of the trench capacitor, but also helps to improve the overall performance of the capacitor, such as energy storage capacity and discharge efficiency.

[0054] In summary, the present application provides a method for preparing a deep trench capacitor. The deep trench capacitor obtained by the preparation method has the advantage of high capacitance density, which makes it have broad application prospects in many applications, especially in semiconductor devices requiring high capacitance density. By using atomic layer deposition technology to prepare deep trench capacitors, their performance can be further improved and meet the needs of future semiconductor devices for higher density and smaller size.

[0055] In some optional embodiments, the temperature of the first atomic layer deposition process is 445° C. to 455° C.;

[0056] In these embodiments, the temperature of the first atomic layer deposition treatment can be 445°C to 455°C, which enables the nitrogen source and titanium source as precursors and co-reactants to form a titanium nitride upper electrode layer or a titanium nitride lower electrode layer of sufficient thickness and uniform distribution through atomic layer deposition treatment, thereby improving the flatness of the metal electrode layer of the trench capacitor to obtain a metal electrode layer with good resistivity, uniformity, deposition rate and step coverage.

[0057] The temperature of the first atomic layer deposition process may be 445°C, 446°C, 447°C, 448°C, 449°C, 450°C, 451°C, 452°C, 453°C, 454°C, or 455°C.

[0058] In some optional embodiments, the temperature of the second atomic layer deposition process is 245° C. to 255° C.;

[0059] In these embodiments, the temperature of the second atomic layer deposition process can be 245°C to 255°C, which enables the oxygen source and aluminum source as precursors and co-reactants to form a sufficiently thick and evenly distributed aluminum oxide dielectric layer through atomic layer deposition, thereby improving the flatness of the dielectric layer of the trench capacitor to obtain a dielectric layer with good resistivity, uniformity, deposition rate and step coverage.

[0060] The temperature of the second atomic layer deposition process may be 245°C, 246°C, 247°C, 248°C, 249°C, 250°C, 251°C, 252°C, 253°C, 254°C or 255°C.

[0061] In some optional embodiments, the introduction time t1 of the titanium source and the introduction time t2 of the nitrogen source satisfy the relationship: t1:t2≥0.1:10;

[0062] In these embodiments, the titanium source introduction time t1 and the nitrogen source introduction time t2 can satisfy the relationship: t1:t2≥0.1:10, so that the titanium source and the nitrogen source have sufficient introduction time to form a titanium nitride upper electrode layer or a titanium nitride lower electrode layer of sufficient thickness and uniform distribution on the surface of the protective layer, thereby improving the flatness of the metal electrode layer of the trench capacitor.

[0063] In some optional embodiments, the titanium source includes titanium tetrachloride and / or titanium tetraisopropoxide; and / or

[0064] The nitrogen source includes ammonia and / or nitrogen;

[0065] In these embodiments, the titanium source may include titanium tetrachloride and / or titanium tetraisopropoxide, and the nitrogen source may include ammonia and / or nitrogen, so as to promote sufficient reaction between the titanium source and the nitrogen source, so that a titanium nitride upper electrode layer or a titanium nitride lower electrode layer of sufficient thickness and uniform distribution is formed on the surface of the protective layer, thereby improving the flatness of the metal electrode layer of the trench capacitor.

[0066] In some optional embodiments, the introduction time t3 of the aluminum source and the introduction time t4 of the oxygen source satisfy the relationship: t3:t4≥0.08:0.03;

[0067] In these embodiments, the aluminum source introduction time t3 and the oxygen source introduction time t4 can satisfy the relationship: t3:t4≥0.08:0.03, which ensures that the aluminum source and the oxygen source have sufficient introduction time to form an aluminum oxide dielectric layer of sufficient thickness and uniform distribution on the surface of the protective layer, thereby improving the flatness of the dielectric layer of the trench capacitor.

[0068] In some optional embodiments, the aluminum source is trimethylaluminum; and / or

[0069] The oxygen source comprises at least one of: water, ozone and oxygen;

[0070] In these embodiments, the aluminum source may be trimethylaluminum, and the oxygen source may include: at least one of water, ozone and oxygen, to promote the aluminum source and the oxygen source to react fully, so that a sufficiently thick and evenly distributed aluminum oxide dielectric layer is formed on the surface of the protective layer, thereby improving the flatness of the dielectric layer of the trench capacitor.

[0071] In some optional embodiments, the inert gas atmosphere includes a nitrogen atmosphere and a zero group element gas atmosphere;

[0072] In these embodiments, the inert gas atmosphere may include a nitrogen atmosphere and a zero group element gas atmosphere, which promotes the first atomic layer deposition process and the second atomic layer deposition process to react fully, so that a titanium nitride upper electrode layer, an aluminum oxide dielectric layer, and a titanium nitride lower electrode layer with sufficient thickness and uniform distribution are formed on the surface of the protective layer.

[0073] Figure 2 A schematic structural diagram of a deep trench capacitor provided in an embodiment of the present application is exemplarily shown;

[0074] Based on a general inventive concept, such as Figure 2 As shown, an embodiment of the present application provides a deep trench capacitor, wherein the deep trench capacitor is prepared by the preparation method, and the deep trench capacitor comprises a substrate 1, and a composite functional layer covering the surface of the substrate 1,

[0075] The composite functional layer includes a protective layer 5, a lower electrode layer 2, a dielectric layer 3 and an upper electrode layer 4, wherein the protective layer 5 is arranged on the surface of the substrate 1, the lower electrode layer 2 is arranged on the surface of the protective layer 5, the dielectric layer 3 is arranged on the surface of the lower electrode layer 2, and the upper electrode layer 4 is arranged on the surface of the dielectric layer 3.

[0076] The deep trench capacitor is realized based on the above-mentioned preparation method. The specific steps of the preparation method can refer to the above-mentioned embodiment. Since the deep trench capacitor adopts part or all of the technical solutions of the above-mentioned embodiment, it has at least all the beneficial effects brought by the technical solutions of the above-mentioned embodiment, which will not be described one by one here.

[0077] It should be noted that, based on the superiority of the atomic layer deposition process, the deep trench capacitor can obtain a deep trench capacitor with a trench depth-to-width ratio greater than 20.

[0078] In some optional embodiments, the thickness of the protective layer 5 is 250nm-280nm, the thickness of the upper electrode layer 4 is 5nm-10nm, the thickness of the dielectric layer 3 is 35nm-45nm, and the thickness of the lower electrode layer 2 is 5nm-10nm;

[0079] In these embodiments, the thickness of the protective layer 5 can be 250nm~280nm, the thickness of the upper electrode layer 4 can be 5nm~10nm, and the thickness of the lower electrode layer 2 can be 5nm~10nm, so that the deep trench capacitor has an upper electrode layer 4 and a lower electrode layer 2 of sufficient thickness, so that the deep trench capacitor has good electrical properties; in addition, the thickness of the dielectric layer 3 can be 35nm~45nm, so that the protective layer 5 has sufficient thickness, which can play a good role in isolating current leakage, thereby ensuring the functionality of the deep trench capacitor.

[0080] The thickness of the protective layer 5 can be 250 nm, 255 nm, 260 nm, 265 nm, 270 nm, 275 nm, 280 nm, 285 nm or 290 nm.

[0081] The thickness of the upper electrode layer 4 may be 5 nm, 6 nm, 7 nm, 8 nm, 9 nm or 10 nm.

[0082] The thickness of the lower electrode layer 2 can be 5 nm, 6 nm, 7 nm, 8 nm, 9 nm or 10 nm.

[0083] The thickness of the dielectric layer 3 may be 35 nm, 36 nm, 37 nm, 38 nm, 39 nm, 40 nm, 41 nm, 42 nm, 43 nm, 44 nm or 45 nm.

[0084] The present application is further described below in conjunction with specific examples. The experimental methods in the following examples where specific conditions are not specified are usually measured in accordance with national standards / industry standards; if there are no corresponding national standards / industry standards, they are measured in accordance with common international standards, conventional conditions or conditions recommended by the manufacturer.

[0085] Example 1

[0086] like Figure 1 As shown, a method for preparing a deep trench capacitor comprises:

[0087] S1. Etching the silicon wafer substrate to obtain a deep trench substrate;

[0088] S2. The deep groove substrate is heat treated at 450° C. for 3 h to obtain a deep groove substrate containing a protective layer;

[0089] S3. Performing a first atomic layer deposition process on the deep groove substrate containing the protective layer using a nitrogen source and a titanium source in an inert gas atmosphere to obtain a first deep groove substrate containing a lower electrode layer; the specific process is as follows: introducing titanium tetrachloride for 0.1s at 450°C in an inert gas atmosphere, reacting for 5s and then purging for 10s, and then using an inert gas to clear the excess titanium tetrachloride in the reaction chamber; then introducing nitrogen for 10s and then purging for 10s to deposit the lower electrode layer on the surface of the protective layer;

[0090] S4. The first deep trench substrate is subjected to a second atomic layer deposition process using an oxygen source and an aluminum source in an inert gas atmosphere to obtain a second deep trench substrate containing a dielectric layer and a lower electrode layer; the specific process is as follows: trimethylaluminum is introduced for 0.08s at 250°C in an inert gas atmosphere, and after reacting for 2s, it is purged for 10s, and then water is introduced for 0.03s, and then purged for 10s to form a dielectric layer on the surface of the lower electrode layer.

[0091] S5. Perform a first atomic layer deposition process on the second deep trench substrate using a nitrogen source and a titanium source in an inert gas atmosphere to obtain a deep trench capacitor comprising an upper electrode layer, a dielectric layer and a lower electrode layer.

[0092] The temperature of the first ALD process was 450°C.

[0093] The temperature of the second ALD process was 250°C.

[0094] The introduction time t1 of the titanium source and the introduction time t2 of the nitrogen source satisfy the relationship: t1:t2=0.1:10.

[0095] The titanium source is titanium tetrachloride; the nitrogen source is nitrogen gas.

[0096] The introduction time t3 of the aluminum source and the introduction time t4 of the oxygen source satisfy the relationship: t3:t4=0.08:0.03.

[0097] The aluminum source was trimethylaluminum;

[0098] The oxygen source is water.

[0099] The inert gas atmosphere includes a nitrogen atmosphere and a group zero element gas atmosphere.

[0100] like Figure 2 As shown, a deep trench capacitor is prepared by a preparation method, the deep trench capacitor includes a silicon wafer substrate 1, and a composite functional layer covering the surface of the substrate 1, the composite functional layer includes a lower electrode layer 2, a dielectric layer 3 and an upper electrode layer 4, the lower electrode layer 2 is arranged on the surface of the substrate 1, the dielectric layer 3 is arranged on the surface of the lower electrode layer 2, and the upper electrode layer 4 is arranged on the surface of the dielectric layer 3.

[0101] The thickness of the protective layer 5 is 260 nm, the thickness of the upper electrode layer 4 is 8 nm, the thickness of the dielectric layer 3 is 40 nm, and the thickness of the lower electrode layer 2 is 8 nm.

[0102] Example 2

[0103] Based on the contents disclosed in Example 1, the following modifications are further made:

[0104] The temperature of the first ALD process was 445°C.

[0105] The temperature of the second ALD process was 245°C.

[0106] Example 3

[0107] Based on the contents disclosed in Example 1, the following modifications are further made:

[0108] The temperature of the first ALD process was 455°C.

[0109] The temperature of the second ALD process was 255°C.

[0110] Comparative Example 1

[0111] Based on the contents disclosed in Example 1, the following modifications are further made:

[0112] The lower electrode layer 2, the dielectric layer 3 and the upper electrode layer 4 are formed on the surface of the protective layer by physical vapor deposition.

[0113] Comparative Example 2

[0114] Based on the contents disclosed in Example 1, the following modifications are further made:

[0115] A lower electrode layer 2, a dielectric layer 3 and an upper electrode layer 4 are formed on the surface of the protective layer by chemical vapor deposition.

[0116] Related experiments and effect data:

[0117] Since the trench structure of the deep trench capacitor is relatively complex, the thickness at each stage of the preparation process will fluctuate to varying degrees, and these fluctuations will affect the final yield of the deep trench capacitor. Generally, the coverage and thickness uniformity of the lower electrode layer 2, the dielectric layer 3 and the upper electrode layer 4 determine the yield of the deep trench capacitor. The yields of the deep trench capacitors prepared in each embodiment and the comparative example are statistically analyzed, and the results are shown in Table 1.

[0118] Table 1 The yield rate of deep trench capacitors in various embodiments and comparative examples

[0119]

[0120]

[0121] As can be seen from Table 1, the embodiment of the present application provides a method for preparing a deep trench capacitor, which can prepare a deep trench capacitor including a lower electrode layer 2, a dielectric layer 3 and an upper electrode layer 4 with uniform thickness distribution, and the coverage degree of each layered structure is high, thereby obtaining a deep trench capacitor with a yield of 98% or more.

[0122] In summary, the present application provides a method for preparing a deep trench capacitor, which is processed by multiple atomic layer deposition. Compared with the traditional physical vapor deposition and chemical vapor deposition processes, the deep trench capacitor obtained by atomic layer deposition has a higher depth-to-width ratio, and a larger capacitance density can be obtained on a limited silicon wafer area. In addition, the atomic layer deposition process has excellent three-dimensional conformality and step coverage, and the thickness of the deposited different layered structures can be simply controlled by adjusting the number of cycles. Therefore, compared with the process using physical vapor deposition and chemical vapor deposition, the preparation method can more accurately regulate the thickness and structure of the electrode layer and the dielectric layer 3, avoiding the problem of poor quality of the layered structure at the bottom and sidewall positions of the trench structure of the deep trench capacitor, so that the deep trench capacitor has a higher yield rate.

[0123] The above description is only a specific implementation of the present application, so that those skilled in the art can understand or implement the present application. It will be apparent to those skilled in the art that various modifications to these embodiments are possible, and the general principles defined in the present application can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown in the present application, but will conform to the widest range consistent with the principles and novel features applied for by the present application.

Claims

1. A method for preparing a deep trench capacitor, the method comprising: The substrate is etched to obtain a deep groove substrate; The deep groove substrate is subjected to heat treatment to obtain a deep groove substrate containing a protective layer; Using a nitrogen source and a titanium source in an inert gas atmosphere, the deep trench substrate containing the protective layer is subjected to a first atomic layer deposition process to obtain a first deep trench substrate containing a lower electrode layer; Using an oxygen source and an aluminum source in an inert gas atmosphere, subjecting the first deep trench substrate to a second atomic layer deposition process to obtain a second deep trench substrate comprising a dielectric layer and a lower electrode layer; The second deep trench substrate is subjected to the first atomic layer deposition process using the nitrogen source and the titanium source in an inert gas atmosphere to obtain a deep trench capacitor including an upper electrode layer, a dielectric layer and a lower electrode layer. 2 . The preparation method according to claim 1 , wherein the temperature of the first atomic layer deposition treatment is 445° C. to 455° C. 3 . The preparation method according to claim 1 , wherein the temperature of the second atomic layer deposition treatment is 245° C. to 255° C.

4. The preparation method according to claim 1, wherein the introduction time t1 of the titanium source and the introduction time t2 of the nitrogen source satisfy the relationship: t1:t2≥0.1:

10.

5. The preparation method according to claim 1 or 4, wherein the titanium source comprises titanium tetrachloride and / or titanium tetraisopropoxide; and / or The nitrogen source includes ammonia and / or nitrogen.

6. According to the preparation method of claim 1, the introduction time t3 of the aluminum source and the introduction time t4 of the oxygen source satisfy the relationship: t3:t4≥0.08:0.

03.

7. The preparation method according to claim 1 or 6, wherein the aluminum source is trimethylaluminum; and / or The oxygen source includes at least one of: water, ozone and oxygen. 8 . The preparation method according to claim 1 , wherein the inert gas atmosphere comprises a nitrogen atmosphere and a zero group element gas atmosphere.

9. A deep trench capacitor, wherein the deep trench capacitor is prepared by the preparation method according to any one of claims 1 to 8, and the deep trench capacitor comprises a substrate (1), and a composite functional layer covering the surface of the substrate (1), wherein the composite functional layer comprises a protective layer (5), a lower electrode layer (2), a dielectric layer (3) and an upper electrode layer (4), wherein the protective layer (5) is arranged on the surface of the substrate (1), the lower electrode layer (2) is arranged on the surface of the protective layer (5), the dielectric layer (3) is arranged on the surface of the lower electrode layer (2), and the upper electrode layer (4) is arranged on the surface of the dielectric layer (3).

10. The deep trench capacitor according to claim 9, wherein the thickness of the protective layer (5) is 250nm-280nm, the thickness of the upper electrode layer (4) is 5nm-10nm, the thickness of the dielectric layer (3) is 35nm-45nm, and the thickness of the lower electrode layer (2) is 5nm-10nm.

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