Execution circuit for floating point exponentiation

Abstract

Techniques related to dedicated power function circuitry for floating point power instructions are disclosed. In some embodiments, the execution circuitry is configured to execute a floating point power instruction to evaluate the power function xy as # imgabs0 #, a 2-bottomed logarithm circuit is configured to evaluate a 2-bottomed logarithm (e.g., log2x) of a first input by determining coefficients of a polynomial function and evaluating the polynomial function using the determined coefficients and the first input. In some embodiments, a multiplication circuit multiplies the 2-bottomed logarithmic result by a second input to generate a multiplication result. In some embodiments, a 2-bottomed power function circuit is configured to evaluate a 2-bottomed power function for the multiplication result. Compared to conventional techniques, the disclosed techniques may advantageously improve the performance of floating point power function operations and reduce its power consumption with reasonable area and accuracy.

Description

Background Art Technical Field

[0001] The present disclosure relates generally to computer processors, and more particularly to floating point circuits.

[0002] Related technical description

[0003] Complex functions are often performed in computer processors for a variety of applications, such as numerical calculations, graphics processing, machine learning algorithms, display processing, etc. In general, computer processors use specialized circuits to perform many common operations, such as multiplication and addition. However, some more complex operations (such as, for example, the power function x) are y , exponential functions, and logarithmic functions) are typically implemented using software libraries with multiple instructions. Implementing such operations in hardware with an acceptable circuit area and desired accuracy can be challenging. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a block diagram illustrating example execution circuitry according to some embodiments.

[0005] Figure 2 is a block diagram illustrating an example pipeline according to some embodiments.

[0006] Figure 3 is a block diagram illustrating detailed example execution circuitry according to some embodiments.

[0007] Figure 4 is a block diagram illustrating an example base 2 logarithm circuit according to some embodiments.

[0008] Figure 5 is a block diagram illustrating a detailed example polynomial approximation circuit according to some embodiments.

[0009] Figure 6 is a flowchart illustrating an example method according to some embodiments.

[0010] Figure 7 is a block diagram illustrating an example computing device according to some embodiments.

[0011] Figure 8 is a diagram illustrating an example application of the disclosed systems and devices according to some embodiments.

[0012] Fig. 9 is a block diagram illustrating an example computer-readable medium storing circuit design information according to some embodiments. DETAILED DESCRIPTION

[0013] Common computational functions such as multiplication and addition typically utilize dedicated circuits to generate floating-point results. However, for more complex functions such as power functions, conventional techniques utilize software libraries, for example due to accuracy and area constraints. In general, the disclosed dedicated power function circuits can significantly improve the performance of floating-point power function operations and reduce their power consumption at a reasonable area and accuracy for a range of input values ​​relative to conventional techniques.

[0014] In some embodiments, the execution circuitry is configured to execute a single floating point exponentiation instruction to perform a power function Executing a single instruction of a power function relative to executing multiple instructions of a software library may have various performance benefits. In addition, the disclosed circuit may implement various techniques to maintain accuracy targets.

[0015] For example, in some embodiments, the execution hardware approximates the power function in three steps, including performing a base 2 logarithmic approximation on a first input (e.g., log2x), multiplying the base 2 logarithmic approximation result by a second input (e.g., y×log2x), and performing a base 2 power function approximation based on the multiplication result (e.g., ).

[0016] In some embodiments discussed in detail below, as part of the base-2 logarithm approximation, execution circuitry determines coefficients of a polynomial function and evaluates the polynomial function using the determined coefficients and the x input to generate a result. This operation can use head-and-tail arithmetic to improve accuracy relative to using the original input format (e.g., 32-bit floating point format) without the circuit area associated with operations in a higher precision format (e.g., associated with multiplication in a 64-bit floating point format). In general, the use of head-and-tail arithmetic can reduce rounding errors, facilitating the tradeoff between accuracy and area considerations described above. In addition, the base-2 logarithm circuit can be configured using overlapping intervals when determining coefficients (e.g., using a lookup table), which can reduce errors (which are typically largest near the edges of a given interval).

[0017] The multiplication circuit may also perform the multiplication operation using head-tail arithmetic. In some embodiments discussed in detail below, the execution circuit generates a power function result by approximating a base-2 power function based on the multiplication result (and the base-2 power function may also be approximated using a polynomial).

[0018] Note that in addition to the performance benefits listed above, dedicated power function circuits can advantageously provide intermediate results utilized by other functions (e.g., base 2 logarithm results or base 2 power results used as activation functions for machine learning applications) with little increase in circuit area. This can reduce power consumption and also improve performance of these functions.

[0019] Example Implementation Circuit

[0020] Figure 1 is a block diagram illustrating an example execution circuit according to some embodiments. In the illustrated embodiment, execution circuit 100 includes base 2 logarithm circuit 110 , multiplication circuit 120 , and base 2 power function circuit 130 .

[0021] In some embodiments, execution circuit 100 computes a floating point power function by generating an approximation of a base 2 logarithm for a first input, multiplying a result of the base 2 logarithm approximation by a second input, and generating an approximation of a base 2 power function for the result of the multiplication.

[0022] In the illustrated embodiment, the base 2 logarithm circuit 110 is configured to evaluate a base 2 logarithm, e.g., log2x, based on an input operand x. In some embodiments, the base 2 logarithm circuit 110 may perform various operations, as described below with respect to Figure 4 and Figure 5 The following operations are discussed in detail: shifting of arguments, floating point conversions, polynomial approximation, head and tail arithmetic addition, etc.

[0023] In some embodiments, the base 2 logarithm circuit evaluates the base 2 logarithm of the input operand x by determining coefficients of a polynomial function based on the input operand x, and evaluating the polynomial function based on the determined coefficients and the input operand x to determine a base 2 logarithm result. Figure 3 In some embodiments discussed in detail, a base-2 logarithm result evaluated by a base-2 logarithm circuit may include a head component and a tail component of head-tail arithmetic.

[0024] In some embodiments, head-tail arithmetic is used to generate a higher precision result so that rounding errors do not become unacceptable at a later stage (e.g., in a multiplication operation performed by multiplication circuit 120). As will be appreciated by those skilled in the art, head-tail arithmetic uses two lower precision components to represent a higher precision number, and operates on the two components separately. This approach can advantageously maintain accuracy without increasing the width of certain circuit elements (e.g., multipliers, adders, etc.), which may more significantly affect area considerations, power consumption, etc. Note that in some embodiments, head-tail operations can utilize more than two portions of a given operand, e.g., where the middle portion is used for a total of three portions, a total of four portions, etc., with similar independent operations and then converted to a more conventional format.

[0025] In some embodiments, the input operand x is provided to the base 2 logarithm circuit 110 in a first floating point format. As an example, the input operand x can be represented using the IEEE standard single precision floating point format, which uses 32 bits to represent floating point numbers. In some embodiments, the header component and the tail component use less than or equal to the number of bits of the input operand x.

[0026] In the illustrated embodiment, the multiplication circuit 120 is configured to perform a multiplication operation between the base 2 logarithm result generated by the base 2 logarithm circuit 110 and the input operand y to generate a multiplication result y×log2x. Figure 3 In some embodiments discussed in detail, the multiplication operation may be a head and tail operation, and the multiplication result may include a multiplication head result and a multiplication tail result.

[0027] In the illustrated embodiment, the power function circuit 130 with base 2 is configured to evaluate the representation power of the multiplication result of two to generate the result of the floating point instruction in a first floating point format. For example, the representation of the multiplication result can be an output that converts the head-to-tail multiplication result into a non-head-to-tail format. In these embodiments, the power function circuit 130 with base 2 is not configured to perform head-to-tail arithmetic.

[0028] Example Pipeline

[0029] Figure 2 2 is a block diagram illustrating an example pipeline according to some embodiments. In the illustrated embodiment, the example pipeline illustrates multiple elements, including a fetch stage 210, a decode stage 220, a dispatch stage 230, and an execution circuit 100. Although the illustrated stages are included for purposes of illustration, in other embodiments, a given pipeline may include various other stages or may omit the illustrated stages. Furthermore, one or more of the illustrated elements may themselves be pipelined (e.g., the execution circuit 100 may include multiple stages).

[0030] The concept of processor "pipelining" is well known and refers to the concept of dividing the "work" that a processor performs on an instruction into multiple stages. In some embodiments, decoding, dispatching, executing (i.e., proceeding), and retiring of instructions may be examples of different pipeline stages. Many different pipeline architectures may have different element / partial orderings. Various pipeline stages perform such steps on instructions during one or more processor clock cycles and then pass the instruction or operations associated with the instruction to other stages for further processing.

[0031] In some embodiments, the fetch stage circuit 210 is configured to fetch instructions for execution, including instructions that specify that a floating-point exponentiation function be evaluated. In some embodiments, the floating-point exponentiation instruction may be a single instruction set architecture (ISA) instruction. In some embodiments, the floating-point exponentiation instruction may be a single micro-operation supported by the processor. In other embodiments, a single floating-point exponentiation instruction may be implemented using multiple micro-operations. Note that in other embodiments, a floating-point exponentiation operation may be implemented using multiple instructions (e.g., two or three). However, in general, the ability to perform exponentiation operations using dedicated hardware support and a limited number of instructions may increase the throughput of exponentiation operations, with a single instruction implementation providing the greatest throughput.

[0032] In some embodiments, the disclosed techniques may allow the fetch stage circuit 210 to fetch floating point exponentiation instructions every cycle, which may significantly increase throughput relative to software-based techniques.

[0033] In the illustrated embodiment, decode stage circuitry 220 is configured to decode instructions fetched from stage 210. In some embodiments, decode 220 prepares the fetched instruction for further processing, such as by examining the opcode of the fetched instruction and determining the locations of source and destination operands.

[0034] According to some embodiments, in some embodiments, dispatch stage circuitry 230 is configured to dispatch operations to reservation stations (not shown) within various execution units of the pipeline circuitry.

[0035] In the illustrated embodiment, execution circuit 100 is configured to evaluate floating point power functions. In some embodiments, this includes evaluating base 2 logarithms, performing multiplication operations, and evaluating base 2 power functions, as described below with respect to Figure 3 Note that execution circuit 100 may also include various other units, such as integer units, load / store units, etc. Various units of execution circuit 100 may be pipelined.

[0036] Detailed implementation circuit

[0037] Figure 3 1 is a block diagram illustrating a detailed example execution circuit according to some embodiments. In the illustrated embodiment, the execution circuit 100 includes a base-2 logarithm circuit 110, a base-2 power function circuit 130, an exception control circuit 310, and various other circuit elements (e.g., multiplier 320, multiplexers 330, 340, 350, and 360, etc.).

[0038] In the illustrated embodiment, execution circuit 100 is configured to execute a single floating point exponentiation instruction to generate a power function result. In some embodiments, execution circuit 100 receives an input operand x, an input operand y, and a function input. In some embodiments, input operands x and y are provided in a first floating point format (e.g., an N-bit floating point format).

[0039] In some embodiments, the function inputs are based on the type of instruction being executed and specify whether intermediate results are to be provided, e.g., using the results evaluated by base 2 logarithm circuit 110 or base 2 power function circuit 130. Thus, portions of the disclosed hardware configured to execute power function instructions may also be advantageously used to execute other types of instructions, e.g., by selecting intermediate results.

[0040] In the illustrated embodiment, the base-2 logarithm circuit 110 calculates a base-2 logarithm for an input operand x. In some embodiments, this includes determining coefficients of a polynomial function based on the input operand x, and evaluating the polynomial function to determine an approximation of a base-2 logarithm result in a second floating-point format (e.g., a head-to-tail format having a header component of N bits or less and a tail component of N bits or less). In some embodiments, determining the base-2 logarithm result includes evaluating the polynomial function based on the determined coefficients and the input operand x.

[0041] In the illustrated embodiment, the base 2 logarithm result includes a head component log2a_head and a tail component log2a_tail, which are inputs to the illustrated multiplier circuit 320 to be multiplied with the input operand y.

[0042] In the illustrated embodiment, multiplier circuit 320 (which may correspond to Figure 1 The multiplication circuit 120) performs a head-tail multiplication operation based on the operands log2a_head, log2a_tail and y to generate a multiplication result including a multiplication head result and a multiplication tail result.

[0043] In the illustrated embodiment, the multiplication header result and the multiplication tail result are inputs to two separate multiplexer circuits 330 and 340, which propagate the multiplication header and multiplication tail results to the base 2 power function circuit 130 for the power function. However, for the base 2 power instruction (indicated by the function input EXP2), the input operand y and the value zero are instead propagated to the base 2 power function circuit 130.

[0044] In some embodiments, before propagating the specified value to the base-2 power function circuit 130, a conversion circuit (not shown) may convert the multiplication header result and the multiplication tail result to the floating-point format of the input operands to generate a converted multiplication result.

[0045] In the illustrated embodiment, the base-2 power function circuit 130 is configured to evaluate the representation of the multiplication result raised to a power of two to generate a result in a first floating point format. For example, the representation of the multiplication result may be the multiplication result itself or a converted multiplication result (e.g., converted from head to tail to a traditional format).

[0046] In some embodiments, the result generated by the base 2 power function circuit 130 is propagated through the multiplexer circuit 350 for the power instruction. However, for the base 2 logarithm instruction (indicated by the function input FLOG2), the head result (e.g., log2a_head) generated by the base 2 logarithm circuit 110 is propagated instead.

[0047] In the illustrated embodiment, according to some embodiments, the exception control circuit 310 is configured to generate exceptions in certain circumstances based on the input operands x and y provided and the function inputs. In some embodiments, the exception control circuit 310 is configured to ensure that the input operands x (e.g., base) and the input operands y (e.g., exponent) do not fall within a set of constraints, which may be programmable. In some embodiments, the constraints may include, but are not limited to, the following types of numbers: ± zero, ± ∞, ± QNaN (quiet non-number), ± SNaN (signaling non-number), ± subnormal number, negative normal number, etc.

[0048] In some embodiments, in response to detecting that input operand x or input operand y falls within the constraints listed above, exception control circuit 310 may provide a value of 0 for the is_valid signal and a value associated with the exception to multiplexer circuit 360. In some embodiments, the value of 0 for the is_valid signal selects the exception value as the output result of multiplexer circuit 360. In some embodiments, based on the specified function and input operands, the output result may be an SNaN value or some other suitable value.

[0049] Example of base 2 logarithm circuit

[0050] Figure 4 is a block diagram illustrating an example base-2 logarithm circuit according to some embodiments. In the illustrated embodiment, base-2 logarithm circuit 110 includes an argument shift circuit 410, a polynomial approximation circuit 420, a floating point conversion circuit 430, and a head-to-tail add circuit 440.

[0051] In the illustrated embodiment, the argument shift circuit 410 is configured to extract a mantissa value and an exponent value from a floating point input. In some embodiments, the argument shift circuit 410 receives an input operand x as input and performs one or more operations to output two values: a mantissa of x and an exponent of x.

[0052] In some embodiments, the argument shift circuit 410 computes the mantissa of x by performing a bit masked AND operation and a bit masked OR operation. In some embodiments, the argument shift circuit 410 generates the mantissa of x in a floating point format equivalent to 1.mantissa. In the illustrated embodiment, the mantissa of x is propagated to the polynomial approximation circuit 420. In some embodiments, the exponent of x is generated by performing a right shift operation, the number of bits of the right shift being equal to the size of the mantissa of x (e.g., 23 bits for the IEEE standard single precision floating point format).

[0053] In some embodiments, the disclosed circuits may be configured to provide results for input values ​​within a certain range. In some embodiments, for values ​​greater than the range, the mantissa of x is folded into a smaller range, which may reduce or avoid floating point elimination errors at later stages in the pipeline (e.g., in a multiplication step). As a non-limiting example, the mantissa of x may be folded into a smaller range [0.75, 1.5), which may reduce or avoid floating point elimination errors at later stages in the pipeline (e.g., in a multiplication step).

[0054] In the illustrated embodiment, the polynomial approximation circuit 420 is configured to generate an approximation of a base 2 logarithm based on the mantissa and generate a head result lgx_head and a tail result lgx_tail. Figure 5 A detailed example of circuit 420 is discussed in detail.

[0055] In the illustrated embodiment, an adder circuit subtracts the bias value from the exponent of x, with the result being propagated to floating point conversion circuit 430 .

[0056] In the illustrated embodiment, floating point conversion circuitry 430 is configured to convert the exponent of x minus the bias from a binary component representation to a single precision floating point representation ( Figure 4 unbiased index in ).

[0057] In the illustrated embodiment, the head-to-tail addition circuit 440 is configured to perform a head-to-tail addition operation between the unbiased exponent and the head (e.g., lgx_head) output and the tail (lgx_tail) output generated by the polynomial approximation circuit 420. In some embodiments, the head-to-tail addition includes performing separate 32-bit floating point addition operations to generate a head (log2a_head) result and a tail (log2a_tail) result.

[0058] Example Polynomial Approximation Circuit

[0059] Figure 5 is a block diagram illustrating a detailed polynomial approximation circuit according to some embodiments. In the illustrated embodiment, the polynomial approximation circuit 420 includes a polynomial coefficient table 510 and fused multiply / add circuits 520A-520C.

[0060] In the illustrated embodiment, the polynomial approximation circuit 420 is configured to perform the above-referenced Figure 4 The polynomial approximation to base 2 of the logarithm discussed.

[0061] In the illustrated embodiment, polynomial approximation circuit 420 receives the mantissa of x as input and generates a third-order polynomial approximation based on the mantissa of x and the coefficients stored in polynomial coefficient table 510. In some embodiments, the polynomial approximation is a piecewise polynomial approximation that includes multiple sets of coefficients corresponding to different ranges of input values ​​(e.g., C0-C3 in this example). In some embodiments, polynomial approximation circuit 420 implements the polynomial approximation equation ((x 尾数 ×C0+C1)×x 尾数 +C2)×x 尾数 + C3. In the example shown, coefficient C0 represents the highest-order coefficient of the third-order polynomial approximation, while coefficient C3 represents the lowest-order (eg, constant) coefficient of the third-order polynomial approximation.

[0062] In the illustrated embodiment, polynomial coefficient table 510 is configured to store coefficients of the polynomial approximation. Table 510 may store different sets of inputs for different ranges of input x tail values. In the illustrated embodiment, some of the determined coefficients include head and tail components (e.g., C2_head, C2_tail, etc.) and some of the determined coefficients do not use head-tail representation (e.g., C0, C1, etc.). This approach may meet accuracy goals without using head-tail representation of some values ​​(which may reduce area and power consumption).

[0063] In some embodiments, the coefficients stored in table 510 are generated using overlapping intervals. For example, the coefficients of a given entry in table 510 may correspond to a curve fit over a larger range of input values ​​than the range of input values ​​corresponding to the entry. As a hypothetical example and for purposes of explanation, a given entry of table 510 may store (and return) coefficients for the mantissa of x in the input value range [0.80, 0.90), but the corresponding coefficients of the given entry may correspond to a curve fit operation over a larger range [0.78, 0.92).

[0064] In some embodiments, using overlapping intervals to generate the coefficients in table 510 preserves the monotonicity of the base-2 logarithm approximation. This can also advantageously reduce errors (which are typically greatest near the edges of a given interval).

[0065] In the illustrated embodiment, the fused multiply / add circuits 520A-520C are configured to perform a cascaded fused multiply-add operation between the determined coefficients and the mantissa of x to implement the polynomial. In other embodiments, the fused multiply-add operation may use a variation of the mantissa of x to implement the polynomial. For example, before the fused multiply / add circuits 520A-520C perform the cascaded fused multiply-add operation, a conversion circuit (not shown) may convert the mantissa of x into a different format. In some embodiments, the fused multiply / add circuits 520A-520C perform fixed-point fused multiply / add operations.

[0066] In some embodiments, the fused multiply / add circuit 520A performs a multiplication operation between the mantissa of x and the coefficient C0, followed by the addition of the coefficient C1, to generate the expression (x) represented by the intermediate result z1. 尾数 ×C0+C1).

[0067] In some embodiments, the fused multiply / add circuit 520B performs a multiplication between the intermediate result z1 and the mantissa of x, followed by a head-to-tail addition operation using coefficients C2_head and C2_tail to generate intermediate results z2_head and z2_tail. In some embodiments, the intermediate result z2_head represents the expression (x 尾数 ×C0+C1)×x 尾数 +C2_head, and z2_tail means (x 尾数 ×C0+C1)×x 尾数 +C2_tail.

[0068] In some embodiments, the fused multiply / add circuit 520C performs a separate head-to-tail multiplication operation between the intermediate results z2_head and z2_tail and the mantissa of x, followed by a head-to-tail addition operation using coefficients C3_head and C3_tail to generate a log2a_head result and a log2a_tail result. In some embodiments, log2a_head and log2a_tail represent the head component and the tail component of the base-2 logarithmic polynomial approximation, respectively.

[0069] Example Method

[0070] Figure 6 is a flowchart illustrating an example method according to some embodiments. Figure 6The method shown can be used in conjunction with any of the computer circuits, systems, devices, elements or components disclosed herein. In various embodiments, some of the method elements shown can be performed concurrently in a different order than shown, or can be omitted. Additional method elements can also be performed as needed.

[0071] At 610, in the illustrated embodiment, a computing device (eg, execution circuit 100) executes a single power instruction that operates on a first floating point input and a second floating point input in a first floating point format to generate a power function The result of evaluating.

[0072] In some embodiments, the first floating point format is an N-bit floating point format. As an example, the first floating point format may be an IEEE standard single-precision floating point format, which uses 32 bits to represent floating point numbers.

[0073] At 620 , in the illustrated embodiment, a computing device (eg, base 2 logarithm circuit 110 ) determines coefficients of a polynomial function based on the first input.

[0074] In some embodiments, the polynomial function is a third order polynomial.In some embodiments, determining coefficients of the polynomial function includes accessing a table of polynomial coefficients based on the first input.

[0075] In some embodiments, a given entry of the polynomial coefficient table includes multiple coefficients of a third-order polynomial corresponding to a range of input values.

[0076] In some embodiments, overlapping intervals are used to generate a table of polynomial coefficients such that the coefficients for a given entry in the table of polynomial coefficients correspond to a curve fit over a larger range of input values ​​than the range of input values ​​corresponding to the entry.

[0077] At 630 , in the illustrated embodiment, a computing device (eg, base 2 logarithm circuit 110 ) evaluates the polynomial function based on the determined coefficients and the first input to determine a first result in a second floating point format.

[0078] In some embodiments, the second floating point format includes a header component and a tail component (e.g., a head-tail format). In some embodiments, this includes a header component of N bits or less and a tail component of N bits or less. In some embodiments, the head-tail format is used to generate a higher precision result so that rounding errors do not become unacceptable at a later stage (e.g., in the multiplication operation at 640). The head-tail format uses two lower precision components to represent a higher precision number and operates on the two components separately.

[0079] In some embodiments, one or more of the determined coefficients include a head component and a tail component, and one or more of the determined coefficients use a non-head-tail representation.

[0080] In some embodiments, the first result includes a first head result and a first tail result.

[0081] At 640 , in the illustrated embodiment, the computing device (eg, multiplication circuit 120 ) multiplies the first result by the second floating point input to generate a multiplication result.

[0082] In some embodiments, the multiplication is a head and tail operation, and the multiplication result includes a second head result (e.g., a multiplication head result) and a second tail result (e.g., a multiplication tail result).

[0083] At 650 , in the illustrated embodiment, a computing device (eg, base-2 power function circuit 130 ) evaluates the represented power of the multiplication result of two to generate a single floating point power function result in a first floating point format.

[0084] In some embodiments, to evaluate the represented power of the multiplication result of two, a computing device (e.g., base-2 power function circuit 130) determines coefficients of a third-order polynomial function based on the multiplication result, and evaluates the third-order polynomial function to determine the represented power of the multiplication result of two in a first floating-point format.

[0085] In some embodiments, the computing device converts the second header result and the second tail result into the first floating point format to generate a converted multiplication result. In some embodiments, the computing device (e.g., base 2 power function circuit 130) evaluates the converted multiplication result raised to a power of two.

[0086] In some embodiments, the first header result, the first tail result, the second header result, and the second tail result are all represented using N bits or fewer. In some embodiments, the computing device (e.g., execution circuit 100) also executes a base 2 logarithm instruction and evaluates the base 2 logarithm of the input to generate a result of the base 2 logarithm instruction. In some embodiments, the computing device includes a multiplexer circuit that selects the result of the base 2 logarithm instruction.

[0087] In some embodiments, the computing device (e.g., execution circuit 100) further executes a power function instruction with base 2 and evaluates the input power function with base 2 to generate a result of the power function instruction with base 2. In some embodiments, the computing device (e.g., execution circuit 100) includes a multiplexer circuit to select the result of the power function instruction with base 2.

[0088] Example Device

[0089] Reference now Figure 7 , which shows a block diagram of an example embodiment of an exemplary device 700. In some embodiments, elements of the device 700 may be included in a system on a chip. In some embodiments, the device 700 may be included in a mobile device that may be battery powered. Therefore, the power consumption of the device 700 may be an important design consideration. In the illustrated embodiment, the device 700 includes a structure 710, a computing complex 720, an input / output (I / O) bridge 750, a cache / memory controller 745, a graphics unit 775, and a display unit 765. In some embodiments, in addition to or in place of the components shown, the device 700 may include other components (not shown), such as video processor encoders and decoders, image processing or recognition elements, computer vision elements, etc.

[0090] The structure 710 may include various interconnects, buses, MUXs, controllers, etc., and may be configured to facilitate communication between various elements of the device 700. In some embodiments, portions of the structure 710 may be configured to implement a variety of different communication protocols. In other embodiments, the structure 710 may implement a single communication protocol, and elements coupled to the structure 710 may internally convert from the single communication protocol to other communication protocols.

[0091] In the illustrated embodiment, computing complex 720 includes bus interface unit (BIU) 725, cache 730, and cores 735 and 740. In various embodiments, computing complex 720 may include various numbers of processors, processor cores, and caches. For example, computing complex 720 may include 1, 2, or 4 processor cores, or any other suitable number. In one embodiment, cache 730 is a set of associative L2 caches. In some embodiments, cores 735 and / or 740 may include internal instruction and data caches. In some embodiments, a consistency unit (not shown) in structure 710, cache 730, or elsewhere in device 700 may be configured to maintain consistency between the various caches of device 700. BIU 725 may be configured to manage communications between computing complex 720 and other elements of device 700. Processor cores such as cores 735 and 740 may be configured to execute instructions of a specific instruction set architecture (ISA) that may include operating system instructions and user application instructions.

[0092] The cache / memory controller 745 may be configured to manage data transfers between the structure 710 and one or more caches and memories. For example, the cache / memory controller 745 may be coupled to an L3 cache, which in turn may be coupled to system memory. In other embodiments, the cache / memory controller 745 may be coupled directly to the memory. In some embodiments, the cache / memory controller 745 may include one or more internal caches.

[0093] As used herein, the term "coupled to" may indicate one or more connections between elements, and a coupling may include intermediate elements. Figure 7 In FIG, graphics unit 775 may be described as being "coupled to" memory via structure 710 and cache / memory controller 745. In contrast, in Figure 7 In the illustrated embodiment, graphics unit 775 is "directly coupled" to structure 710 because there are no intervening elements.

[0094] Graphics unit 775 may include one or more processors, such as one or more graphics processing units (GPUs). For example, graphics unit 775 receives graphics-oriented instructions, such as Metal or Instructions. The graphics unit 775 may execute dedicated GPU instructions or perform other operations based on the received graphics-oriented instructions. The graphics unit 775 may be configured to process large data blocks in parallel and may build images in a frame buffer to output to a display, which may be included in the device or may be a separate device. The graphics unit 775 may include transformation, lighting, triangle and rendering engines in one or more graphics processing pipelines. The graphics unit 775 may output pixel information for displaying an image. In various embodiments, the graphics unit 775 may include a programmable shader circuit, which may include a highly parallel execution core configured to execute graphics programs, which may include pixel tasks, vertex tasks and computational tasks (which may be graphics-related or may not be graphics-related).

[0095] The display unit 765 may be configured to read data from the frame buffer and provide a stream of pixel values ​​for display. In some embodiments, the display unit 765 may be configured as a display pipeline. In addition, the display unit 765 may be configured to blend multiple frames to produce an output frame. In addition, the display unit 765 may include one or more interfaces (e.g., a touch screen or an external display) for coupling to a user display (e.g., or embedded DisplayPort (eDP).

[0096] The I / O bridge 750 may include various elements configured to implement, for example, universal serial bus (USB) communications, security, audio, and low-power always-on functionality. The I / O bridge 750 may also include interfaces such as, for example, pulse width modulation (PWM), general purpose input / output (GPIO), serial peripheral interface (SPI), and inter-integrated circuit (I2C). Various types of peripherals and devices may be coupled to the device 700 via the I / O bridge 750.

[0097] In some embodiments, the device 700 includes a network interface circuit (not explicitly shown), which can be connected to the structure 710 or the I / O bridge 750. The network interface circuit can be configured to communicate via various networks, which can be wired networks, wireless networks, or both. For example, the network interface circuit can be configured to communicate via a wired local area network, a wireless local area network (e.g., via WiFi) or a wide area network (e.g., the Internet or a virtual private network). In some embodiments, the network interface circuit is configured to communicate via one or more cellular networks using one or more radio access technologies. In some embodiments, the network interface circuit is configured to communicate using device-to-device communication (e.g., Bluetooth or WiFi direct connection) and the like. In various embodiments, the network interface circuit can provide the device 700 with connections to various types of other devices and networks.

[0098] Figure 7 Various elements of the system may utilize the disclosed techniques. For example, execution circuit 100 may be included in compute complex 720 or graphics unit 775. In various embodiments, the disclosed techniques may advantageously improve the performance and reduce the power consumption of floating point power function operations with reasonable area and accuracy.

[0099] Sample Application

[0100] Now go to Figure 8 , various types of systems that may include any of the circuits, devices, or systems described above are shown. Systems or devices 800 that may combine or otherwise utilize one or more of the techniques described herein are used in a wide range of fields. For example, system or device 800 may be used as part of the hardware of a system such as a desktop computer 810, a laptop computer 820, a tablet computer 830, a cellular or mobile phone 840, or a television 850 (or a set-top box coupled to a television).

[0101] Similarly, the disclosed elements can be used in a wearable device 860, such as a smart watch or a health monitoring device. In many embodiments, a smart watch can implement a variety of different functions—for example, access to email, cellular service, calendar, health monitoring, etc. The wearable device can also be designed to perform only health monitoring functions, such as monitoring the user's vital signs, performing epidemiological functions such as contact tracing, providing communications to emergency medical services, etc. Other types of devices are also contemplated, including devices worn around the neck, devices that can be implanted in the human body, glasses or helmets designed to provide computer-generated reality experiences, such as those based on augmented reality and / or virtual reality, etc.

[0102] The system or device 800 can be used in various other contexts. For example, the system or device 800 can be used in the context of a server computer system (such as a dedicated server) or on shared hardware that implements a cloud-based service 870. Further, the system or device 800 can be implemented in a wide range of dedicated everyday devices, including devices 880 commonly found in the home, such as refrigerators, thermostats, security cameras, etc. The interconnection of such devices is generally referred to as the "Internet of Things" (IoT). Elements can also be implemented in various modes of transportation. For example, the system or device 800 can be used for control systems, guidance systems, entertainment systems, etc. of various types of vehicles 890.

[0103] Figure 8 The applications shown in are merely exemplary and are not intended to limit the potential future applications of the disclosed system or device. Other example applications include, but are not limited to: portable game devices, music players, data storage devices, unmanned aerial vehicles, etc.

[0104] Example Computer Readable Medium

[0105] The disclosure has described various example circuits in detail above. It is intended that the disclosure encompass not only embodiments including such circuits, but also computer-readable storage media including design information specifying such circuits. Thus, the disclosure is intended to support claims that encompass not only devices including the disclosed circuits, but also storage media that specify the circuits in a format recognized by a manufacturing system configured to produce hardware (e.g., an integrated circuit) that includes the disclosed circuits. Claims to such storage media are intended to cover, for example, entities that generate a circuit design but do not manufacture the design itself.

[0106] Fig. 9 is a block diagram illustrating an example non-transitory computer-readable storage medium storing circuit design information according to some embodiments. In the illustrated embodiment, a semiconductor manufacturing system 920 is configured to process design information 915 stored on a non-transitory computer-readable storage medium 910 and to manufacture an integrated circuit 930 based on the design information 915.

[0107] The non-transitory computer-readable storage medium 910 may include any of a variety of suitable types of memory devices or storage devices. The non-transitory computer-readable storage medium 910 may be an installation medium, such as a CD-ROM, a floppy disk, or a tape device; a computer system memory or random access memory, such as DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc.; a non-volatile memory, such as flash memory, a magnetic medium, for example, a hard drive or an optical storage device; a register, or other similar types of memory elements, etc. The non-transitory computer-readable storage medium 910 may also include other types of non-transitory memories or combinations thereof. The non-transitory computer-readable storage medium 910 may include two or more memory media that may reside in different locations, such as different computer systems connected by a network.

[0108] The design information 915 may be specified using any of a variety of suitable computer languages, including hardware description languages ​​such as, but not limited to, VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. The design information 915 may be capable of being used by the semiconductor manufacturing system 920 to manufacture at least a portion of the integrated circuit 930. The format of the design information 915 may be recognizable by at least one semiconductor manufacturing system 920. In some embodiments, the design information 915 may also include one or more cell libraries that specify the synthesis, layout, or both of the integrated circuit 930. In some embodiments, the design information is specified in whole or in part in the form of a netlist that specifies the cell library elements and their connectivity. The design information 915 obtained separately may or may not include sufficient information for manufacturing the corresponding integrated circuit. For example, the design information 915 may specify the circuit elements to be manufactured, but not their physical layout. In this case, the design information 915 may need to be combined with the layout information to actually manufacture the specified circuit.

[0109] In various embodiments, the integrated circuit 930 may include one or more custom macrocells, such as memory, analog or mixed signal circuits, etc. In this case, the design information 915 may include information related to the included macrocells. Such information may include, but is not limited to, a schematic capture database, mask design data, behavioral models, and device or transistor level netlists. As used herein, the mask design data may be formatted according to a graphic data system (GDSII) or any other suitable format.

[0110] Semiconductor manufacturing system 920 may include any of a variety of suitable elements configured to manufacture integrated circuits. This may include, for example, elements for depositing semiconductor material (e.g., on a wafer that may include a mask), removing material, changing the shape of deposited material, modifying material (e.g., by doping the material or using ultraviolet treatment to modify the dielectric constant), etc. Semiconductor manufacturing system 920 may also be configured to perform various tests of the manufactured circuits for proper operation.

[0111] In various embodiments, integrated circuit 930 is configured to operate according to the circuit design specified by design information 915, which may include performing any of the functionality described herein. For example, integrated circuit 930 may include Figures 1 to 5 and Figure 7 Any of the various elements shown in . In addition, the integrated circuit 930 can be configured to perform various functions described herein in conjunction with other components. In addition, the functionality described herein can be performed by multiple connected integrated circuits.

[0112] As used herein, a phrase of the form "design information specifying a design of a circuit configured to..." does not imply that the circuit in question must be manufactured in order to satisfy the element. Rather, the phrase indicates that the design information describes a circuit that, when manufactured, will be configured to perform the indicated actions or will include the specified components.

[0113] ***

[0114] This disclosure includes references to "an embodiment" or groups of "embodiments" (e.g., "some embodiments" or "various embodiments"). Embodiments are different specific implementations or examples of the disclosed concepts. References to "an embodiment," "one embodiment," "a particular embodiment," etc. are not necessarily to the same embodiment. A large number of possible embodiments are contemplated, including those specifically disclosed, as well as modifications or alternatives that fall within the spirit or scope of the present disclosure.

[0115] The present disclosure may discuss potential advantages that may be generated by the disclosed embodiments. Not all of these implementations will necessarily exhibit any or all of the potential advantages. Whether a particular implementation achieves an advantage depends on many factors, some of which are outside the scope of the present disclosure. In fact, there are many reasons why an implementation that falls within the scope of the claims may not exhibit some or all of any of the disclosed advantages. For example, a particular implementation may include other circuits outside the scope of the present disclosure that, in combination with one of the disclosed embodiments, negate or reduce one or more of the disclosed advantages. In addition, suboptimal design execution of a particular implementation (e.g., a specific implementation technique or tool) may also negate or reduce the disclosed advantages. Even assuming a specific implementation of the technology, the realization of the advantages may still depend on other factors, such as the environmental conditions in which the specific implementation is deployed. For example, the input provided to a particular implementation may prevent one or more problems solved in the present disclosure from occurring in a particular occasion, and as a result, the benefits of its solution may not be realized. In view of the existence of possible factors external to the present disclosure, it is hereby clarified that any potential advantages described herein should not be construed as claim limitations that must be met in order to prove infringement. Instead, the identification of such potential advantages is intended to illustrate the types of improvements available to designers who benefit from the present disclosure. Permanently describing such advantages (eg, stating that a particular advantage "may occur") is not intended to convey a doubt as to whether such advantage can actually be achieved, but rather to recognize that achievement of such advantage typically depends on technical realities of additional factors.

[0116] Unless otherwise stated, the embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of the claims drafted based on the present disclosure, even if only a single example is described with respect to a particular feature. The disclosed embodiments are intended to be illustrative and not restrictive, without any contrary statement in the present disclosure. Therefore, the present application is intended to allow claims covering the disclosed embodiments, as well as such alternatives, modifications and equivalents, which will be apparent to those skilled in the art who are aware of the beneficial effects of the present disclosure.

[0117] For example, features in this application may be combined in any suitable manner. Accordingly, new claims may be made during the prosecution of this application (or an application claiming priority thereto) for any such combination of features. In particular, with reference to the appended claims, features of dependent claims may be combined, where appropriate, with features of other dependent claims, including claims that are dependent on other independent claims. Similarly, features from corresponding independent claims may be combined, where appropriate.

[0118] Thus, while the appended dependent claims may be drafted such that each dependent claim is dependent upon a single other claim, additional dependencies are also contemplated. Any combination of dependent features consistent with the present disclosure is contemplated and may be claimed in this or another application. In short, the combinations are not limited to those specifically recited in the appended claims.

[0119] It is also contemplated that claims drafted in one format or legal type (eg, apparatus) are intended to support corresponding claims in another format or legal type (eg, method), where appropriate.

[0120] ***

[0121] Because this disclosure is a legal document, various terms and phrases may be subject to regulatory and judicial interpretation. Notice is hereby given that the definitions provided in the following paragraphs and throughout this disclosure will be used to determine how to interpret claims drafted based on this disclosure.

[0122] Unless the context clearly dictates otherwise, reference to an item in the singular (i.e., a noun or noun phrase preceded by "a," "an," or "the") is intended to mean "one or more." Thus, reference to "an item" in a claim does not exclude additional instances of that item without the accompanying context. A "plurality" of an item refers to a collection of two or more of the items.

[0123] The word "may" is used herein in a permissive sense (ie, having the potential to, being able to), rather than the mandatory sense (ie, must).

[0124] The terms "including" and "comprising" and forms thereof are open ended and mean "including, but not limited to."

[0125] When the term "or" is used in this disclosure with respect to a list of options, it will generally be understood to be used in an inclusive sense unless the context provides otherwise. Thus, the expression "x or y" is equivalent to "x or y, or both," and thus encompasses 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, phrases such as "either x or y, but not both" make it clear that "or" is used in an exclusive sense.

[0126] The expressions "w, x, y, or z, or any combination thereof" or "... at least one of w, x, y, and z" are intended to cover all possibilities involving individual elements up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase "... at least one of w, x, y, and z" thus refers to at least one element in the set [w, x, y, z], thereby covering all possible combinations in the list of elements. The phrase should not be interpreted as requiring the presence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0127] In this disclosure, various "labels" may precede a noun or noun phrase. Unless the context provides otherwise, different labels used for a feature (e.g., "a first circuit," "a second circuit," "a particular circuit," "a given circuit," etc.) refer to different instances of the feature. Additionally, unless otherwise stated, the labels "first," "second," and "third" do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to features.

[0128] The phrase "based on" or is used to describe one or more factors that influence a determination. The term does not exclude the possibility that additional factors may influence the determination. That is, a determination may be based only on the specified factors or on the specified factors and other unspecified factors. Consider the phrase "A is determined based on B." The phrase specifies that B is a factor used to determine A or that B influences the determination of A. The phrase does not exclude that the determination of A may also be based on some other factor such as C. The phrase is also intended to cover embodiments in which A is determined based only on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0129] The phrases "in response to" and "in response to" describe one or more factors that trigger an effect. The phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect, either in conjunction with the specified factors or independently of the specified factors. That is, the effect may be responsive to these factors alone, or may be responsive to the specified factors as well as other unspecified factors. Consider the phrase "A is performed in response to B." The phrase specifies that B is a factor that triggers the execution of A or triggers a specific result of A. The phrase does not exclude that the execution of A may also be responsive to certain other factors, such as C. The phrase also does not exclude that the execution of A may be performed jointly in response to B and C. The phrase is also intended to cover embodiments in which A is performed only in response to B. As used herein, the phrase "in response to" is synonymous with the phrase "at least partially in response to." Similarly, the phrase "in response to" is synonymous with the phrase "at least partially in response to."

[0130] ***

[0131] Within the present disclosure, different entities (which may be variously referred to as "units," "circuits," other components, etc.) may be described or claimed as being "configured to" perform one or more tasks or operations. The expression—[an entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a physical thing). More specifically, the expression is used to indicate that the structure is arranged to perform one or more tasks during operation. A structure may be considered to be "configured to" perform a task even if the structure is not currently being operated. Thus, an entity described or stated as "configured to" perform a task refers to a physical thing used to implement the task, such as a device, a circuit, a system with a processor unit, and a memory storing executable program instructions, etc. This phrase is not used herein to refer to an intangible thing.

[0132] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. It should be understood that these entities are "configured to" perform those tasks / operations, even if not specifically stated.

[0133] The term "configured to" is not intended to mean "capable of being configured to". For example, an unprogrammed FPGA would not be considered "configured to" perform a particular function. However, the unprogrammed FPGA may be "configurable to" perform that function. After being appropriately programmed, the FPGA may then be considered "configured to" perform a particular function.

[0134] For purposes of a U.S. patent application based on the present disclosure, stating in a claim that a structure is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. §112(f) for that claim element. If the applicant wishes to invoke section 112(f) during prosecution of a U.S. patent application based on the present disclosure, it would use the “means for [performing the function]” construct to phrase the claim element.

[0135] Different "circuits" may be described in the present disclosure. These circuits or "circuits" constitute hardware that includes various types of circuit elements, such as combinational logic, clock storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. Circuits may be custom designed or taken from a standard library. In various specific implementations, circuits may include digital components, analog components, or a combination of both, as appropriate. Certain types of circuits may be generally referred to as "units" (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such units are also referred to as circuits or circuits.

[0136] Thus, the disclosed circuits / units / components and other elements illustrated in the drawings and described herein include hardware elements, such as those described in the preceding paragraphs. In many cases, the internal arrangement of hardware elements in a particular circuit can be specified by describing the functionality of that circuit. For example, a particular "decode unit" may be described as performing the function of "processing an opcode for an instruction and routing the instruction to one or more of a plurality of functional units," meaning that the decode unit is "configured to" perform that function. For one skilled in the computer arts, this functional specification is sufficient to suggest a set of possible structures for the circuit.

[0137] In various embodiments, as described in the preceding paragraphs, circuits, units, and other elements may be defined by the functions or operations they are configured to implement. The arrangement relative to each other and such circuits / units / components and the way they interact form a microarchitecture definition of hardware, which is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitecture definition. Therefore, the microarchitecture definition is considered by those skilled in the art to be a structure from which many physical implementations can be derived, all of which fall into the broader structure described by the microarchitecture definition. That is, a technician with a microarchitecture definition provided in accordance with the present disclosure can implement the structure by coding a description of a circuit / unit / component in a hardware description language (HDL) such as Verilog or VHDL without excessive experimentation and using the application of ordinary technicians. HDL descriptions are often expressed in a way that can be displayed as functional. However, for those skilled in the art, the HDL description is a way to convert the structure of a circuit, unit, or component into the next level of specific implementation details. Such HDL descriptions may take the form of behavioral code (which is generally non-synthesizable), register transfer language (RTL) code (which is generally synthesizable compared to behavioral code), or structural code (e.g., a netlist specifying logic gates and their connectivity). The HDL description may be sequentially synthesized for a library of cells designed for a given integrated circuit manufacturing technology, and may be modified for timing, power, and other reasons to obtain a final design database that is sent to the factory to generate masks and ultimately produce integrated circuits. Some hardware circuits or portions thereof may also be custom designed in a schematic editor and captured into an integrated circuit design along with the synthesized circuits. The integrated circuit may include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.), as well as interconnects between transistors and circuit elements. Some embodiments may implement multiple integrated circuits coupled together to implement the hardware circuit, and / or discrete elements may be used in some embodiments. Alternatively, the HDL design may be synthesized into a programmable logic array such as a field programmable gate array (FPGA), and may be implemented in an FPGA. This decoupling between the design of a set of circuits and the subsequent low-level implementation of those circuits often leads to a situation where a circuit or logic designer never specifies a particular set of structures for the low-level implementation beyond a description of what the circuits are configured to do, because that process is performed at different stages of the circuit implementation process.

[0138] The fact that many different low-level combinations of circuit elements can be used to achieve the same specification of a circuit results in a large number of identical structures for that circuit. As noted, these low-level circuit implementations can vary depending on variations in manufacturing technology, the foundry selected to manufacture the integrated circuit, the cell libraries provided for a particular project, etc. In many cases, the selection made by different design tools or methodologies to produce these different implementations can be arbitrary.

[0139] Furthermore, for a given embodiment, a single implementation of a particular functional specification of a circuit typically includes a large number of devices (e.g., millions of transistors). Thus, the shear volume of this information makes it impractical to provide a complete description of the low-level structure used to implement a single embodiment, let alone the large number of equivalent possible implementations. For this reason, the present disclosure describes the structure of the circuit using functional shorthand commonly used in the industry.

Claims

1. A device, comprising: An execution circuit is configured to perform an operation on a first floating point input and a second floating point input in a first floating point format to generate a pair of 2 (第二输入*log 2 (第一输入)) The result of the evaluation is performed, wherein the execution circuit comprises: a base-2 logarithm circuit configured to evaluate a base-2 logarithm of the first input, comprising: determining coefficients of a polynomial function based on the first input; and evaluating the polynomial function based on the determined coefficients and the first input to determine a first result in a second floating point format; a multiplication circuit configured to multiply the first result by the second floating-point input to generate a multiplication result; and A base-2 power function circuit is configured to evaluate a represented power of the multiplication result of two to generate a result of the single floating point power instruction in the first floating point format.

2. The apparatus of claim 1, wherein the second floating point format comprises a header component and a trailer component; The first result includes a first head result and a first tail result; and The multiplication is a head-tail operation, and the multiplication result includes a second head result and a second tail result.

3. The apparatus according to claim 2, further comprising: conversion circuitry configured to convert the second header result and the second tail result into the first floating point format to generate a converted multiplication result; Wherein the base 2 power function circuit is configured to evaluate the converted multiplication result raised to a power of two. 4 . The apparatus of claim 3 , wherein the first floating point format is an N-bit floating point format, and the first header result, the first tail result, the second header result, and the second tail result are each represented using N bits or less.

5. The apparatus of claim 1, wherein the polynomial function is a third-order polynomial, and wherein to determine coefficients of the third-order polynomial, the base-2 logarithm circuit is further configured to access a table of polynomial coefficients based on the first input. 6 . The apparatus of claim 5 , wherein one or more of the determined coefficients include a head component and a tail component, and one or more of the determined coefficients use a non-head-tail representation.

7. The apparatus of claim 5, wherein a given entry of the polynomial coefficient table comprises a plurality of coefficients of the third-order polynomial corresponding to a range of input values.

8. The apparatus of claim 7, wherein the polynomial coefficient table is generated using overlapping intervals so that coefficients for a given entry in the polynomial coefficient table correspond to a curve fit over a larger range of input values ​​than the range of input values ​​corresponding to the entry.

9. The apparatus of claim 1 , wherein to evaluate the represented power of the multiplication result of two, the base 2 power function circuit is configured to: determining coefficients of a third-order polynomial function based on the multiplication result; and The third order polynomial function is evaluated to determine a representation power of the multiplication result of two in the first floating point format.

10. The apparatus of claim 1 , wherein the execution circuit is further configured to execute a base 2 logarithm instruction, including for evaluating the base 2 logarithm of an input using the base 2 logarithm circuit to generate a result of the base 2 logarithm instruction; and Wherein the execution circuit includes a multiplexer circuit configured to select the result of the base 2 logarithm instruction from the base 2 logarithm circuit.

11. The apparatus of claim 1 , wherein the execution circuit is further configured to execute a base 2 power instruction, including for evaluating a base 2 power function of an input using the base 2 power function circuit to generate a result of the base 2 power instruction; and Wherein the execution circuit includes a multiplexer circuit configured to select the result of the base 2 power instruction from the base 2 power function circuit.

12. The apparatus of claim 1, wherein the apparatus is a computing device, the computing device further comprising: monitor; Central processing unit; and Network interface circuit.

13. A method comprising: A single floating point exponentiation instruction is executed by a computing device to operate on a first floating point input and a second floating point input in a first floating point format to generate a power of 2 (第二输入*log 2 (第一输入)) The result of evaluating, wherein the executing comprises: determining coefficients of a polynomial function based on the first input; evaluating the polynomial function based on the determined coefficients and the first input to determine a first result in a second floating point format; multiplying the first result by the second floating point input to generate a multiplication result; and A represented power of the multiplication result of two is evaluated to generate a result of a single floating point power function in the first floating point format.

14. The method according to claim 13, wherein: The second floating point format includes a header component and a trailer component; The first result includes a first head result and a first tail result; and The multiplication is a head and tail operation, and the multiplication result includes a second head result and a second tail result.

15. The method of claim 13, wherein the polynomial function is a third order polynomial, and wherein determining coefficients of the third order polynomial comprises accessing a table of polynomial coefficients based on the first input.

16. The method of claim 15, wherein one or more of the determined coefficients include a head component and a tail component, and one or more of the determined coefficients use a non-head-tail representation.

17. A non-transitory computer-readable medium having instructions stored thereon, the instructions executable by a computing device to perform operations comprising: Execute a single floating point power instruction in the instructions to operate on a first floating point input and a second floating point input in a first floating point format to generate a power of 2 (第二输入*log 2 (第一输入)) The result of evaluating, wherein the executing comprises: evaluating a base 2 logarithm of the first input, including determining coefficients of a polynomial function based on the first input, and evaluating the polynomial function based on the determined coefficients and the first input to determine a first result in a second floating point format; multiplying the first result by the second floating point input to generate a multiplication result; as well as A represented power of the multiplication result of two is evaluated to generate a result of the single floating point exponentiation instruction in the first floating point format.

18. The non-transitory computer readable medium of claim 17, wherein the second floating point format comprises a header component and a trailer component; The first result includes a first head result and a first tail result; and The multiplication is a head-tail operation, and the multiplication result includes a second head result and a second tail result.

19. The non-transitory computer readable medium of claim 18, wherein the executing further comprises: The second header result and the second tail result are converted to the first floating point format to generate a converted multiplication result.

20. The non-transitory computer readable medium of claim 17, wherein the executing further comprises: Coefficients of a third order polynomial function are determined to evaluate the base 2 logarithm of the first input, wherein the determining includes accessing a table of polynomial coefficients based on the first input.

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