Method for manufacturing semiconductor device and semiconductor device

Abstract

A method for manufacturing a semiconductor device includes: forming a lower electrode on a substrate; forming a high dielectric constant film comprising an oxide containing tetravalent metal cations on the lower electrode; forming an oxide film comprising an oxide containing a pentavalent metal cation on the high dielectric constant film; forming a conductive mixed layer in which an oxide containing a tetravalent metal cation and an oxide containing a pentavalent metal cation are mixed by reacting the high dielectric constant film with the oxide film; and forming an upper electrode.

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a semiconductor device and a semiconductor device. Background Art

[0002] As capacitors used in DRAM (dynamic random access memory) and the like, capacitors are used in which a lower electrode, a high dielectric constant film, and an upper electrode are sequentially formed on a substrate. Patent Document 1 describes a capacitor using zirconium oxide as the high dielectric constant film.

[0003] Patent Document 2 discloses a first dielectric film including tantalum oxide or niobium oxide, a second dielectric film provided between a lower electrode and the first dielectric film, and a third dielectric film provided between the first dielectric film and an upper electrode. It is also disclosed that zirconium oxide or the like is used as the second dielectric film and the third dielectric film.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2001-152339

[0007] Patent Document 2: Japanese Patent Application Publication No. 2004-266009 Summary of the invention

[0008] Problem that the invention aims to solve

[0009] The present disclosure provides a method for manufacturing a semiconductor device and a semiconductor device capable of achieving both high capacitance and low leakage current of a capacitor.

[0010] Solutions for solving problems

[0011] A method for manufacturing a semiconductor device according to one embodiment of the present invention comprises: forming a lower electrode on a substrate; forming a high dielectric constant film composed of an oxide containing a tetravalent metal cation on the aforementioned lower electrode; forming an oxide film composed of an oxide containing a pentavalent metal cation on the aforementioned high dielectric constant film; forming a mixed layer having conductivity formed by a mixture of the aforementioned oxide containing a tetravalent metal cation and the aforementioned oxide containing a pentavalent metal cation by reacting the aforementioned high dielectric constant film with the aforementioned oxide film; and forming an upper electrode.

[0012] Effects of the Invention

[0013] According to the present disclosure, a method for manufacturing a semiconductor device and a semiconductor device capable of achieving both high capacitance and low leakage current of a capacitor are provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1It is a flowchart which shows the manufacturing method of the semiconductor device of 1st Embodiment.

[0015] Figure 2 The figures are cross-sectional views showing the steps of the method for manufacturing the semiconductor device according to the first embodiment.

[0016] Figure 3 This is a diagram showing the relationship between CET and leakage current in a conventional ZrO2 single film capacitor.

[0017] Figure 4 A cross-sectional view showing a portion of the structure of a conventional capacitor.

[0018] Figure 5 This is a diagram showing the distribution of density of states (DOS) obtained by calculation when five of the 16 Ti sites in TiO2 are replaced with Zr.

[0019] Figure 6 This is a graph showing the relationship between the number of Zr atoms at the site where Ti of TiO2 is substituted and the band gap.

[0020] Figure 7 This is a diagram showing the distribution of the density of states (DOS) obtained by calculation when the number of substitutions of 24 Nb sites in Nb2O5 with Zr is 0 and 8.

[0021] Figure 8 This is a graph showing the relationship between the number of Zr atoms at the site where Nb of Nb2O5 is substituted and the band gap.

[0022] Fig. 9 The diagram shows the results of actually manufacturing the semiconductor device (capacitor) according to the first embodiment and observing the characteristics.

[0023] Fig.10 It is a flowchart showing the manufacturing method of the semiconductor device of the second embodiment.

[0024] Fig.11 The present invention is a cross-sectional view showing a part of the steps of the method for manufacturing a semiconductor device according to the second embodiment.

[0025] Fig.12 represents the Nb2O5 oxygen vacancy formed relative to Nb 12 O 29 A diagram showing the distribution of density of states (DOS) obtained by calculation when the number of substitutions of 28 sites of Nb with Zr is 4.

[0026] Fig.13 To replace Nb 12 O 29The relationship between the number of Zr atoms at the Nb site and the band gap is compared with the case where the Nb site of Nb2O5 is replaced by Zr atoms.

[0027] Fig.14 To replace Ti9O 17 The relationship between the number of Zr atoms at the Ti site of TiO2 and the band gap is compared with the case where the Ti site of TiO2 is replaced by Zr atoms.

[0028] Fig.15 The diagram shows the results of actually manufacturing the semiconductor device (capacitor) according to the second embodiment and observing the characteristics.

[0029] Fig.16 It is a flowchart showing the manufacturing method of the semiconductor device of the third embodiment.

[0030] Fig.17 The present invention is a cross-sectional view showing a part of the steps of the method for manufacturing a semiconductor device according to the third embodiment.

[0031] Fig.18 The diagram shows the results of actually manufacturing the semiconductor device (capacitor) according to the third embodiment and observing the characteristics. DETAILED DESCRIPTION

[0032] Hereinafter, embodiments will be described with reference to the drawings.

[0033] <First Embodiment>

[0034] First, the first embodiment will be described.

[0035] Figure 1 is a flowchart showing a method for manufacturing a semiconductor device according to the first embodiment. Figure 2 This is a cross-sectional diagram of the process.

[0036] In this embodiment, first, the lower electrode 102 is formed on the substrate 101 (step ST1, Figure 2 (a)). The substrate 101 is not particularly limited, and a semiconductor substrate such as a Si substrate can be exemplified. The lower electrode 102 can be a TiN film. As the lower electrode 102, in addition to the TiN film, a TiSiN film, a TiAlN film, a TiMeN (Me: transition metal) film, a W film, a Mo film, or a Ru film can also be used. The lower electrode 102 can be formed by CVD, ALD, or PVD (sputtering).

[0037] Next, a high dielectric constant film (High-k film) 103 composed of an oxide containing tetravalent metal cations is formed on the lower electrode 102 as a capacitor film (step ST2, Figure 2(b)). The High-k film 103 composed of an oxide containing a tetravalent metal cation may be a ZrO2 film or a HfO2 film. The High-k film 103 may be formed by CVD, ALD, or PVD (sputtering). The film thickness of the High-k film 103 may be in the range of 2 to 10 nm.

[0038] Next, an oxide film 104 composed of an oxide containing pentavalent metal cations is formed on the High-k film 103 (step ST3, Figure 2 (c)). The oxide film 104 composed of an oxide containing pentavalent metal cations may be a Nb2O5 film, a Ta2O5 film, or a V2O5 film. The oxide film 104 may be formed by CVD, ALD, or PVD (sputtering). The film thickness of the oxide film 104 may be less than 1 nm.

[0039] Next, the High-k film 103 and the oxide film 104 react at the interface to form a conductive mixed layer 105 in which an oxide containing tetravalent metal cations and an oxide containing pentavalent metal cations are mixed (step ST4, Figure 2 (d)). The mixed layer 105 can be formed as a reaction layer during annealing for crystallization of the High-k film 103. For example, when the High-k film 103 is a ZrO2 film and the oxide film 104 is a Nb2O5 film, diffusion of Zr and Nb occurs by annealing to form NbZrO x As a conductive mixed layer 105. The annealing temperature at this time can be in the range of 250 to 600°C. In addition, the annealing time can be less than 120 minutes. The composition of the mixed layer 105 can be adjusted by the temperature and time during annealing, and by increasing the amount of Zr, it can become conductive.

[0040] Next, the upper electrode 106 is formed on the mixed layer 105 or the oxide film 104 (step ST5, Figure 2 (e)). The upper electrode 106 may be a TiN film. In addition to the TiN film, a TiSiN film, a TiAlN film, a TiMeN (Me: transition metal) film, a W film, a Mo film, or a Ru film may be used as the upper electrode 106. The upper electrode 106 may be formed by CVD, ALD, or PVD (sputtering).

[0041] After forming the upper electrode 106 , annealing is performed for the purpose of removing damage, etc., and the process is terminated. It should be noted that even if this annealing is performed, it is difficult to form a mixed layer between the upper electrode 106 and the mixed layer 105 due to atomic diffusion.

[0042] It should be noted that, in the present embodiment, the formation of the mixed layer 105 in step ST4 may be performed after the formation of the upper electrode 106 in step ST5 .

[0043] The semiconductor device manufactured as described above is used as a capacitor, typically a capacitor of a DRAM.

[0044] like Figure 2 As shown in (e), the semiconductor device manufactured by the method of this embodiment has: a lower electrode 102 formed on a substrate 101; a High-k film 103 formed on the lower electrode 102 and composed of an oxide containing a quadrivalent metal cation; a mixed layer 105 formed on the High-k film 103; and an upper electrode 106 formed thereon.

[0045] In this embodiment, the mixed layer 105 is composed of a combination of a tetravalent metal cation and a pentavalent metal cation, so as to generate defects for satisfying the charge neutrality condition as described later, it can become conductive. By forming a conductive mixed layer 105, the film thickness of the dielectric part becomes thinner accordingly, and the CET (Capacitance Equivalent Thickness; capacity conversion film thickness) can be reduced to increase the capacity. In addition, the presence of the mixed layer 105 can also reduce the leakage current.

[0046] The following is a detailed description.

[0047] Recently, the high integration and high speed of LSI have been further developed, and the design rules of semiconductor elements constituting LSI have become increasingly fine. As a result, the capacity of capacitors used in, for example, DRAM has tended to decrease, and there is a demand for an increase in the capacity of capacitors. In a capacitor in which a high-k film, i.e., a ZrO2 film, is provided as a single layer between TiN electrodes as a dielectric film as shown in Patent Document 1, the CET can be reduced and the capacitor capacity can be increased by thinning the ZrO2 film. However, when the ZrO2 film is thinned, the increase in leakage current becomes a problem, and it is difficult to achieve both high capacity and low leakage current by reducing CET. That is, as shown in Patent Document 1, Figure 3 As shown in FIG. 1 , until the ZrO2 film is about 3.5 nm, the relationship between CET and leakage current is roughly a linear relationship. In contrast, when the ZrO2 film thickness is thinner than 3 nm, for example, 2.5 nm, the leakage current increases compared to the straight line (trend line). In addition, a capacitor having multiple dielectric films is described in Patent Document 2, but it is not intended to take into account both high capacitance and low leakage current.

[0048] Therefore, in this embodiment, an oxide film 104 composed of an oxide containing a pentavalent metal cation, such as Nb2O5, is formed on a High-k film 103 composed of an oxide containing a tetravalent metal cation, such as a ZrO2 film. Then, by annealing, the High-k film 103 and the oxide film 104 react at the interface (atomic diffusion) to form a mixed layer 105 in which they are mixed. For example, when the High-k film 103 is a ZrO2 film and the oxide film 104 is Nb2O5, a mixed layer 105 containing NbZrO x A mixed layer 105 is provided.

[0049] Figure 4 In the case of a conventional capacitor having a structure in which a ZrO2 film 103' is provided as a dielectric film between a lower electrode 102' and an upper electrode 106' made of TiN, annealing after the formation of the upper electrode 106' also causes a reaction (atomic diffusion) between the upper electrode 106' and the ZrO2 film 103' to form a TiZrO2 film. x The mixed layer (interface layer) 105' is formed.

[0050] At this time, the mixed layer 105 ′ can be considered as a layer in which a part of the Ti site is substituted by Zr, and the defect structure formula at this time is represented by the following formula (1).

[0051]

[0052] Both Ti and Zr are tetravalent metal cations, and the site where Ti is replaced by Zr is a site where a tetravalent metal cation is replaced by a tetravalent metal cation, so that a charge neutrality condition can be maintained. Therefore, no electrical defects are formed. Figure 5 The distribution of density of states (DOS) obtained by calculation when five of the 16 Ti sites in TiO2 are replaced by Zr is shown in the figure. As shown in the figure, a band gap is formed in the DOS distribution. x The mixed layer 105' is insulating. It should be noted that in the figure, [up] and [down] are the directions of the spins, [up] means that the DOS is positive, and [down] means that the DOS is negative.

[0053] Figure 6 This is a graph showing the relationship between the number of Zr atoms at the sites of Ti substituted with TiO2 and the band gap. As shown in the graph, it is known that the band gap is not closed regardless of the number of Zr atoms substituted in TiO2, and it acts as an insulator. Therefore, by forming the mixed layer 105', the dielectric layer is increased accordingly.

[0054] That is, if the CET of the ZrO2 film is set to CET ZrO2 The mixed layer 105', i.e., TiZrO xThe CET is set to CET TiZrOx , then the overall CET of the capacitor is CET TZT Become CET as follows ZrO2 With CET TiZrOx The mixed layer 105' acts in the direction of increasing CET.

[0055] CET TZT =CET TiZrOx +CET ZrO2

[0056] In contrast, the mixed layer 105 of the present embodiment is a mixture of an oxide containing a pentavalent metal cation, such as Nb2O5, and an oxide containing a tetravalent metal cation, such as ZrO2, for example, NbZrO x When ZrO2, which is an oxide containing tetravalent metal cations, is added to Nb2O5, which is an oxide containing pentavalent metal cations, that is, when part of the Nb site is replaced by Zr, the defect structural formula is as shown in the following formula (2).

[0057]

[0058] When the site of Nb, which is a pentavalent metal cation, is replaced by Zr, which is a tetravalent metal cation, oxygen vacancies in the third term on the right side of the above formula (2) and negatively charged defects derived from Zr in the first term on the right side are generated to satisfy the charge neutrality condition, thereby achieving conductivity.

[0059] Figure 7 This is a diagram showing the distribution of the density of states (DOS) calculated when the number of substitutions of 24 Nb sites in Nb2O5 with Zr is 0 and 8. Figure 7 As shown, it was confirmed by calculation that when the Zr content was 8, energy levels derived from electron orbitals of oxygen and Zr were generated within the band gap of the DOS distribution, thereby achieving conductivity.

[0060] Figure 8 This is a graph showing the relationship between the number of Zr atoms at the Nb site substituted in Nb2O5 and the band gap. As shown in the figure, it can be seen that as the number of Zr atoms substituted in Nb2O5 increases, the band gap narrows, and when the number of Zr atoms substituted becomes 8 or more, the band gap closes and becomes a conductor.

[0061] That is, in this embodiment, the mixed layer 105 can be made conductive by increasing the number of substitutions of tetravalent metal cations (Zr in this example) in the mixed layer 105. In this embodiment, the conductive mixed layer 105 is formed by adjusting the heat treatment conditions during annealing.

[0062] The High-k film 103 is a ZrO2 film, and the mixed layer 105 is a NbZrO x In the case of ZrO2 film, if the CET is set to CET ZrO2 、NbZrO x The CET is set to CET NbZrOx , then the overall CET of the capacitor is CET TNZT Become CET as follows ZrO2 With CET NbZrOx sum.

[0063] CET TNZT =CET NbZrOx +CET ZrO2

[0064] Here, NbZrO x is conductive, so CET NbZrOx is approximately 0. Therefore, the film thickness of the dielectric film is thinner than that of the conventional ZrO2 film single film capacitor, and CET can be reduced. x The presence of the mixed layer 105 can prevent damage to the High-k film 103 when the upper electrode 106 is formed. That is, if there is no mixed layer 105, the High-k film 103 will be chemically damaged by Cl, NH3, etc. when the upper electrode 106 is formed by ALD, and will be physically damaged by plasma when the film is formed by PVD, but such damage is prevented by the presence of the mixed layer 105. Therefore, although CET is small, the increase in leakage current can be suppressed. Therefore, both high capacitance and low leakage current of the capacitor can be achieved.

[0065] The semiconductor device (capacitor) of this embodiment was actually manufactured and its characteristics were determined. Here, a ZrO2 film with a thickness of 4 nm and a Nb2O5 film with a thickness of 0.6 nm were formed on the lower electrode composed of a TiN film formed on a Si substrate, and then annealing was performed to form a NbZrO x A capacitor (sample 1) was manufactured by forming an upper electrode made of a TiN film on the capacitor. CET and leakage current of the capacitor of sample 1 were obtained. Fig. 9 As shown, it was confirmed that compared with the capacitor of the conventional structure using a single film of ZrO2 (Ref), the increase in leakage current can be suppressed and CET can be reduced by about 15%, and the characteristics are improved compared with the trend line of the single film of ZrO2.

[0066] <Second Embodiment>

[0067] Next, a second embodiment will be described.

[0068] Fig.102 is a flowchart showing a method for manufacturing a semiconductor device according to a second embodiment. Fig.11 It is a process cross-sectional view showing a part of the process.

[0069] In this embodiment, steps ST11 to ST13 are performed which are the same as steps ST1 to ST3 of the first embodiment. That is, a lower electrode 102 is formed on a substrate 101 (step ST11), a high dielectric constant film (High-k film) 103 composed of an oxide containing a tetravalent metal cation is formed as a capacity film (step ST12), and an oxide film 104 composed of an oxide containing a pentavalent metal cation is formed on the High-k film 103 (step ST13).

[0070] Next, similarly to step ST4 of the first embodiment, during annealing for crystallization of the High-k film 103, for example, the High-k film 103 and the oxide film 104 react at the interface to form a conductive mixed layer 105 in which an oxide containing a tetravalent metal cation and an oxide containing a pentavalent metal cation are mixed (step ST14, Fig.11 (a)).

[0071] Next, an oxygen extraction layer 108 for extracting oxygen is formed on the mixed layer 105 (step ST15, Fig.11 (b)). At this time, if Fig.11 As shown in (b), the oxygen extraction layer 108 is formed by means of a barrier film 107 composed of a TiN film, for example. A metal film composed of an active metal such as TiAl can be used as the oxygen extraction layer 108. In addition to TiAl, Ti, Al, etc. can also be used as the oxygen extraction layer 108.

[0072] Next, similarly to step ST5 of the first embodiment, an upper electrode 106 made of, for example, a TiN film is formed on the oxygen extraction layer 108 (step ST16, Fig.11 (c)).

[0073] Next, heat treatment is performed in a reducing atmosphere (step ST17, Fig.11 (d)). As a result, oxygen is extracted from the lower mixed layer 105 to the oxygen extraction layer 108, forming a mixed layer 105a with oxygen vacancies. The heat treatment at this time can be carried out under the conditions of an atmosphere containing H2 (hydrogen concentration: 1 to 100%, for example 4%), a temperature of 350 to 600°C, for example 400°C, and a time of less than 120 minutes, for example 10 minutes.

[0074] The formation of the oxygen extraction layer 108 in step ST15 and the heat treatment in a reducing atmosphere in step ST17 constitute a reduction treatment process.

[0075] After step ST17, annealing is further performed as necessary, and the process is terminated.

[0076] It should be noted that in this embodiment, the formation of the mixed layer 105 in step ST14 may be performed during step ST17 or during annealing after step ST17. When step ST14 is performed during annealing after step ST17, the oxygen extraction (reduction treatment) in ST17 is performed on the oxide film 104.

[0077] In this embodiment, the semiconductor device manufactured as described above is also used as a capacitor, typically a capacitor of a DRAM.

[0078] In this embodiment, the mixed layer 105 composed of a combination of 4-valent metal cations and 5-valent metal cations and generating defects for satisfying the charge neutrality condition is subjected to oxygen extraction as a reduction treatment to generate oxygen vacancies, thereby forming a mixed layer 105a in which oxygen vacancies are generated. Therefore, the mixed layer 105a is more conductive than the mixed layer 105 due to the presence of oxygen vacancies, and the conductivity can be improved. Therefore, compared with the first embodiment, the effect of reducing CET can be improved. In addition, by the presence of the mixed layer 105a, not only can the damage to the High-k film 103 be prevented during the formation of the upper electrode 106 as described above, but also the damage to the High-k film 103 during the reduction treatment can be prevented, and the increase in leakage current can be suppressed.

[0079] The following is a detailed description.

[0080] As described above, the mixed layer 105 formed by mixing an oxide containing a pentavalent metal cation, such as Nb2O5, and an oxide containing a tetravalent metal cation, such as ZrO2, generates oxygen vacancies and negatively charged defects derived from Zr, and can become conductive. In addition, the mixed layer 105a in which oxygen vacancies are increased by extracting oxygen from the mixed layer 105 is more likely to become conductive.

[0081] Fig.12 represents the Nb2O5 oxygen vacancy formed relative to Nb 12 O 29 The distribution of the density of states (DOS) calculated when the number of substitutions of 28 Nb sites to Zr is 4 is shown in FIG. Fig.12 As shown in the figure, it is confirmed that the Nb2O5 with respect to the formation of oxygen vacancies 12 O 29 In the case of , even if the number of Zr substitutions is as small as 4, energy levels derived from the electron orbits of oxygen and Zr are generated within the band gap of the DOS distribution, resulting in conductivity.

[0082] Fig.13 To replace Nb 12 O29 The relationship between the number of Zr atoms at the Nb site and the band gap is shown in the figure compared with the case where the Nb site of Nb2O5 is replaced by Zr atoms. As shown in the figure, it can be seen that in the case of Nb forming oxygen vacancies with respect to Nb2O5, 12 O 29 In the case of Nb2O5, the band gap is sharply narrowed by the substitution of Zr atoms compared with that of Nb2O5. When the number of Zr atoms substituted is 4 or more, the band gap is closed and the material becomes a conductor.

[0083] That is, in this embodiment, the mixed layer 105a in which oxygen vacancies are increased by subjecting the mixed layer 105 to oxygen extraction treatment as a reduction treatment is more likely to become conductive than the mixed layer 105. Therefore, the CET can be further reduced compared with the first embodiment.

[0084] It should be noted that in the above Figure 4 In the case of a conventional capacitor in which the oxide film 104 composed of an oxide containing pentavalent metal cations is not formed as shown, even if oxygen vacancies are generated by reduction treatment after the mixed layer (interface layer) 105' is formed, it remains an insulator. Fig.14 This is explained. Fig.14 To replace Ti9O 17 The relationship between the number of Zr atoms at the Ti site and the band gap is shown in the figure compared with the case where the Ti site of TiO2 is replaced by Zr atoms. 17 Similar to TiO2, the band gap is not closed regardless of the number of Zr atoms substituted, and the material acts as an insulator.

[0085] The semiconductor device (capacitor) of this embodiment was actually manufactured and its characteristics were understood. Here, a ZrO2 film with a thickness of 4 nm and a Nb2O5 film with a thickness of 0.6 nm were formed on a lower electrode composed of a TiN film formed on a Si substrate, and then annealing was performed to form a NbZrOx film. Then, a 3 nm TiN film and a 3 nm TiAl film were formed thereon, and then an upper electrode composed of a TiN film was formed, and then a heat treatment at 400°C was performed in a reducing atmosphere to manufacture a capacitor (sample 2). CET and leakage current were calculated for the capacitor of sample 2. As a result, Fig.15 As shown, it was confirmed that the increase in leakage current can be suppressed to less than two digits and CET can be reduced by about 35% compared to the trend line of single-film ZrO2 capacitors (Ref). In addition, Fig.15 The results of Sample 1 of the first embodiment are also described in FIG. 1 , and it is found that Sample 2 has a higher CET lowering effect than Sample 1.

[0086] <Third Embodiment>

[0087] Next, a third embodiment will be described.

[0088] Fig.16 2 is a flowchart showing a method for manufacturing a semiconductor device according to a third embodiment. Fig.17 It is a process cross-sectional view showing a part of the process.

[0089] In this embodiment, steps ST21 to ST23 are performed which are the same as steps ST1 to ST3 of the first embodiment. That is, a lower electrode 102 is formed on a substrate 101 (step ST21), a high dielectric constant film (High-k film) 103 composed of an oxide containing a tetravalent metal cation is formed as a capacity film (step ST22), and an oxide film 104 composed of an oxide containing a pentavalent metal cation is formed on the High-k film 103 (step ST23).

[0090] Next, similarly to step ST4 of the first embodiment, during annealing for crystallization of the High-k film 103, for example, the High-k film 103 and the oxide film 104 react at the interface to form a conductive mixed layer 105 in which an oxide containing a tetravalent metal cation and an oxide containing a pentavalent metal cation are mixed (step ST24, Fig.17 (a)).

[0091] Next, the restoration process is performed (step ST25, Fig.17 (b)). Thus, the mixed layer 105 is reduced to form a mixed layer 105b in which oxygen vacancies are generated. The reduction treatment can be performed by heat treatment in a reducing atmosphere, a hydrogen (H2 gas) atmosphere or a deuterium (D2 gas) atmosphere, for example, at a temperature of 250 to 600° C. and a time of 60 minutes or less. Alternatively, the reduction treatment can be performed using H2 plasma.

[0092] Next, similarly to step ST5 of the first embodiment, an upper electrode 106 made of, for example, a TiN film is formed on the mixed layer 105b (step ST26, Fig.17 (c)).

[0093] After step ST26, annealing is further performed as necessary, and the process is terminated.

[0094] It should be noted that in this embodiment, the formation of the mixed layer 105 in step ST24 may be performed during step ST26 or during annealing after step ST26. When step ST24 is performed during annealing after step ST26, oxygen vacancies are generated in the oxide film 104 during the reduction treatment in step ST25.

[0095] In this embodiment, the semiconductor device manufactured as described above is also used as a capacitor, typically a capacitor of a DRAM.

[0096] In this embodiment, similarly to the second embodiment, a reduction treatment is performed on the mixed layer 105 composed of a combination of 4-valent metal cations and 5-valent metal cations and generating defects for satisfying the charge neutrality condition, thereby forming a mixed layer 105b having oxygen vacancies relative to the mixed layer 105. Therefore, the mixed layer 105b is more conductive than the mixed layer 105 due to the presence of oxygen vacancies, and the conductivity can be improved. Therefore, compared with the first embodiment, the effect of reducing CET can be improved. In addition, through the mixed layer 105b, similarly to the mixed layer 105a of the second embodiment, not only can damage to the High-k film 103 be prevented during the formation of the upper electrode 106, but also damage to the High-k film 103 during the reduction treatment can be prevented, and the increase in leakage current can be suppressed.

[0097] The semiconductor device (capacitor) of this embodiment was actually manufactured and its characteristics were understood. Here, a ZrO2 film with a thickness of 4 nm and a Nb2O5 film with a thickness of 0.6 nm were formed on a lower electrode composed of a TiN film formed on a Si substrate, and then annealing was performed to form a NbZrOx film. Then, a reduction treatment was performed at 541°C in an H2 gas atmosphere, and an upper electrode composed of a TiN film was formed thereon to manufacture a capacitor (sample 3). A capacitor (sample 4) was also manufactured under the same conditions as sample 3, except that the reduction treatment was set to a D2 gas atmosphere. CET and leakage current were calculated for the capacitor. As a result, Fig.18 As shown, it was confirmed that compared with the capacitor of the existing structure using a single film of ZrO2 (Ref), the increase in leakage current can be suppressed to less than two digits, and CET can be reduced by about 30%, and the characteristics are improved compared with the trend line of the single film of ZrO2.

[0098] <Other Applications>

[0099] Although the embodiments have been described above, it should be understood that the embodiments disclosed this time are illustrative in all aspects and not restrictive. The above embodiments may be omitted, replaced, or modified in various ways without departing from the appended claims and the gist thereof.

[0100] Description of Reference Numerals

[0101] 101: substrate, 102: lower electrode, 103: High-k film composed of oxide containing tetravalent metal cations, 104: oxide film composed of oxide containing pentavalent metal cations, 105, 105a, 105b: mixed layer, 106: upper electrode, 107: TiN film, 108: oxygen extraction layer.

Claims

1. A method for manufacturing a semiconductor device, comprising the following steps: forming a lower electrode on a substrate; forming a high dielectric constant film composed of an oxide containing a tetravalent metal cation on the lower electrode; forming an oxide film composed of an oxide containing pentavalent metal cations on the high dielectric constant film; forming a mixed layer having conductivity in which the oxide containing tetravalent metal cations and the oxide containing pentavalent metal cations are mixed by reacting the high dielectric constant film with the oxide film; and An upper electrode is formed.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The high dielectric constant film composed of an oxide containing tetravalent metal cations is any one of a ZrO 2 film and a HfO 2 film.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: The oxide film composed of an oxide containing pentavalent metal cations is any one of a Nb2O5 film, a V2O5 film, and a Ta2O5 film.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The high dielectric constant film composed of an oxide containing tetravalent metal cations is a ZrO2 film, and the oxide film composed of an oxide containing pentavalent metal cations is a Nb2O5 film.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: The upper electrode and the lower electrode are formed of a TiN film. 6 . The method for manufacturing a semiconductor device according to claim 1 , further comprising the step of performing a reduction treatment at least after forming the oxide film.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: The reduction treatment is a step of forming an oxygen extraction layer on the mixed layer or the oxide film, and then extracting oxygen from the mixed layer or the oxide film to the oxygen extraction layer through heat treatment in a reducing atmosphere.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The heat treatment in the reducing atmosphere is performed after forming the upper electrode.

9. The method for manufacturing a semiconductor device according to claim 7, wherein: Oxygen vacancies are generated in the mixed layer by extracting oxygen into the oxygen extraction layer.

10. The method for manufacturing a semiconductor device according to claim 6, wherein: The reduction treatment is performed by heat treatment in a hydrogen atmosphere or a deuterium atmosphere.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: Oxygen vacancies are generated in the mixed layer through the heat treatment in the hydrogen atmosphere or the deuterium atmosphere.

12. The method for manufacturing a semiconductor device according to claim 10, wherein: The reduction treatment is performed before forming the upper electrode.

13. The method for manufacturing a semiconductor device according to any one of claims 1 to 5, wherein: The oxide film has a thickness of 1 nm or less.

14. The method for manufacturing a semiconductor device according to any one of claims 1 to 5, wherein: The semiconductor device is a capacitor of a DRAM.

15. A semiconductor device comprising: substrate; a lower electrode formed on the substrate; a high dielectric constant film composed of an oxide containing tetravalent metal cations formed on the lower electrode; a conductive mixed layer formed on the high dielectric constant film and formed by mixing the oxide containing tetravalent metal cations and the oxide containing pentavalent metal cations; as well as An upper electrode is formed on the mixed layer.

16. The semiconductor device according to claim 15, wherein The mixed layer has oxygen vacancies.

17. The semiconductor device according to claim 15 or 16, which is used as a capacitor of a DRAM.

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