Semiconductor device, chip and preparation method thereof, and storage system

Abstract

The invention provides a semiconductor device, a chip, a preparation method of the chip and a storage system, the semiconductor device comprises a plurality of cutting channels, a plurality of bare chips and a bare chip test structure, and the plurality of bare chips are defined by the plurality of cutting channels in a crossing manner. The cutting channels comprise at least one first cutting channel, a plurality of second cutting channels and a third cutting channel, the first cutting channels and the second cutting channels are arranged in parallel, and the third cutting channel, the first cutting channels and the second cutting channels are arranged in a crossed mode.

Description

Semiconductor device, chip, manufacturing method thereof, and storage system Technical Field

[0001] The present disclosure generally relates to electronic devices, and more particularly, to a semiconductor device, a chip, a method for manufacturing the same, and a storage system. Background Art

[0002] NAND memory devices are non-volatile storage products with low power consumption, lightweight, and high performance, and are widely used in electronic products. Planar NAND devices have reached their practical scalability limits. To further increase storage capacity and reduce the cost per bit, 3D NAND memory has been proposed. In a 3D NAND memory structure, multiple layers of data storage cells are stacked vertically to create a stacked memory architecture.

[0003] As the number of stacked layers increases, the cutting process of the saw streets has a greater impact on the strength of the device. Technical Solutions

[0004] The present disclosure aims to provide a semiconductor device and a method for manufacturing the same, aiming to reduce the impact of cutting streets on device strength.

[0005] In a first aspect, the present disclosure provides a semiconductor device, comprising:

[0006] A plurality of cutting lanes, including at least one first cutting lane, a plurality of second cutting lanes and a third cutting lane, wherein the first cutting lane and the second cutting lane are arranged parallel to each other, and the third cutting lane is arranged to intersect with the first cutting lane and the second cutting lane;

[0007] a plurality of dies, wherein the plurality of dicing lanes intersect to define the plurality of dies;

[0008] The bare die test structure is located only in the first dicing lanes, and any one of the first dicing lanes is adjacent to at least one of the second dicing lanes.

[0009] In some embodiments, at least three second cutting streets are arranged between two adjacent first cutting streets.

[0010] In some embodiments, the number of the second cutting streets spaced between two adjacent first cutting streets is equal.

[0011] In some embodiments, the scribe line includes alternately stacked first and second dielectric layers, the die test structure penetrates the scribe line along a stacking direction of the scribe line, and includes alternately stacked third dielectric layers and conductive layers along the stacking direction.

[0012] In some embodiments, the thickness of the die test structure is less than or equal to the thickness of the scribe line.

[0013] In some embodiments, the die test structures having the same thickness are located in the same first scribe line.

[0014] In some embodiments, the semiconductor device further comprises:

[0015] semiconductor layer;

[0016] a stacking layer, located on the semiconductor layer, and comprising the third dielectric layer and the conductive layer alternately stacked along the stacking direction;

[0017] The dicing streets and the bare die test structure are located on the semiconductor layer.

[0018] In some embodiments, the die includes a memory device and a peripheral circuit bonded to each other, and the die test structure is used for electrical testing of the memory device, the peripheral circuit, or the bonding surface between the memory device and the peripheral device.

[0019] In some embodiments, the plurality of dicing streets and the plurality of dies form a repeating unit, the repeating unit includes at least one first dicing street; and the semiconductor device includes a plurality of the repeating units.

[0020] In a second aspect, the present disclosure provides a chip prepared from the semiconductor device in any of the above embodiments, wherein the chip includes a first cutting surface and a second cutting surface, wherein the second cutting surface is located at the periphery of the first cutting surface, and the height of the second cutting surface is less than the height of the first cutting surface.

[0021] In a third aspect, the present disclosure provides a storage system, comprising:

[0022] The chip provided by the above embodiment;

[0023] A controller is electrically connected to the chip and is used to control the chip to store data.

[0024] In a fourth aspect, the present disclosure provides a method for preparing a chip, the method for preparing a semiconductor device comprising:

[0025] A semiconductor device is provided, wherein a plurality of dicing lanes are provided in the semiconductor device, wherein the dicing lanes include a first dicing lane, a second dicing lane, and a third dicing lane, wherein the first dicing lane and the second dicing lane are arranged parallel to each other, the third dicing lane is arranged to intersect with the first dicing lane and the second dicing lane, and a bare die test structure is provided in the first dicing lane;

[0026] The semiconductor device is cut into a plurality of chips along the first dicing street, the second dicing street, and the third dicing street.

[0027] In some embodiments, the step of cutting the semiconductor device into a plurality of chips along the first dicing street, the second dicing street, and the third dicing street includes:

[0028] The semiconductor device is cut twice using two different cutting processes.

[0029] In some embodiments, the step of cutting the semiconductor device into a plurality of chips along the first dicing street, the second dicing street, and the third dicing street includes:

[0030] Using a first laser to form a first groove in the first scribe line to remove a portion of the bare die test structure, wherein a depth of the first groove is less than a thickness of the first scribe line;

[0031] The second dicing street, the third dicing street, and the first dicing street below the first slot are mechanically cut to form a plurality of chips.

[0032] In some embodiments, before the step of using a blade to cut the first scribe line, the second scribe line, and the third scribe line below the first slot, the chip preparation method further includes:

[0033] Using a second laser to form a second groove in the second cutting street and a third groove in the third cutting street, the depth of the second groove is less than the thickness of the second cutting street, and the depth of the third groove is less than the thickness of the third cutting street;

[0034] The step of mechanically cutting the second cutting street, the third cutting street and the first cutting street below the first slot includes: using a blade to cut the first cutting street below the first slot, the second cutting street below the second slot and the third cutting street below the third slot.

[0035] In some embodiments, the energy of the second laser is less than the energy of the first laser.

[0036] The present disclosure provides a semiconductor device, a chip, a method for manufacturing the same, and a storage system. The semiconductor device includes multiple cutting lanes, multiple bare dies, and a bare die test structure. The multiple bare dies are defined by the intersection of the multiple cutting lanes. The multiple cutting lanes include at least one first cutting lane, multiple second cutting lanes, and a third cutting lane. The first cutting lane and the second cutting lane are arranged parallel to each other, and the third cutting lane is arranged to intersect with the first cutting lane and the second cutting lane. The bare die test structure is only located in the first cutting lane, and any first cutting lane is arranged adjacent to at least one of the second cutting lanes. By concentrating the bare die test structure in the first cutting lane and not in the second cutting lane and the third cutting lane, different laser cutting conditions can be used for the cutting lanes with the bare die test structure and the cutting lanes without the bare die test structure during the cutting process, so that the laser cutting depth of the second cutting lane and the third cutting lane is reduced, thereby improving the strength of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The technical solutions and other beneficial effects of the present disclosure will be made apparent by describing the specific embodiments of the present disclosure in detail below in conjunction with the accompanying drawings.

[0038] FIG1 is a schematic structural diagram of a semiconductor device provided by some embodiments of the present disclosure;

[0039] FIG2 is a schematic structural diagram of a semiconductor device provided by some embodiments of the present disclosure;

[0040] FIG3 is a schematic diagram of a cross-sectional structure of the semiconductor device taken along line A-A1 in FIG1 according to some embodiments of the present disclosure;

[0041] FIG4 is a schematic flow chart of a chip preparation method according to some embodiments of the present disclosure;

[0042] 5a-5c are schematic structural diagrams of a chip during the preparation process provided by some embodiments of the present disclosure;

[0043] FIG6 is a schematic diagram of the structure of a storage system provided by some embodiments of the present disclosure. DETAILED DESCRIPTION

[0044] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of them. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present disclosure.

[0045] It should be understood that although the terms first, second, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another. For example, a first component can be referred to as a second component, and similarly, a second component can be referred to as a first component without departing from the scope of this disclosure.

[0046] It should be understood that when a component is said to be "on" or "connected" to another component, it can be directly on or connected to the other component, or there may be intervening components. Other words used to describe the relationship between components should be interpreted in a similar manner.

[0047] As used herein, the term "layer" refers to a portion of a material including an area with a thickness. A layer may extend over the entire underlying or superstructure, or may have a range that is smaller than the range of the underlying or superstructure. In addition, a layer may be an area of ​​a uniform or non-uniform continuous structure having a thickness that is less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and a contact layer (wherein contacts, interconnect lines, and / or vertical interconnect access (VIA) are formed) and one or more dielectric layers.

[0048] It should be noted that the illustrations provided in the embodiments of the present disclosure are only used to schematically illustrate the basic concept of the present disclosure. Although the illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed at will, and the component layout may also be more complicated.

[0049] Please refer to Figure 1, which is a schematic diagram of the structure of a semiconductor device provided by some embodiments of the present disclosure. The semiconductor device 100 may be a wafer, which, after dicing, can be formed into multiple chips, such as a three-dimensional memory. Three-dimensional memory can be applied to communications products, consumer electronics, automotive products, aerospace products, artificial intelligence products, or big data. Consumer electronics products include, but are not limited to, mobile phones, computers, tablets, cameras, smart glasses, and gaming products.

[0050] The semiconductor device 100 includes a plurality of dicing lanes 10, a plurality of dies 20, and a die test structure 30. The plurality of dicing lanes 10 are defined by the intersection of the plurality of dicing lanes 10. The plurality of dicing lanes 10 include at least one first dicing lane 11, a plurality of second dicing lanes 12, and a third dicing lane 13. The first dicing lane 11 and the second dicing lane 12 are arranged parallel to each other, and the third dicing lane 13 is arranged to intersect with the first dicing lane 11 and the second dicing lane 12. For example, the first dicing lane 11 and the second dicing lane 12 can both be arranged along the X direction, and the third dicing lane 13 can be arranged along the Y direction. The first dicing lane 11, the second dicing lane 12, and the third dicing lane 13 intersect to define a plurality of dicing lanes 20, that is, the dicing lanes 20 are located in the area defined by the intersection of the plurality of dicing lanes 10, for example, one dicing lane 20 is arranged in one of the areas. Moreover, a dicing lane 20 referred to here may include an integrated circuit block defined by the dicing lanes on the wafer but not separated.

[0051] The die test structures 30 are located only within the first scribe lanes 11, and any first scribe lane 11 is adjacent to at least one of the second scribe lanes 12. That is, the die test structures 30 are concentrated within the first scribe lanes 11, while the die test structures 30 are not located within the second scribe lanes 12 and the third scribe lanes 13. Furthermore, each first scribe lane 11 is adjacent to a second scribe lane 12. For example, each first scribe lane 11 may be adjacent to one, two, or more second scribe lanes 12. In other words, the scribe lanes with the die test structures 30 are referred to as the first scribe lanes 11, while the scribe lanes extending in the same direction as the first scribe lanes 11 but not adjacent to the die test structures 30 are referred to as the second scribe lanes 12. Specifically, each first scribe lane 11 may have one, two, or more second scribe lanes 12 located adjacent to one side (one side along the Y direction), or each first scribe lane 11 may have second scribe lanes 12 located adjacent to both sides (both sides along the Y direction). The number of second scribe lanes 12 on either side may be equal or unequal.

[0052] In some specific embodiments, the first cutting lanes 11 and the second cutting lanes 12 can be arranged alternately, so that any first cutting lane 11 is located between two second cutting lanes 12, that is, the first cutting lane 11 is adjacent to the two second cutting lanes 12, or it can be said that any first cutting lane 11 is adjacent to a second cutting lane 12 on both sides.

[0053] In some embodiments, at least three second cutting streets 12 may be provided between two adjacent first cutting streets 11. As shown in FIG1 , any first cutting street 11 is adjacent to five second cutting streets 12, and five second cutting streets 12 are provided between two adjacent first cutting streets 11.

[0054] In some embodiments, multiple scribe lines 10 and multiple dies 20 may form a repeating unit C of mask exposure. "Mask exposure" refers to a process of patterning underlying structures using a mask, including a photolithography process. The repeating unit C includes at least one first scribe line 11, and the semiconductor device 100 includes multiple repeating units C.

[0055] Figure 1 shows a repeating unit C, meaning that the integrated circuit pattern in semiconductor device 100 is formed by repeating this repeating unit C along the X and / or Y directions. It should be understood that a first scribe line 11 is also provided below the bottommost die 20 in Figure 1 , but this first scribe line 11 belongs to another repeating unit. Alternatively, the first scribe line 11 at the bottom of Figure 1 belongs to this repeating unit C, while the first scribe line 11 at the top of Figure 1 belongs to another repeating unit. A repeating unit C can be formed by a single reticle, and a single reticle can be used to form multiple dies 20, as shown in Figure 1 .

[0056] As shown in FIG1 , a repeating unit C may include one first cutting lane 11 and five second cutting lanes 12. The first cutting lane 11 may be disposed on one side of the five second cutting lanes 12. In other embodiments, the first cutting lane 11 may also be disposed between any two second cutting lanes 12. It should be noted that the specific number of cutting lanes 10 in the present disclosure is only an example, and the present disclosure does not limit the specific number of cutting lanes 10, first cutting lanes 11, and second cutting lanes 12.

[0057] Please refer to Figure 2, which is a schematic diagram of the structure of a semiconductor device provided by some embodiments of the present disclosure. In Figure 2, semiconductor device 200 shows a repeating unit C1, which includes two first scribe lines 11 and four second scribe lines 12. That is, if there are a large number of bare die test structures 30, the bare die test structures 30 can be concentrated in the two first scribe lines 11.

[0058] In some embodiments, when the number of die test structures 30 is large, the die test structures 30 may be concentrated and distributed in two or more first scribe lines 11 .

[0059] In some embodiments, the number of second scribe lines 12 between two adjacent first scribe lines 11 is equal, which can ensure that the die test structure 30 is more evenly distributed and thus average stress. For example, two second scribe lines 12 can be spaced between two adjacent first scribe lines 11.

[0060] Please refer to FIG. 3 , which is a schematic diagram of the cross-sectional structure of the semiconductor device along A-A1 in FIG. 1 provided by some embodiments of the present disclosure.

[0061] The cutting line 10 may include a first dielectric layer 101 and a second dielectric layer 102 alternately stacked, the bare chip test structure 30 passes through the cutting line 10 along the stacking direction (Z) of the cutting line 10, and may include a third dielectric layer 301 and a conductive layer 302 alternately stacked along the stacking direction (Z).

[0062] The materials of the first dielectric layer 101 and the second dielectric layer 102 may include, but are not limited to, silicon oxide, silicon nitride, or silicon oxynitride, and the materials of the first dielectric layer 101 and the second dielectric layer 102 are different. The materials of the third dielectric layer 301 include, but are not limited to, silicon oxide, silicon nitride, or silicon oxynitride, with silicon oxide being an exemplary material. The third dielectric layer 301 may be made of the same material as the first dielectric layer 101 or the second dielectric layer 102. For example, the third dielectric layer 301 and the first dielectric layer 101 may both be made of silicon oxide and disposed in the same layer, and the conductive layer 302 and the second dielectric layer 102 may be disposed in the same layer; or the third dielectric layer 301 and the second dielectric layer 102 may both be made of silicon oxide and disposed in the same layer, and the conductive layer 302 and the first dielectric layer 101 may be disposed in the same layer.

[0063] The conductive layer 302 may include one or more conductive materials, such as tungsten, titanium carbide, polysilicon, etc. The conductive layer 302 may also include a high-K dielectric material, such as aluminum oxide.

[0064] The semiconductor device 100 may further include a semiconductor layer 40 and a stacked layer 50 located on the semiconductor layer 40. The stacked layer 50 includes a third dielectric layer 301 and a conductive layer 302 alternately stacked along the stacking direction (Z). The scribe line 10 and the die test structure 30 are located on the semiconductor layer 40. The die 20 may include the stacked layer 50 and a plurality of channel structures 51. The die 20 (or the stacked layer 50) is adjacent to the first scribe line 11 and the second scribe line 12.

[0065] In some embodiments, the thickness of the scribe line 10 may be equal to the thickness of the stacked layer 50. It is understood that the "thickness" in the present disclosure refers to the thickness along the Z direction.

[0066] In some embodiments, the thickness of the die test structure 30 is less than or equal to the thickness of the scribe line 10 .

[0067] In some embodiments, the thickness of all the die test structures 30 is smaller than the thickness of the scribe line 10 , or the thickness of all the die test structures 30 is equal to the thickness of the scribe line 10 .

[0068] In some embodiments, a portion of the die test structure 30 has a thickness less than the thickness of the scribe line 10 , while another portion of the die test structure 30 has a thickness equal to the thickness of the scribe line 10 .

[0069] The bare die 20 may also include a memory device and a peripheral circuit (not shown) bonded to each other. The bare die 20 may be a memory (NAND) chip, and the peripheral circuit may be a CMOS (Complementary Metal Oxide Semiconductor). The peripheral circuit is electrically connected to the memory device to transmit signals to the memory device. The peripheral circuit can be used for logical operations and to control and detect the switching state of each memory cell in the memory device through metal wiring to achieve data storage and reading.

[0070] The bare die test structure 30 can be used to test the electrical properties of the memory device, peripheral circuits, or the bonding surfaces between the memory device and peripheral devices. For example, the bare die test structure 30 can be used to test the electrical properties of memory cells in the memory device, the electrical properties of transistors in the peripheral circuits, and the electrical connection of the bonding surfaces.

[0071] In some embodiments, the semiconductor device 100 may be cut along the first dicing street 11, the second dicing street 12, and the third dicing street 13 to separate the plurality of dies 20 into a plurality of chips. The cutting process may include laser cutting and mechanical cutting.

[0072] The inventors have discovered that as the number of stacked layers 50 increases, the number of conductive layers 302 in the die test structure 30 increases, meaning the die test structure 30 becomes thicker. If the die test structures 30 are scattered throughout the first and second scribe lines 11 and 12, and possibly also within the third scribe line 13, for example, if only one or two die test structures 30 are provided within a scribe line 10, then the materials of the scribe line 10 at locations with and without die test structures 30 are different. When laser scanning and cutting is performed along the scribe line 10, because the laser output power is difficult to adjust during scanning and cutting of the same scribe line 10, different cutting depths are formed at different locations. Specifically, the cutting depth at locations without die test structures 30 is deeper than the cutting depth at locations with die test structures 30. Excessively deep laser cutting can cause a decrease in device strength.

[0073] In the semiconductor device provided by the embodiment of the present disclosure, the bare die test structure 30 is concentrated in the first cutting lane 11, and the bare die test structure 30 is not provided in the second cutting lane 12 and the third cutting lane 13. Therefore, different laser settings can be used to process the first cutting lane 11 during laser cutting. For example, the laser energy used in the second cutting lane 12 and the third cutting lane 13 is adjusted to be less than the laser energy used in the first cutting lane 11 (even 0), so that the consistency of the laser cutting depth of the cutting lane 10 is better. In other words, for the second cutting lane 12 and the third cutting lane 13 without the bare die test structure 30, the laser cutting depth thereof can be reduced, thereby improving the reduction in device strength caused by laser cutting. Furthermore, during the chip packaging process, it can withstand greater bending forces, reducing the risk of chip breakage.

[0074] In some embodiments, the bare chip test structure 30 is set in the first cutting street 11 and is not set at the intersection of the first cutting street 11 and the third cutting street 13. In this way, different cutting conditions can be used for the first cutting street 11 and the third cutting street 13, making the cutting depth more consistent.

[0075] In some embodiments, die test structures 30 of the same thickness may be disposed in the same first scribe line 11 . For example, a thicker die test structure 30 may be disposed in one first scribe line 11 , and a thinner die test structure 30 may be disposed in another first scribe line 11 .

[0076] Compared to the first scribe lines 11 for the thicker die test structures 30, adjusting the laser cutting conditions for the first scribe lines 11 for the thinner die test structures 30 to achieve lower laser energy can improve the consistency of the cutting depths of the two. Furthermore, the cutting depth of the first scribe lines 11 for the thinner die test structures 30 can be reduced, thereby improving the strength of the device.

[0077] Please refer to Figure 4, which is a schematic flow diagram of a chip manufacturing method provided by some embodiments of the present disclosure. Please also refer to Figures 5a-5c, which are schematic diagrams of the structure of a chip provided by some embodiments of the present disclosure during the manufacturing process. The chip is cut from the semiconductor device 100 described above, so reference can be made to Figures 1 and 3. The chip manufacturing process may include the following steps S1-S2.

[0078] Step S1: Provide a semiconductor device, in which a plurality of cutting lanes 10 are provided, wherein the cutting lanes 10 include a first cutting lane 11, a second cutting lane 12 and a third cutting lane 13, wherein the first cutting lane 11 and the second cutting lane 12 are arranged parallel to each other, and the third cutting lane 13 is arranged to cross the first cutting lane 11 and the second cutting lane 12, and a bare chip test structure 30 is provided in the first cutting lane 11.

[0079] 1 , in a repeating unit C, the die test structures 30 are concentrated in a first scribe line 11. As shown in FIG5a , the die 20 is located between two first scribe lines 11 or between a first scribe line 11 and a second scribe line 12.

[0080] Step S2 : cutting the semiconductor device into a plurality of chips 60 along the first dicing street 11 , the second dicing street 12 and the third dicing street 13 .

[0081] In some embodiments, the semiconductor device can be cut twice using two different cutting processes. For example, laser cutting can be used to form a groove on the front side of the device, and then a machine (e.g., a blade) can be used to completely cut the semiconductor device. Using laser cutting first can make the cut edge of the device front side smoother, thereby improving the quality of the front side of the chip 60.

[0082] As shown in FIG5b, a first laser can be used to form a first slot 110 in the first cutting street 11 to remove part of the bare die test structure 30. The depth of the first slot 110 is less than the thickness of the first cutting street 11. As shown in FIG5c, the second cutting street 12, the third cutting street 13, and the first cutting street 11 below the first slot 110 are then mechanically cut to form a plurality of chips 60. In other words, the first cutting street 11 can be first cut by laser cutting to form a slot, while the second cutting street 12 and the third cutting street 13 are not cut by laser. Then, the first cutting street 11, the second cutting street 12, and the third cutting street 13 are mechanically cut once to cut the semiconductor device into a plurality of chips 60. Therefore, this cutting method can realize local laser cutting, achieving low cost and high output.

[0083] In some embodiments, before performing the above-mentioned mechanical cutting, a second laser can be used to form a second groove 120 in the second cutting street 12 and a third groove (not shown in the figure) in the third cutting street 13. The depth of the second groove 120 is less than the thickness of the second cutting street 12, and the depth of the third groove is less than the thickness of the third cutting street 13.

[0084] Among them, since there is no bare chip test structure 30 in the second cutting lane 12 and the third cutting lane 13, the energy of the second laser is set to be less than the energy of the first laser, so that the depth of the second groove 120 and the third groove can be made consistent with the depth of the first groove 110, that is, when laser cutting is performed on both, the laser cutting depth of the second cutting lane 12 and the third cutting lane 13 is reduced to improve the strength of the chip 60.

[0085] In some embodiments, the number of second laser burns can be reduced (less than the number of first laser burns) to make the depths of the second and third grooves 120 and 110 consistent with the depth of the first groove 110. If laser cutting is not used for the second and third scribe lines 12 and 13, or if the number of laser burns is low, the laser burn time required for the entire semiconductor device can be reduced, thereby increasing output per unit time.

[0086] It can be understood that, as shown in Figure 1, since the bare chip test structure 30 does not completely cover the first cutting street 11, there will be gaps between the bare chip test structures 30. Therefore, when the first cutting street 11 is laser scanned and cut, the cutting depth in the bare chip test structure 30 will be smaller than the laser cutting depth at the gaps.

[0087] In the chip preparation method provided by the embodiment of the present disclosure, since the bare chip test structure 30 is concentrated in the first cutting street 11, different parameters can be used for the first cutting street 11 during the laser cutting process than for the second cutting street 12 and the third cutting street 13, thereby reducing the laser cutting depth in the second cutting street 12 and the third cutting street 13, thereby improving the strength of the chip 60.

[0088] An embodiment of the present disclosure also provides a chip prepared from the semiconductor device in any of the above embodiments. Referring to Figure 5c, the chip includes a first cutting surface 61 and a second cutting surface 62, wherein the second cutting surface 62 is located outside the first cutting surface 61, and the height of the second cutting surface 62 in the Z direction is less than the height of the first cutting surface 61 in the Z direction.

[0089] Please refer to Figure 6, which is a schematic diagram of the structure of a storage system provided in some embodiments of the present disclosure. The storage system 600 includes a chip 601 and a controller 602. The chip 601 can be the chip in any of the above embodiments, and can be made of the semiconductor device in the above embodiments. The controller 602 is electrically connected to the chip 601 and is used to control the chip 601 to store data. The chip 601 can perform data storage operations based on the control of the controller 602.

[0090] In some embodiments, the storage system may be implemented as a storage device such as a Universal Flash Storage (UFS) device, a solid-state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro MMC, a secure digital card in the form of SD, mini SD and micro SD, a Personal Computer Memory Card International Association (PCMCIA) card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a PCI-Express (PCI-E) type storage device, a Compact Flash (CF) card, a smart media card or a memory stick, etc.

[0091] The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present disclosure; ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A semiconductor device, wherein: The semiconductor device comprises: A plurality of cutting lanes, including at least one first cutting lane, a plurality of second cutting lanes and a third cutting lane, wherein the first cutting lane and the second cutting lane are arranged parallel to each other, and the third cutting lane is arranged to cross the first cutting lane and the second cutting lane; A plurality of bare dies, wherein the plurality of dicing lanes intersect to define the plurality of bare dies; The bare die test structure is located only in the first dicing lanes, and any one of the first dicing lanes is disposed adjacent to at least one of the second dicing lanes.

2. The semiconductor device according to claim 1, wherein At least three second cutting streets are arranged between two adjacent first cutting streets.

3. The semiconductor device according to claim 1, wherein The number of the second cutting lines spaced between two adjacent first cutting lines is equal.

4. The semiconductor device according to claim 1, wherein: The scribe line includes a first dielectric layer and a second dielectric layer alternately stacked, the bare die test structure penetrates the scribe line along a stacking direction of the scribe line, and includes a third dielectric layer and a conductive layer alternately stacked along the stacking direction.

5. The semiconductor device according to claim 4, wherein: The thickness of the bare die test structure is less than or equal to the thickness of the scribe line.

6. The semiconductor device according to claim 5, wherein: The bare die test structures with the same thickness are located in the same first dicing street.

7. The semiconductor device according to claim 4, wherein: The semiconductor device further comprises: Semiconductor layer; A stacking layer, located on the semiconductor layer, and comprising the third dielectric layer and the conductive layer alternately stacked along the stacking direction; The dicing road and the bare die test structure are located on the semiconductor layer.

8. The semiconductor device according to claim 1, wherein The bare die includes a memory device and a peripheral circuit bonded to each other, and the bare die test structure is used for electrical testing of the memory device, the peripheral circuit or the bonding surface between the memory device and the peripheral device.

9. The semiconductor device according to claim 1, wherein: The plurality of dicing lanes and the plurality of bare chips form a repeating unit, and the repeating unit includes at least one of the first dicing lanes; the semiconductor device includes a plurality of the repeating units.

10. A chip made from the semiconductor device according to any one of claims 1 to 9, wherein: The chip includes a first cutting surface and a second cutting surface, wherein the second cutting surface is located at the periphery of the first cutting surface, and the height of the second cutting surface is smaller than the height of the first cutting surface.

11. A storage system, wherein: The storage system comprises: The chip according to claim 10; A controller is electrically connected to the chip and is used to control the chip to store data.

12. A method for preparing a chip, wherein: The method for preparing the semiconductor device comprises: A semiconductor device is provided, wherein a plurality of cutting paths are provided in the semiconductor device, wherein the cutting paths include a first cutting path, a second cutting path and a third cutting path, wherein the first cutting path and the second cutting path are arranged parallel to each other, the third cutting path is arranged to intersect with the first cutting path and the second cutting path, and a bare die test structure is arranged in the first cutting path; The semiconductor device is cut into a plurality of chips along the first scribe line, the second scribe line and the third scribe line.

13. The method for preparing a chip according to claim 12, wherein: The step of cutting the semiconductor device into a plurality of chips along the first cutting street, the second cutting street and the third cutting street comprises: The semiconductor device is cut twice using two different cutting processes.

14. The method for preparing a chip according to claim 13, wherein: The step of cutting the semiconductor device into a plurality of chips along the first cutting street, the second cutting street and the third cutting street comprises: Using a first laser to form a first groove in the first scribe line to remove a portion of the bare die test structure, wherein a depth of the first groove is less than a thickness of the first scribe line; The second dicing line, the third dicing line and the first dicing line below the first slot are mechanically diced to form a plurality of chips.

15. The method for preparing a chip according to claim 14, wherein: Before the step of using a blade to cut the first scribe line, the second scribe line, and the third scribe line below the first slot, the chip preparation method further includes: A second laser is used to form a second slot in the second cutting street, and a second slot is formed in the third cutting street. forming a third groove in the second cutting path, wherein the depth of the second groove is less than the thickness of the second cutting path, and the depth of the third groove is less than the thickness of the third cutting path; The step of mechanically cutting the second cutting path, the third cutting path and the first cutting path below the first slot includes: using a blade to cut the first cutting path below the first slot, the second cutting path below the second slot and the third cutting path below the third slot.

16. The method for preparing a chip according to claim 15, wherein: The energy of the second laser is smaller than the energy of the first laser.

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