Integrated dipole region of transistor

Abstract

Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the present disclosure advantageously provide an electronic device that includes a dipole region and meets reduced thickness and lower thermal budget requirements. An electronic device described herein includes a source region, a drain region, and a channel separating the source region from the drain region, an interface layer on a top surface of the channel, a high-k dielectric layer on the interface layer, a dipole layer on the high-k dielectric layer, and optionally a cap layer on the dipole layer. In some embodiments, the method includes annealing the substrate to drive atoms from the dipole layer into one or more of the interfacial layer or the high-k dielectric layer.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of electronic device manufacturing, and in particular to transistors. More particularly, embodiments of the present disclosure relate to FinFET devices and methods of manufacturing FinFET devices. Background Art

[0002] Integrated circuits have evolved into complex devices that may include millions of transistors, capacitors, and resistors on a single chip. In the course of integrated circuit evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line segment) that can be created using a manufacturing process) has decreased.

[0003] A transistor is a circuit component or element typically formed on a semiconductor device. Depending on the circuit design, many transistors may be formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, wires, or other elements. Integrated circuits incorporate planar field effect transistors (FETs) in which current flows through a semiconductor channel between a source and a drain in response to a voltage applied to a control gate.

[0004] As device dimensions have shrunk, device geometries and materials have encountered difficulties in maintaining switching speeds without causing failures. Several new technologies have emerged to allow chip designers to continue to reduce gate lengths. Control of device structure dimensions is a key challenge for current and future technology generations.

[0005] Due to the differences in basic properties (such as threshold voltage, V t )) changes, the reduction of materials currently used as N-MOS and P-MOS has become a challenge. In addition, the transistor technology moving from planar to FinFET requires conformal work function layers for a variety of threshold voltages. V t The tuning range will be limited by the variation in film thickness with further reduction in device size.

[0006] Therefore, there is a need for an electronic device having a dipole region that meets the requirements of reduced thickness and lower thermal budget and a method of manufacturing the electronic device. Summary of the invention

[0007] One or more embodiments relate to a method of manufacturing an electronic device. In some embodiments, the method includes depositing an interfacial layer on a top surface of a channel, the channel being located between a source and a drain on a substrate; depositing a high-K dielectric layer on the interfacial layer; and depositing a dipole layer on the high-K dielectric layer by exposing the substrate to alternating cycles of a metal precursor and a nitrogen-containing reactant. The metal precursor comprises one or more of strontium (Sr), yttrium (Y), ytterbium (Yb), antimony (Sb), or tellurium (Te). The method further comprises annealing the substrate at a temperature less than or equal to 1050° C. to drive atoms from the dipole layer into the high-K dielectric layer. The method optionally comprises depositing a cap layer on the dipole layer.

[0008] Additional embodiments relate to an electronic device comprising a source region, a drain region, and a channel separating the source region and the drain region; an interface layer on a top surface of the channel; a high-K dielectric layer on the interface layer; a dipole layer on the high-K dielectric layer, the dipole layer comprising one or more of strontium (Sr), yttrium (Y), ytterbium (Yb), antimony (Sb), or tellurium (Te); and, optionally, a capping layer on the dipole layer.

[0009] Further embodiments relate to a non-transitory computer-readable medium comprising instructions that, when executed by a controller of a processing chamber, cause the processing chamber to perform the following operations: deposit an interface layer on a top surface of a channel, the channel being located between a source and a drain on a substrate; deposit a high-K dielectric layer on the interface layer; deposit a dipole layer on the high-K dielectric layer by exposing the substrate to alternating cycles of a metal precursor and a nitrogen-containing reactant, the metal precursor comprising one or more of strontium (Sr), yttrium (Y), ytterbium (Yb), antimony (Sb), or tellurium (Te); annealing the substrate at a temperature less than or equal to 1050° C. to drive atoms from the dipole layer into the high-K dielectric layer; and optionally, depositing a cap layer on the dipole layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] By referring to the embodiments in which some embodiments are illustrated in the accompanying drawings, a more specific description of the present disclosure briefly summarized above can be obtained, so that the above-mentioned features of the present disclosure can be understood in detail. However, it will be noted that the drawings only illustrate typical embodiments of the present disclosure and are therefore not to be regarded as limiting its scope, as the present disclosure may allow other equivalent embodiments. The embodiments described herein are illustrated as examples and are not limited to the illustrations in the accompanying drawings, and the same element symbols in the accompanying drawings indicate similar elements.

[0011] Figure 1 a process flow diagram depicting one embodiment of a method according to embodiments described herein;

[0012] Figure 2 depicts a cross-sectional view of a substrate according to one or more embodiments;

[0013] Figure 3A depicts a cross-sectional view of a substrate according to one or more embodiments;

[0014] Figure 3B depicts a cross-sectional view of a substrate according to one or more embodiments; and

[0015] Figure 4 A cluster tool according to one or more embodiments of the present disclosure is depicted. DETAILED DESCRIPTION

[0016] Before describing several exemplary embodiments of the present disclosure, it will be understood that the present disclosure is not limited to the details of the architecture or processing steps set forth in the following description. The present disclosure is capable of other embodiments and can be practiced or carried out in various ways.

[0017] The term "about" as used herein means approximately or nearly, and in the context of a stated value or range means a variation of ±15% or less of that value. For example, a difference in values ​​of ±14%, ±10%, ±5%, ±2%, or ±1% would satisfy the definition of about.

[0018] As used in this specification and the appended claims, the term "substrate" or "wafer" refers to a surface or portion of a surface on which processing is performed. Unless the context clearly indicates otherwise, those skilled in the art will also understand that reference to a substrate may refer to only a portion of a substrate. In addition, reference to a deposition on a substrate may mean both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0019] As used herein, "substrate" refers to any substrate or material surface formed on a substrate on which film processing is performed during a manufacturing process. For example, substrate surfaces on which processing may be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other material, such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, without limitation, semiconductor wafers. The substrate may be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in the present disclosure, any of the film processing steps disclosed may also be performed on an under-layer formed on the substrate, as described in more detail later, and the term "substrate surface" is intended to include such under-layer as indicated by the context. Thus, for example, where a film / layer or portion of a film / layer has been deposited onto a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0020] As used in this specification and the appended claims, the terms "precursor," "reactant," "reactant gas," and the like may be used interchangeably to refer to any gaseous species that may react with a substrate surface.

[0021] The term “on” indicates that there is direct contact between elements. The term “directly on” indicates that there is direct contact between elements and there are no intervening elements.

[0022] As used herein, "atomic layer deposition" or "cyclic deposition" refers to the sequential exposure of two or more reactive compounds to deposit a layer of material on a substrate surface. A substrate or portion of a substrate is separately exposed to two or more reactive compounds introduced into a reaction zone of a processing chamber. In a time-domain ALD process, exposure to each reactive compound is separated by a time delay to allow each compound to adhere and / or react on the substrate surface and then be purged from the processing chamber. The reactive compounds are said to be exposed to the substrate sequentially. In a spatial ALD process, different portions of the substrate surface or materials on the substrate surface are simultaneously exposed to the two or more reactive compounds, such that any given point on the substrate is not substantially simultaneously exposed to more than one reactive compound. As used in this specification and the appended claims, as will be understood by those skilled in the art, the term "substantially" used in this regard means that there is a possibility that a small portion of the substrate will be exposed to multiple reactive gases simultaneously due to diffusion, and such simultaneous exposure is not intentional.

[0023] In one aspect of a time-domain ALD process, a first reactant gas (i.e., a first precursor or compound A) is pulsed into a reaction region followed by a first time delay. Next, a second precursor or compound B is pulsed into the reaction region followed by a second delay. During each time delay, a purge gas such as argon is introduced into the process chamber to purge the reaction region or remove any residual reactant compounds or reaction byproducts from the reaction region. Alternatively, the purge gas may flow continuously during the entire deposition process such that only the purge gas flows during the time delay between pulses of the reactant compounds. The reactant compounds are alternately pulsed until a desired film or film thickness is formed on the substrate surface. In either scenario, the pulsing compound A, purge gas, compound B, and purge gas of the ALD process is a cycle. A cycle may start with either compound A or compound B, and continue the corresponding order of this cycle until a film with a desired thickness is obtained.

[0024] In an embodiment of a spatial ALD process, a first reactant gas and a second reactant gas (e.g., nitrogen) are delivered to the reaction region simultaneously, but separated by an inert gas curtain and / or a vacuum curtain. The substrate moves relative to the gas delivery apparatus so that any given point on the substrate is exposed to both the first reactant gas and the second reactant gas.

[0025] A transistor is a circuit component or element typically formed on a semiconductor device. Depending on the circuit design, a transistor is formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, wires, or other elements. In general, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source region and the drain region include doped regions of a substrate and exhibit a doping profile suitable for a particular application. The gate is positioned above the channel region and includes a gate dielectric inserted in the substrate between the gate electrode and the channel region.

[0026] As used herein, the term "field effect transistor" or "FET" refers to a transistor that uses an electric field to control the electrical behavior of the device. A field effect transistor is a voltage-controlled device in which the current carrying capacity of the field effect transistor is altered by the application of an electric field. Field effect transistors typically exhibit very high input impedance at low temperatures. The conductivity between the drain and source terminals is controlled by the electric field in the device, which is generated by the voltage difference between the body of the device and the gate. The three terminals of a FET are the source (S), through which carriers enter the channel; the drain (D), through which carriers leave the channel; and the gate (G), which regulates the channel conductivity. Traditionally, the current entering the channel at the source (S) is denoted as I S and the current entering the channel at the drain (D) is denoted as I D The drain-to-source voltage is labeled V DS By applying a voltage to the gate (G), the current entering the channel at the drain (i.e., I D ).

[0027] A metal oxide semiconductor field effect transistor (MOSFET) is a type of field effect transistor (FET) and is used in integrated circuits and high-speed switching applications. A MOSFET has an insulated gate, the voltage of which determines the conductivity of the device. The ability to change the conductivity with the amount of applied voltage is used to amplify or switch electronic signals. MOSFETs are based on the modulation of the charge concentration through a metal oxide semiconductor (MOS) capacitor between a body electrode and a gate electrode, which is located above the body and insulated from all other device regions by a gate dielectric layer. Compared to a MOS capacitor, a MOSFET includes two additional terminals (source and drain), each of which is connected to a separate highly doped region separated by a body region. These regions can be p-type or n-type, but they are all the same type and opposite to the type of the body region. The source and drain (unlike the body) are highly doped and are indicated by a "+" sign after the doping type.

[0028] If the MOSFET is an n-channel or nMOS FET, the source and drain are n+ regions and the bulk is the p-type substrate region. If the MOSFET is a p-channel or pMOS FET, the source and drain are p+ regions and the bulk is the n-type substrate region. The source is so named because it is the source of charge carriers (electrons for an n-channel and holes for a p-channel) that flow through the channel; similarly, the drain is where the charge carriers leave the channel.

[0029] An nMOS FET is made of an n-type source and drain and a p-type substrate. When voltage is applied to the gate, holes in the bulk (p-type substrate) are driven away from the gate. This allows an n-type channel to form between the source and drain and current is carried through the induced n-type channel by electrons from the source to the drain. Logic gates and other digital devices implemented using NMOS are said to have NMOS logic. There are three operating modes in NMOS called cutoff, triode, and saturation. Circuits with NMOS logic gates dissipate static power when the circuit is idle because DC current flows through the logic gate when the output is low.

[0030] The pMOS FET is made of p-type source and drain and an n-type substrate. When a positive voltage is applied between the source and gate (negative voltage between the gate and source), a p-type channel is formed between the source and drain with opposite polarity of the channel. Current is carried through the induced p-type channel by holes from the source to the drain. A high voltage on the gate will cause the PMOS to not conduct, while a low voltage on the gate will cause it to conduct. Logic gates and other digital devices implemented using PMOS are called PMOS logic. PMOS technology is low cost and has good noise immunity.

[0031] In NMOS, the carriers are electrons, while in PMOS, the carriers are holes. When a high voltage is applied to the gate, NMOS will turn on, while PMOS will not. In addition, when a low voltage is applied to the gate, NMOS will not turn on and PMOS will turn on. NMOS is considered to be faster than PMOS because the carriers in NMOS are electrons, and electrons travel twice as fast as holes, which are carriers in PMOS. However, PMOS devices are more immune to interference than NMOS devices. Furthermore, NMOS ICs will be smaller than PMOS ICs (given the same functionality) because NMOS can provide half the impedance provided by PMOS (which has the same geometry and operating conditions).

[0032] As used herein, the term "fin field effect transistor (FinFET)" refers to a MOSFET transistor built on a substrate where the gate is placed on two, three, or four sides of the channel or wrapped around the channel, forming a dual gate structure. FinFET devices have been given the generic name FinFET, since the source / drain regions form a "fin" on the substrate. FinFET devices have fast switching times and high current density.

[0033] As used herein, the term "gate-all-around (GAA)" is used to refer to an electronic device, such as a transistor, in which a gate material surrounds a channel region on all sides. The channel region of a GAA transistor may include nanowires or nano-slabs or nanosheets, strip-shaped channels, or other suitable channel configurations known to those skilled in the art. In one or more embodiments, the channel region of a GAA device has multiple horizontal nanowires or horizontal strips spaced vertically, making the GAA transistor a stacked horizontal gate-all-around (hGAA) transistor.

[0034] As used herein, the term "nanowire" refers to a nanostructure with a diameter of less than one nanometer (10 9Nanowires may also be defined as having a ratio of length to width greater than 1000. Alternatively, nanowires may be defined as structures having a thickness or diameter limited to tens of nanometers or less and an unlimited length. Nanowires are used in transistors and some laser applications, and in one or more embodiments, the nanowires are made of semiconductor materials, metallic materials, insulating materials, superconducting materials, or molecular materials. In one or more embodiments, nanowires are used in transistors for logic CPUs, GPUs, MPUs, and volatile (e.g., DRAM) and non-volatile (e.g., NAND) devices. As used herein, the term "nanosheet" refers to a two-dimensional nanostructure having a thickness in a scale ranging from about 0.1 nm to about 1000 nm, or from 0.5 nm to 500 nm, or from 0.5 nm to 100 nm, or from 1 nm to 500 nm, or from 1 nm to 100 nm, or from 1 nm to 50 nm.

[0035] Embodiments of the present disclosure advantageously provide electronic devices that include integrated dipole regions to meet reduced thickness and lower thermal budget requirements. One or more embodiments advantageously involve materials that can be used as effective diodes for p-FETs, which improve V t The new material class can be used in p-diodes without increasing the EOT. Due to the new integration scheme, the embodiments of the present disclosure significantly improve V t Embodiments of the present disclosure include diode materials that provide at least 50 mV V t Move with minimal EOT increase.

[0036] Embodiments of the present disclosure are illustrated by the accompanying drawings, which depict devices (e.g., transistors) and processes for forming transistors according to one or more embodiments of the present disclosure. The processes shown are merely exemplary possible uses for the disclosed processes, and those skilled in the art will recognize that the disclosed processes are not limited to the illustrated applications.

[0037] Figure 1A flow chart depicting a method 100 of manufacturing an electronic device according to one or more embodiments of the present disclosure. The method 100 begins at operation 102 by depositing an interface layer on a top surface of a channel between a source and a drain on a substrate. At operation 104, a high-K dielectric layer is deposited on the interface layer. At operation 106, a dipole layer is deposited on the high-K dielectric layer. In one or more embodiments not shown, the method 100 includes performing a free radical treatment. At operation 108, a cap layer is optionally deposited on the dipole layer. At operation 110, the method 100 includes annealing the substrate.

[0038] In some embodiments, at operation 102, the interface layer is deposited using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin coating, or other insulating layer deposition techniques known to those skilled in the art. In one or more embodiments, the interface layer is formed by etching and forming an oxide on the surface.

[0039] In some embodiments, at operation 102, a wet chemical technique is performed to form an interface layer. The wet chemical technique may be any technique known to those skilled in the art. In some embodiments, the wet chemical technique includes a pre-cleaning treatment. In some embodiments, the pre-cleaning treatment includes using an SC-1 solution containing one or more of ozone, ammonium hydroxide, or hydrogen peroxide. In some embodiments, the pre-cleaning treatment includes using an SC-1 solution without ozone, ammonium hydroxide, or hydrogen peroxide. In some embodiments, after using the SC-1 solution, the pre-cleaning treatment includes using a diluted hydrofluoric acid (diluted HF) comprising greater than 100:1, such as 130:1 diluted HF, to etch away native oxides on the substrate to form a hydrophobic surface (i.e., an interface layer).

[0040] In some embodiments, at operation 104, a high-K dielectric layer is deposited using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin coating, or other insulating layer deposition techniques known to those skilled in the art. In some embodiments, at operation 104, the high-K dielectric layer is conformally deposited by ALD.

[0041] In some embodiments, at operation 106 , a dipole layer is deposited on the high-K dielectric layer using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin coating, or other insulating layer deposition techniques known to those skilled in the art.

[0042] In some embodiments, a dipole layer is deposited on a high-k dielectric layer by ALD. According to some embodiments, an ALD cycle includes exposing a substrate to a pulse of a metal precursor to form a dipole layer on a surface of the substrate. The metal precursor includes one or more of strontium (Sr), yttrium (Y), ytterbium (Yb), antimony (Sb), or tellurium (Te). In some embodiments, the dipole layer includes one or more of strontium (Sr), yttrium (Y), ytterbium (Yb), antimony (Sb), or tellurium (Te). The metal precursor is then purged from the processing chamber or removed from a reaction zone adjacent to the substrate surface. The substrate with the dipole layer thereon is exposed to a pulse of a nitrogen reactant (e.g., ammonia) to form a metal-containing layer or a metal-containing nitride layer on the substrate surface. The nitrogen reactant is then purged from the processing chamber or removed from a reaction zone adjacent to the substrate surface.

[0043] In some embodiments, the metal precursor comprising strontium (Sr) comprises any suitable strontium-containing precursor. In some embodiments, the strontium-containing precursor comprises one or more of strontium imidazole, strontium amidinate, strontium bisamidinate, strontium cyclopentadienyl, or bis(tri-isopropylcyclopentadienyl)strontium.

[0044] In some embodiments, the metal precursor comprising yttrium (Y) comprises any suitable yttrium-containing precursor. In some embodiments, the yttrium-containing precursor comprises one or more of yttrium formamidinate, tris(N,N'-di-i-propylformamidinato)yttrium(III), yttriumtriscyclopentadienyl, tris(butylcyclopentadienyl)yttrium, tris(methlycyclopentadienyl)yttrium, or tris(n-propylcyclopentadienyl)yttrium.

[0045] In some embodiments, the metal precursor comprising ytterbium (Yb) comprises any suitable ytterbium-containing precursor. In some embodiments, the ytterbium-containing precursor comprises one or more of ytterbium formamidinate, Tris(N,N'-di-i-propylformamidinato)ytterbium(III), or ytterbium cyclopentadienyl.

[0046] In some embodiments, the metal precursor comprising antimony (Sb) comprises any suitable antimony-containing precursor. In some embodiments, the antimony-containing precursor comprises one or more of antimony trichloride, antimony pentachloride, or antimony tris(trimethylsilane). In some embodiments, an ALD cycle of antimony trichloride and antimony tris(trimethylsilane) can deposit a pure antimony (Sb) film.

[0047] In some embodiments, the metal precursor comprising tellurium (Te) comprises any suitable tellurium-containing precursor. In some embodiments, the tellurium-containing precursor comprises one or more of tellurium bis(trimethylsilane) or di(tert-butyl) telluride.

[0048] In some embodiments, the nitrogen-containing reactant comprises one or more of nitrogen (N2), ammonia (NH3), hydrazine (N2H4), or a co-flow of nitrogen radicals (N2*) and hydrogen radicals (H*). In some embodiments, the nitrogen-containing reactant comprises a substituted or unsubstituted alkyl hydrazine. In some embodiments, the alkyl hydrazine comprises a range from 1 carbon to 6 carbons. In one or more embodiments, the alkyl hydrazine is tert-butyl hydrazine. In some embodiments, the nitrogen-containing reactant comprises a plasma.

[0049] In some embodiments, the metal precursor comprises one or more of strontium (Sr), yttrium (Y), ytterbium (Yb), antimony (Sb), and the nitrogen-containing reactant comprises one or more of nitrogen (N2), ammonia (NH3), hydrazine (N2H4), or a co-current of nitrogen radicals (N2*) and hydrogen radicals (H*).

[0050] Without wishing to be bound by theory, it is believed that some metal nitrides, such as one or more of strontium nitride, yttrium nitride, ytterbium nitride, antimony nitride, or tellurium nitride, may be unstable nitrides or metastable nitrides at high deposition temperatures / high temperature processing. For example, one or more of strontium nitride, yttrium nitride, ytterbium nitride, antimony nitride, or tellurium nitride may be unstable nitrides at temperatures greater than or equal to 250° C. In other words, strontium nitride, yttrium nitride, ytterbium nitride, antimony nitride, or tellurium nitride may not have the same stoichiometry as the metal nitride at temperatures greater than or equal to 250° C.

[0051] In some embodiments, at operation 106, a dipole layer is deposited on the high-K dielectric layer by ALD at a temperature of less than or equal to 500° C. and a pressure of less than or equal to 50 Torr. In some embodiments, the temperature is in a range from 100° C. to 500° C., or in a range from 150° C. to 450° C., in a range from 200° C. to 400° C., or in a range from 250° C. to 350° C. In some embodiments, the pressure is in a range from 0 mTorr to 50 Torr, or in a range from 100 mTorr to 50 Torr, or in a range from 1 Torr to 40 Torr, in a range from 10 Torr to about 35 Torr, or in a range from 20 Torr to 30 Torr. Without wishing to be bound by theory, it is believed that when the dipole layer is deposited on the high-K dielectric layer by ALD at a temperature of, for example, 450° C. or 500° C., atoms from the dipole layer are driven into the high-K dielectric layer.

[0052] In some embodiments, at operation 108, a cap layer is optionally deposited on the dipole layer using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin coating, or other insulating layer deposition techniques known to those skilled in the art.

[0053] In some embodiments, at operation 110, the method 100 includes annealing the substrate at a temperature less than or equal to 1100° C. to drive atoms from the dipole layer into the high-K dielectric layer. In some embodiments, at operation 110, the method 100 includes annealing the substrate at a temperature less than or equal to 1050° C. to drive atoms from the dipole layer into the high-K dielectric layer. In some embodiments, the temperature is in a range from 500° C. to 1100° C., including in a range from 500° C. to 1050° C., including in a range from 600° C. to 1025° C., in a range from 700° C. to 1000° C., in a range from 750° C. to 950° C., or in a range from 800° C. to 900° C.

[0054] Without wishing to be bound by theory, it is contemplated that annealing the substrate according to operation 110 drives an increased number of atoms from the dipole layer into one or more of the interfacial layer or the high-K dielectric layer compared to a process where no annealing occurs. In one or more embodiments, annealing the substrate at operation 110 includes a rapid thermal process (RTP). The RTP may be any suitable process known to those skilled in the art. Without wishing to be bound by theory, the RTP is believed to densify and improve the physical properties of the deposited dipole layer.

[0055] Without wishing to be bound by theory, it is contemplated that a dipole region including a channel having an n-type material or a p-type material and a dipole layer as described above simplifies existing integration processes and reduces integration costs. In addition, when atoms (such as metal atoms) from the dipole layer are embedded in the interface layer and / or the high-K dielectric layer, a dipole region is formed and oxidation is contemplated to be reduced, which potentially reduces the required annealing temperature.

[0056] In one or more embodiments not shown, method 100 includes performing an etching process to remove the cap layer and the dipole layer. The etching process can be any suitable etching process known to those skilled in the art. In some embodiments, the etching process includes a wet etching process or a dry etching process. In some embodiments, the etching process includes a wet etching process.

[0057] Without wishing to be bound by theory, the high-K dielectric layer includes properties of the dipole layer when, at operation 110, the method 100 includes annealing the substrate at a temperature less than or equal to 1050° C. to drive atoms from the dipole layer into the high-K dielectric layer. In other words, after performing an etching process to remove the cap layer and the dipole layer, the high-K dielectric layer has the dipole properties as a result of the annealing process (operation 110).

[0058] In one or more embodiments, the cap layer and the dipole layer are removed, and a gate comprising one or more of a gate metal (not shown) or a gate contact (not shown) may be optionally formed or deposited on the exposed surface of the high-K dielectric layer. The gate metal may be any suitable material known to those skilled in the art. In one or more embodiments, the gate metal comprises one or more of nitrogen (N), copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), ruthenium (Ru), iridium (Ir), aluminum (Al), or platinum (Pt). In one or more specific embodiments, the gate metal comprises a metal selected from one or more of nitrogen (N), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), iridium (Ir), aluminum (Al), or platinum (Pt). In other specific embodiments, the gate metal comprises a metal or metal alloy selected from one or more of nitrogen (N), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), ruthenium (Ru), hafnium (Hf), or zirconium (Zr). In an embodiment where the gate metal is formed on a high-K dielectric layer, the gate metal is deposited as a gate metal layer (not shown). The gate metal layer may be deposited using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin coating, or other insulating layer deposition techniques known to those skilled in the art. The gate metal layer may have any suitable thickness. In some embodiments, the gate metal layer has a thickness in the range of from 1 nm to 3 nm. In an embodiment where the gate metal is formed on a high-K dielectric layer, the gate metal layer has a capping layer thereon. The capping layer on the gate metal layer may have any suitable thickness. In some embodiments, the capping layer on the gate metal layer has a thickness in a range from 0.5 nm to 2 nm, including in a range from 0.6 nm to 1.9 nm, in a range from 0.7 nm to 1.8 nm, in a range from 0.8 nm to 1.7 nm, in a range from 0.9 nm to 1.6 nm, in a range from 1 nm to 1.5 nm, in a range from 1.1 nm to 1.4 nm, or in a range from 1.2 nm to 1.3 nm.

[0059] In one or more embodiments, the gate contact may be any suitable material known to those skilled in the art. In one or more embodiments, the gate contact includes an element or alloy selected from one or more of nitrogen (N), copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), iridium (Ir), tantalum (Ta), aluminum (Al), or platinum (Pt).

[0060] Figure 2 , Figure 3A ,and Figure 3Bis a cross-sectional view of an electronic device (eg, transistor) 200 according to one or more embodiments. Figure 2 , Figure 3A ,and Figure 3B The electronic device 200 in the embodiment can be Figure 1 The method 100 shown in FIG.

[0061] In one or more embodiments, the electronic device 200 includes a semiconductor substrate 202 having a top surface 203. The semiconductor substrate 202 can be any suitable substrate material. In one or more embodiments, the semiconductor substrate 202 includes a semiconductor material, such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium phosphide (InP), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), germanium (Ge), silicon germanium (SiGe), copper indium gallium selenide (CIGS), other semiconductor materials, or any combination of the foregoing. In one or more embodiments, the semiconductor substrate 202 includes one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), indium (In), phosphorus (P), copper (Cu), or selenium (Se). Although a few examples of materials that may form substrate 202 are described herein, any material that may serve as a basis for passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic device) upon which may be constructed falls within the spirit and scope of the present disclosure.

[0062] In one or more embodiments, the semiconductor substrate 202 is a p-type or n-type substrate. As used herein, the term "n-type" refers to a semiconductor created by doping an intrinsic semiconductor with an electron donor element during fabrication. The term n-type comes from the negative charge of the electron. In an n-type semiconductor, electrons are the majority carriers and holes are the minority carriers. As used herein, the term "p-type" refers to the positive charge of the well (or hole). In contrast to an n-type semiconductor, a p-type semiconductor has a greater concentration of holes than electrons. In a p-type semiconductor, holes are the majority carriers and electrons are the minority carriers.

[0063] In some embodiments, the source region 204a is on the top surface 203 of the semiconductor substrate 202. In one or more embodiments, the source region 204a has a source and a source contact (not shown). The drain region 204b is opposite to the source region 204a on the top surface 203 of the semiconductor substrate 202. In one or more embodiments, the drain region 204b has a drain and a drain contact (not shown).

[0064] In one or more embodiments, the source region 204a and / or the drain region 204b may be any suitable material known to those skilled in the art. In one or more embodiments, the source region 204a and / or the drain region 204b may have more than one layer. For example, the source region 204a and / or the drain region 204b may independently include three layers. In one or more embodiments, the source region 204a and the drain region 204b may independently include one or more of copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), platinum (Pt), phosphorus (P), germanium (Ge), silicon (Si), aluminum (Al), or zirconium (Zr). In some embodiments, the source region 204a and the drain region 204b may independently include a bottom layer with doped epitaxial silicon (e.g., SiGe, SiP, and the like), a second layer of silicide, which may contain nickel (Ni), titanium (Ti), aluminum (Al), and the like, and a third layer or top layer, which may be a metal such as, but not limited to, cobalt, tungsten, ruthenium, and the like.

[0065] In some embodiments, the source region 204a and the drain region 204b may be elevated source / drain regions formed by epitaxial growth. In one or more embodiments, the source contact and / or the drain contact may be independently selected from one or more of nitrogen (N), copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), or platinum (Pt). In one or more embodiments, the formation of the source contact and / or the drain contact is performed by any suitable process known to those skilled in the art, including but not limited to ALD, CVD, PVD, MBE, MOCVD, spin coating, or other insulating layer deposition techniques known to those skilled in the art.

[0066] In one or more embodiments, the channel 206 is located between the source 204a and the drain 204b. In one or more embodiments, the dipole region 208 covers the channel 206 and contacts one or more of the channel 206, the source region 204a, and the drain region 204b. In one or more embodiments, the dipole region 208 has a thickness in a range from 2 nm to 6 nm, including in a range from 2.5 nm to 5.5 nm, in a range from 3 nm to 5 nm, or in a range from 3.5 nm to 4.5 nm.

[0067] In one or more embodiments, the dipole region 208 includes one or more of an interface layer 210, a high-K dielectric layer 212, a dipole layer 214, and a cap layer 216. In some embodiments, the dipole region 208 includes an interface layer 210, a high-K dielectric layer 212, a dipole layer 214, and a cap layer 216. In some embodiments, the dipole region 208 includes an interface layer 210, a high-K dielectric layer 212, and a dipole layer 214.

[0068] In one or more embodiments, the interface layer 210 is deposited on the top surface 205 of the trench 206. In some embodiments, the interface layer 210 is deposited on the top surface 205 of the trench 206 according to operation 102 of the method 100. In some embodiments, the interface layer 210 comprises a dielectric material selected from one or more of silicon (Si), silicon oxide (SiOx), doped silicon, doped silicon oxide, or a spin-on dielectric.

[0069] The interface layer 210 can have any suitable thickness. In some embodiments, the interface layer 210 has a thickness in a range from 0.2 nm to 0.8 nm, including in a range from 0.3 nm to 0.7 nm, or in a range from 0.4 nm to 0.6 nm.

[0070] In one or more embodiments, the high-K dielectric layer 212 is deposited on the top surface 211 of the interface layer 210. In some embodiments, the high-K dielectric layer 212 is deposited on the top surface 211 of the interface layer 210 according to operation 104 of the method 100. The high-K dielectric layer 212 can be any suitable high-K dielectric material known to those skilled in the art. In one or more embodiments, the high-K dielectric layer 212 includes one or more of hafnium oxide (HfOx), zirconium oxide (ZrOx), hafnium zirconium oxide (HfZrOx), or a spin-on dielectric.

[0071] The high-K dielectric layer 212 can have any suitable thickness. In some embodiments, the high-K dielectric layer 212 has a thickness in a range from 1 nm to 2 nm, including in a range from 1.1 nm to 1.9 nm, in a range from 1.2 nm to 1.8 nm, in a range from 1.3 nm to 1.7 nm, or in a range from 1.4 nm to 1.6 nm.

[0072] In one or more embodiments, the dipole layer 214 is deposited on the top surface 213 of the high-K dielectric layer 212. In some embodiments, the dipole layer 214 is deposited on the top surface 213 of the high-K dielectric layer 212 according to operation 106 of the method 100. The dipole layer 214 can have any suitable thickness. In some embodiments, the dipole layer 214 has a thickness in a range from 0.3 nm to 1.5 nm, including in a range from 0.4 nm to 1.4 nm, in a range from 0.5 nm to 1.3 nm, in a range from 0.6 nm to 1.2 nm, in a range from 0.7 nm to 1.1 nm, or in a range from 0.8 nm to 1.0 nm.

[0073] In one or more specific embodiments, when the dipole layer 214 comprises one or more of a metal carbide, a metal nitride, or a metal oxide, the method 100 further comprises performing a free radical treatment (not shown) to remove carbides, nitrides, and oxides from each of the metal carbide, the metal nitride, or the metal oxide. The free radical treatment process may include any process known to those skilled in the art to remove carbides, nitrides, and oxides. In one or more embodiments, the free radical treatment comprises introducing free radicals comprising one or more of H*, OH*, O*, N2*, NH3*, or H2O*. In some embodiments, the free radicals are generated by forming a plasma from a free radical gas. In some embodiments, the plasma is generated by a remote plasma source.

[0074] In some embodiments, the free radical treatment is performed once after the dipole layer 214 deposition cycle has been completed to form the dipole layer 214 having a predetermined thickness. In some embodiments, the free radical treatment is performed during the dipole layer 214 deposition cycle. In some embodiments, the free radical treatment is performed multiple times during the dipole layer 214 deposition cycle. In some embodiments, the free radical treatment is performed up to 5 times during the dipole layer 214 deposition cycle. For example, a thin dipole layer (e.g., a dipole layer having a thickness of 0.3 nm) is deposited and followed by the free radical treatment. In some embodiments, method 100 includes the following sequence: depositing a first thin dipole layer (e.g., a dipole layer having a thickness of 0.3 nm), performing a free radical treatment, depositing a second thin dipole layer (e.g., a dipole layer having a thickness of 0.3 nm), performing a free radical treatment, depositing a third thin dipole layer (e.g., a dipole layer having a thickness of 0.3 nm), performing a free radical treatment, depositing a fourth thin dipole layer (e.g., a dipole layer having a thickness of 0.3 nm), performing a free radical treatment, and depositing a fifth thin dipole layer (e.g., a dipole layer having a thickness of 0.3 nm), and performing a free radical treatment.

[0075] In one or more embodiments, after the deposition of the dipole layer 214, a capping layer 216 is optionally deposited to control film oxidation. In one or more embodiments, the capping layer 216 is optionally deposited on the top surface 215 of the dipole layer 214 according to operation 108 of the method 100. In one or more embodiments, the electronic device 200 does not include the capping layer 216.

[0076] In one or more embodiments where the electronic device 200 includes a capping layer 216, the capping layer 216 is an in-situ capping layer. In some embodiments, the capping layer 216 comprises one or more of amorphous silicon, a metal, a metal carbide, a metal nitride, or a metal oxide. The capping layer 216 may have any suitable thickness. In some embodiments, the capping layer has a thickness in a range from 0.5 nm to 2 nm, including in a range from 0.6 nm to 1.9 nm, in a range from 0.7 nm to 1.8 nm, in a range from 0.8 nm to 1.7 nm, in a range from 0.9 nm to 1.6 nm, in a range from 1 nm to 1.5 nm, in a range from 1.1 nm to 1.4 nm, or in a range from 1.2 nm to 1.3 nm.

[0077] Reference Figure 3A In one or more embodiments, the cap layer 216 on the PFET side 250 is removed by patterning. Figure 3B In one or more embodiments, the dipole layer 214 and the cap layer 216 on the PFET side 250 are removed by patterning.

[0078] In one or more embodiments, after removing the cap layer and the dipole layer, a gate comprising one or more of a gate metal (not shown) or a gate contact (not shown) may be optionally formed or deposited on the exposed surface of the high-K dielectric layer. The gate metal may be any material known to those skilled in the art. In one or more embodiments, the gate metal comprises one or more of nitrogen (N), copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), ruthenium (Ru), iridium (Ir), aluminum (Al), or platinum (Pt). In one or more specific embodiments, the gate metal comprises a metal selected from one or more of nitrogen (N), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), iridium (Ir), aluminum (Al), or platinum (Pt). In other embodiments, the gate metal 226 includes a metal or metal alloy selected from one or more of nitrogen (N), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), ruthenium (Ru), hafnium (Hf), or zirconium (Zr).

[0079] In an embodiment where the gate metal is formed on the high-K dielectric layer 212, the gate metal is deposited as a gate metal layer (not shown). The gate metal layer may be deposited using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin coating, or other insulating layer deposition techniques known to those skilled in the art. The gate metal layer may have any suitable thickness. In some embodiments, the gate metal layer has a thickness in the range of from 1 nm to 3 nm. In an embodiment where the gate metal is formed on the high-K dielectric layer 212, the gate metal layer has a capping layer thereon. The capping layer formed on the gate metal layer may have the same or similar properties as the capping layer 216 depicted in the accompanying drawings. The capping layer (e.g., capping layer 216) on the gate metal layer may have any suitable thickness. In some embodiments, the capping layer on the gate metal layer (e.g., capping layer 216) has a thickness in a range from 0.5 nm to 2 nm, including in a range from 0.6 nm to 1.9 nm, in a range from 0.7 nm to 1.8 nm, in a range from 0.8 nm to 1.7 nm, in a range from 0.9 nm to 1.6 nm, in a range from 1 nm to 1.5 nm, in a range from 1.1 nm to 1.4 nm, or in a range from 1.2 nm to 1.3 nm.

[0080] In one or more embodiments, the gate contact can be any suitable material known to those skilled in the art. In one or more embodiments, the gate contact comprises an element or alloy selected from one or more of nitrogen (N), copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), iridium (Ir), tantalum (Ta), aluminum (Al), or platinum (Pt).

[0081] Additional embodiments of the present disclosure relate to a processing tool 900 for forming electronic devices and described methods, such as Figure 4 shown.

[0082] The cluster tool 900 includes at least one central transfer station 921, 931 with multiple sides. Robots 925, 935 are positioned within the central transfer station 921, 931 and are configured to move robot blades and wafers to each of the multiple sides.

[0083] The cluster tool 900 includes a plurality of processing chambers 902, 904, 906, 908, 910, 912, 914, 916, and 918, also referred to as processing stations, connected to a central transfer station. The various processing chambers provide separate processing areas isolated from adjacent processing stations. The processing chambers may be any suitable chambers, including but not limited to pre-clean chambers, buffer chambers, transfer spaces, wafer orienters / degas chambers, cryogenic cooling chambers, deposition chambers, annealing chambers, etching chambers, thermal treatment (RTP) chambers, plasma oxidation chambers, plasma nitridation chambers, and atomic layer deposition (ALD) chambers. The specific arrangement of processing chambers and components may vary depending on the cluster tool and should not be taken as limiting the scope of the present disclosure.

[0084] exist Figure 4 In the illustrated embodiment, the factory interface 950 is connected to the front of the cluster tool 900. The factory interface 950 includes a loading chamber 954 and an unloading chamber 956 on the front 951 of the factory interface 950. Although the loading chamber 954 is shown on the left and the unloading chamber 956 is shown on the right, those skilled in the art will understand that this is only representative of one possible configuration.

[0085] The size and shape of the load chamber 954 and the unload chamber 956 may vary depending, for example, on the substrates being processed in the cluster tool 900. In the illustrated embodiment, the load chamber 954 and the unload chamber 956 are sized to hold a wafer cassette with a plurality of wafers positioned therein.

[0086] A robot 952 is within the factory interface 950 and can move between a loading chamber 954 and an unloading chamber 956. The robot 952 can move wafers from a cassette in the loading chamber 954 through the factory interface 950 to a load lock chamber 960. The robot 952 can also move wafers from a load lock chamber 962 through the factory interface 950 to a cassette in the unloading chamber 956. As will be appreciated by one skilled in the art, the factory interface 950 can have more than one robot 952. For example, the factory interface 950 can have a first robot that moves wafers between the loading chamber 954 and the load lock chamber 960, and a second robot that moves wafers between the load lock 962 and the unloading chamber 956.

[0087] The cluster tool 900 shown has a first section 920 and a second section 930. The first section 920 is connected to the factory interface 950 through the load lock chambers 960, 962. The first section 920 includes a first transfer chamber 921 with at least one robot 925 positioned therein. The robot 925 is also referred to as a robot wafer transfer mechanism. The first transfer chamber 921 is centrally positioned relative to the load lock chambers 960, 962, the processing chambers 902, 904, 916, 918, and the buffer chambers 922, 924. The robot 925 of some embodiments is a multi-arm robot capable of independently moving more than one wafer at a time. In one or more embodiments, the first transfer chamber 921 includes more than one robot wafer transfer mechanism. The robot 925 in the first transfer chamber 921 is configured to move wafers between chambers surrounding the first transfer chamber 921. Individual wafers are carried on a wafer transfer blade located at a distal end of the first robot mechanism.

[0088] After processing the wafer in the first section 920, the wafer may be transferred through a pass-through chamber to the second section 930. For example, the chambers 922, 924 may be one-way or two-way pass-through chambers. The pass-through chambers 922, 924 may be used, for example, to cryogenically cool the wafer prior to processing in the second section 930 or to allow the wafer to cool or post-process prior to moving back to the first section 920.

[0089] The system controller 990 is in communication with the first robot 925, the second robot 935, the first plurality of processing chambers 902, 904, 916, 918, and the second plurality of processing chambers 906, 908, 910, 912, 914. The system controller 990 may be any suitable component capable of controlling the processing chambers and the robot. For example, the system controller 990 may be a computer including a central processing unit, memory, suitable circuitry, and storage.

[0090] The process may be typically stored in a memory of the system controller 990 as a software program, which, when executed by a processor, causes the processing chamber to perform the process of the present disclosure. The software program may also be stored and / or executed by a second processor (not shown), which is located at a remote end of the hardware controlled by the processor. Some or all of the methods of the present disclosure may also be executed in hardware. Therefore, the process may be implemented in software and implemented in hardware using a computer system as, for example, an ASIC or other type of hardware implementation, or as a combination of software or hardware. When executed by a processor, the software program transforms a general-purpose computer into a special-purpose computer (controller), which controls the chamber operation so that the process is executed.

[0091] In one or more embodiments, the processing tool 900 includes a central transfer station 921, 931, which includes at least one robot 925, 935, which is configured to deposit an interface layer on the top surface of the channel between the source and the drain on the substrate; deposit a high-K dielectric layer on the interface layer; deposit a dipole layer on the high-K dielectric layer by exposing the substrate to alternating cycles of a metal precursor and a nitrogen-containing reactant; perform a free radical treatment; optionally, deposit a cap layer on the dipole layer; or anneal the substrate. In further embodiments, at least one robot 925, 935 is configured to perform an etching process to remove one or more of the cap layer or the dipole layer. In embodiments where the cap layer is not present, at least one robot 925, 935 is configured to perform an etching process to remove the dipole layer. In one or more embodiments, at least one robot 925, 935 is configured to form or deposit a gate including one or more gate metals (not shown) or gate contacts (not shown) on the exposed surface of the high-K dielectric layer after removing one or more of the capping layer or the dipole layer.

[0092] One or more embodiments of the present disclosure are directed to a non-transitory computer-readable medium including instructions that, when executed by a controller of a processing chamber, cause the processing chamber to perform the operations of method 100. In some embodiments, the non-transitory computer-readable medium includes instructions that, when executed by a controller of the processing chamber, cause the processing chamber to perform the following operations: deposit an interfacial layer on a top surface of a channel between a source and a drain on a substrate (operation 102); deposit a high-K dielectric layer on the interfacial layer (operation 104); deposit a dipole layer on the high-K dielectric layer by exposing the substrate to alternating cycles of a metal precursor and a nitrogen-containing reactant (operation 106); perform a free radical treatment (not shown); optionally, deposit a cap layer on the dipole layer (operation 108); or anneal the substrate (operation 110).

[0093] In further embodiments, the non-transitory computer readable medium includes instructions that, when executed by a controller of the processing chamber, cause the processing chamber to perform the following operations: perform an etching process to remove the cap layer and the dipole layer. In embodiments where the cap layer is not present, the non-transitory computer readable medium includes instructions that, when executed by a controller of the processing chamber, cause the processing chamber to perform the following operations: perform an etching process to remove the dipole layer.

[0094] In a further embodiment, the non-transitory computer readable medium includes instructions that, when executed by a controller of a processing chamber, cause the processing chamber to perform the following operations: after removing one or more of the capping layer or the dipole layer, form or deposit a gate including one or more of a gate metal (not shown) or a gate contact (not shown) on an exposed surface of the high-K dielectric layer.

[0095] Spatially relative terms such as "below," "beneath," "lower," "above," "over," and similar terms may be used herein to simplify descriptions of the relationship of one element or feature relative to another element or feature as depicted in the accompanying drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned upside down, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" may encompass both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein are interpreted accordingly.

[0096] The use of the terms "a" and "an" and "the" and similar designators in the context of describing the materials and methods discussed herein (particularly in the context of the claims that follow) is intended to be constructed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. The numerical ranges mentioned herein are intended only as a shorthand method of individually referring to each separate value falling within the range, unless otherwise indicated herein, each separate value is incorporated into this specification as if it were individually referred to herein. All methods described herein can be performed in any suitable order, unless otherwise indicated herein or clearly contradicted by context. The use of any and all examples or exemplary language (e.g., "such as") provided herein is intended only to better illustrate the materials and methods, and does not impose limitations on the scope unless otherwise stated. No language in this specification should be construed to indicate that any non-declared element is essential to the implementation of the disclosed materials and methods.

[0097] References throughout this specification to "one embodiment," "some embodiments," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described with respect to that embodiment is included in at least one embodiment of the present disclosure. Thus, the appearance of phrases such as "in one or more embodiments," "in some embodiments," "in one embodiment," or "in an embodiment" in various places throughout this specification do not necessarily refer to the same embodiment of the present disclosure. In one or more embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner.

[0098] Although the present disclosure has been described herein with reference to specific embodiments, it will be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. Various modifications and variations may be made to the methods and apparatus of the present disclosure without departing from the spirit and scope of the present disclosure, as will be apparent to those skilled in the art. Therefore, the present disclosure is intended to include modifications and variations that fall within the scope of the appended claims and their equivalents.

Claims

1. A method for manufacturing an electronic device, the method comprising the following steps: depositing an interfacial layer on a top surface of a channel, the channel being located between a source electrode and a drain electrode on a substrate; depositing a high-K dielectric layer on the interface layer; depositing a dipole layer on the high-K dielectric layer by exposing the substrate to alternating cycles of a metal precursor and a nitrogen-containing reactant, the metal precursor comprising one or more of strontium (Sr), yttrium (Y), ytterbium (Yb), antimony (Sb), or tellurium (Te); and The substrate is annealed at a temperature less than or equal to 1050° C. to drive atoms from the dipole layer into the high-K dielectric layer.

2. The method of claim 1, wherein the interface layer comprises a dielectric material selected from one or more of silicon (Si), silicon oxide (SiOx), doped silicon, doped silicon oxide, or spin-on dielectric.

3. The method of claim 1, wherein the high-K dielectric layer comprises one or more of hafnium oxide (HfOx), zirconium oxide (ZrOx), or hafnium zirconium oxide (HfZrOx).

4. The method of claim 1, wherein the metal precursor comprises one or more of strontium imidazole, strontium amidinate, strontium bisamidinate, strontium cyclopentadienyl, or strontium bis(triisopropylcyclopentadienyl).

5. The method of claim 1, wherein the metal precursor comprises one or more of yttrium formamidine, yttrium (III) tri(N,N′-di-isopropylformamidine), yttrium tricyclopentadienyl, yttrium tri(butylcyclopentadienyl), yttrium tri(methylcyclopentadienyl), or yttrium tri(n-propylcyclopentadienyl).

6. The method of claim 1, wherein the metal precursor comprises one or more of ytterbium formamidinium, ytterbium (III) tris(N,N'-di-isopropylformamidinium), or cyclopentadienyl ytterbium.

7. The method of claim 1, wherein the metal precursor comprises one or more of antimony trichloride, antimony pentachloride, or tris(trimethylsilyl)antimony.

8. The method of claim 1, wherein the metal precursor comprises one or more of bis(trimethylsilyl)tellurium or di(tert-butyl)tellurium.

9. The method of claim 1, wherein the metal precursor comprises one or more of strontium (Sr), yttrium (Y), ytterbium (Yb), antimony (Sb) and the nitrogen-containing reactant comprises one or more of nitrogen (N2), ammonia (NH3), hydrazine (N2H4), or a co-current of nitrogen radicals (N2*) and hydrogen radicals (H2*).

10. The method of claim 1, wherein the dipole layer is deposited on the high-K dielectric layer by atomic layer deposition (ALD) at a temperature less than or equal to 500°C and at a pressure less than or equal to 50 Torr.

11. The method of claim 1, further comprising the step of performing a free radical treatment to remove carbides, nitrides, or oxides from the dipole layer.

12. The method of claim 1, further comprising the step of depositing a cap layer on the dipole layer.

13. The method of claim 12, wherein the cap layer comprises one or more of amorphous silicon, a metal, a metal carbide, a metal nitride, or a metal oxide.

14. An electronic device comprising: an interface layer on a top surface of a channel, wherein the channel is located between a source electrode and a drain electrode on a substrate; a high-K dielectric layer, the high-K dielectric layer being on the interface layer; a dipole layer on the high-K dielectric layer, the dipole layer comprising one or more of strontium (Sr), yttrium (Y), ytterbium (Yb), antimony (Sb), or tellurium (Te); and Optionally, a cap layer, the cap layer being on the dipole layer.

15. The electronic device of claim 14, wherein the interface layer comprises a dielectric material selected from one or more of silicon (Si), silicon oxide (SiOx), doped silicon, doped silicon oxide, or spin-on dielectric. 16 . The electronic device of claim 15 , wherein the interface layer has a thickness in a range of 0.2 nm to 0.8 nm. 17 . The electronic device of claim 14 , wherein the high-K dielectric layer comprises one or more of hafnium oxide (HfOx), zirconium oxide (ZrOx), or hafnium zirconium oxide (HfZrOx). 18 . The electronic device of claim 17 , wherein the high-K dielectric layer has a thickness in a range of 1 nm to 2 nm.

19. The electronic device of claim 14, wherein the dipole layer has a thickness in a range of 0.3 nm to 1.5 nm.

20. The electronic device of claim 14, wherein the electronic device comprises the capping layer and the capping layer has a thickness in a range of 0.5 nm to 2 nm.

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