A digital signal processing platform based on FPGA

Abstract

The application provides a kind of digital signal processing platform based on FPGA, it is related to the technical field of airborne computer, including: analog circuit control module, frequency channel acquisition module and pattern recognition and initialization unit, analog circuit control module and frequency channel acquisition module are connected with pattern recognition and initialization unit respectively;Pattern recognition and initialization unit connects external input signal, for identifying external input signal and initializing platform, external input signal includes platform mode selection signal, pattern recognition and initialization unit is connected to the parallel bus interface and serial bus interface respectively, and pattern recognition and initialization unit is also connected to parallel bus interface and serial bus interface through serial-parallel protocol conversion control module respectively.The application can realize mode conversion according to the running state of airborne system, to adapt to the data conversion and data transmission requirements of airborne avionics system at different positions or different time.

Description

Technical Field

[0001] The present invention relates to the technical field of aviation airborne computers, and in particular to a digital signal processing platform based on FPGA. Background Art

[0002] Avionics systems primarily include subsystems such as hydraulics, transmissions, fuel systems, and auxiliary power units (APUs). Aircraft computers monitor the functional status of these subsystems using discrete, analog, and frequency parameters. Data exchange between digital signal processing platforms within the airborne computer varies, with interface states varying across time and space. Therefore, the digital signal processing platform must accommodate data transmission across the airborne computer under varying interface conditions. Furthermore, it must ensure redundancy in signal processing and data transmission during idle interface conditions, thereby enhancing the reliability and flexibility of the airborne computer.

[0003] Currently in the field of avionics, digital signal processing platforms are simple in type, single in structure, and poor in portability. Airborne computer host interfaces are relatively abundant, and resource utilization is low. Summary of the Invention

[0004] In light of this, embodiments of the present application provide an FPGA-based digital signal processing platform that can switch modes based on the operating state of the onboard system to adapt to the data conversion and data transmission requirements of the onboard avionics system at different locations or times. This improves the system's safety and reliability, and provides a certain degree of portability in other system designs.

[0005] The present application provides the following technical solution: an FPGA-based digital signal processing platform, comprising: an analog circuit control module, a frequency channel acquisition module, and a pattern recognition and initialization unit, wherein the analog circuit control module is used to implement switching and conversion control of analog channels, and the frequency channel acquisition module is used to acquire and convert frequencies to implement status monitoring of an airborne auxiliary power unit; the analog circuit control module and the frequency channel acquisition module are respectively connected to the pattern recognition and initialization unit;

[0006] The mode recognition and initialization unit is connected to an external input signal and is used to recognize the external input signal and initialize the platform. The external input signal includes a platform mode selection signal. The mode recognition and initialization unit is respectively connected to an external parallel bus interface and a serial bus interface. The mode recognition and initialization unit is also respectively connected to the parallel bus interface and the serial bus interface through a serial-parallel protocol conversion control module. The platform mode selection signal includes a parallel bus connection mode signal, a serial bus connection mode signal, and a serial and parallel bus connection mode signal.

[0007] The mode identification and initialization unit is used to determine the current platform operating mode according to the platform mode selection signal; when the platform mode selection signal is a parallel bus connection mode signal, the external host accesses the analog circuit control module and the frequency channel acquisition module through the parallel bus interface, or accesses the slave device connected to the serial bus interface through the serial-parallel protocol conversion control module; when the platform mode selection signal is a serial bus connection mode signal, the external host accesses the analog circuit control module and the frequency channel acquisition module through the serial bus interface, or accesses the slave device connected to the parallel bus interface through the serial-parallel protocol conversion control module; when the platform mode selection signal is a serial and parallel bus connection mode signal, the external host realizes platform internal data access interaction through the serial bus interface and the parallel bus interface, thereby realizing dual redundancy of data transmission.

[0008] According to one embodiment of the present application, the external input signal also includes a platform mode switching signal. When the mode recognition and initialization unit receives the platform mode switching signal, it switches the current platform working mode. During the process of switching the platform working mode, the platform enters a stop working state and resumes working after the mode switching is completed.

[0009] According to one embodiment of the present application, the external input signal also includes a platform reset signal. When the mode recognition and initialization unit receives the platform reset signal, it initializes the analog circuit control module, the frequency channel acquisition module, the parallel bus interface, the serial bus interface and the serial-parallel protocol conversion control module respectively.

[0010] According to an embodiment of the present application, 64 readable registers are set in the analog circuit control module, and the register bit width is 32 bits to store the sampling values ​​of 64 analog channels.

[0011] According to an embodiment of the present application, 8 readable registers are set in the frequency channel acquisition module, and the register bit width is 32 bits to record the final calculated values ​​of the 8 frequency channels.

[0012] According to an embodiment of the present application, the single channel of the frequency channel acquisition module continuously acquires 16 adjacent frequency values, performs sliding window filtering on the 16 frequency values, and outputs the final frequency value to a readable register through a sliding window filtering algorithm.

[0013] According to one embodiment of the present application, the serial bus interface integrates an RS232 controller.

[0014] According to an embodiment of the present application, the bus clock frequency of the parallel bus interface is 66 MHz, the data bit width is 32 bits, and the address bit width is 27 bits.

[0015] Compared with existing technologies, the at least one technical solution employed in the embodiments of this specification can achieve at least the following beneficial effects: The embodiments of the present invention provide an FPGA-based digital signal processing platform that can implement mode switching based on the operating state of the airborne system to adapt to the data conversion and data transmission requirements of the airborne avionics system at different locations or times. This improves the system's safety and reliability and provides a certain degree of portability in other system designs. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0017] Figure 1 This is a schematic diagram of the system architecture of a digital signal processing platform based on FPGA according to an embodiment of the present invention;

[0018] Figure 2 Schematic diagram of initialization and state transition actions according to an embodiment of the present invention. DETAILED DESCRIPTION

[0019] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0020] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the features in the following embodiments and embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative work are within the scope of protection of this application.

[0021] like Figure 1As shown, an embodiment of the present invention provides an FPGA-based digital signal processing platform, comprising: an analog circuit control module, a frequency channel acquisition module, and a pattern recognition and initialization unit. The analog circuit control module is used to implement switching and conversion control of analog channels, and the frequency channel acquisition module is used for frequency acquisition and conversion to implement status monitoring of an airborne auxiliary power unit. The analog circuit control module and the frequency channel acquisition module are respectively connected to the pattern recognition and initialization unit.

[0022] The mode recognition and initialization unit is connected to an external input signal and is used to recognize the external input signal and initialize the platform. The external input signal includes a platform mode selection signal. The mode recognition and initialization unit is respectively connected to an external parallel bus interface and a serial bus interface. The mode recognition and initialization unit is also respectively connected to the parallel bus interface and the serial bus interface through a serial-parallel protocol conversion control module. The platform mode selection signal includes a parallel bus connection mode signal, a serial bus connection mode signal, and a serial and parallel bus connection mode signal.

[0023] The mode identification and initialization unit is used to determine the current platform operating mode according to the platform mode selection signal; when the platform mode selection signal is a parallel bus connection mode signal, the external host accesses the analog circuit control module and the frequency channel acquisition module through the parallel bus interface, or accesses the slave device connected to the serial bus interface through the serial-parallel protocol conversion control module; when the platform mode selection signal is a serial bus connection mode signal, the external host accesses the analog circuit control module and the frequency channel acquisition module through the serial bus interface, or accesses the slave device connected to the parallel bus interface through the serial-parallel protocol conversion control module; when the platform mode selection signal is a serial and parallel bus connection mode signal, the external host realizes platform internal data access interaction through the serial bus interface and the parallel bus interface, thereby realizing dual redundancy of data transmission.

[0024] The present invention provides an FPGA-based signal processing platform capable of multi-channel digital signal transmission and parallel / serial bus data transmission. This platform allows for simultaneous data exchange when host interfaces are available, improving system reliability. Furthermore, when host interfaces are limited, the platform can be expanded to connect external slave devices, improving host interface resource utilization. This platform offers a certain degree of flexibility and compatibility in airborne computer applications.

[0025] In the digital signal processing platform of this embodiment of the present invention, the analog circuit control module implements switching and conversion control of analog channels for external fuel systems, hydraulic systems, and other systems. The frequency channel module monitors the status of the onboard auxiliary power unit (APU). The platform can switch between different operating scenarios based on the output signals of the main control chip. External interfaces can be defined as host interfaces, external expansion interfaces, or data transmission redundancy, depending on the application scenario.

[0026] Specifically, in this embodiment, the FPGA has platform mode selection, mode switching, and module initialization functions.

[0027] In this embodiment, the input signals include a platform mode selection signal (MODE_SEL[1:0]), a platform mode switching signal (MCHAN), a platform reset signal (RST), a data error signal (DATA_ERROR) (for the mode recognition and initialization unit), an 8-channel frequency input signal (for the frequency channel acquisition module) (FREQUENCY[8:1]), an A / D busy signal (AD_BUSY), an A / D conversion output digital quantity (AD_DATA[31:0]), etc. (for the analog circuit control module).

[0028] The mode identification and initialization unit determines the platform operating mode by reading the platform mode selection signal (MODE_SEL[1:0]) during the platform initialization process until the next platform reset. The platform mode is switched by the platform mode switching signal during the platform operation process.

[0029] When the mode recognition and initialization unit receives the platform mode switching signal, it switches the current platform working mode. During the process of switching the platform working mode, the platform enters a stop working state and resumes working after the mode switching is completed.

[0030] When receiving the platform reset signal, the pattern recognition and initialization unit initializes the analog circuit control module, the frequency channel acquisition module, the parallel bus interface, the serial bus interface and the serial-parallel protocol conversion control module respectively.

[0031] The judgment logic for the data error signal (DATA_ERROR) is: the sampled value (DATA[X]) exceeds the data range. When the data error signal is valid, the analog circuit control switch opens the channel for repeated sampling. If 10 consecutive sample values ​​are incorrect, the corresponding data position of the A / D channel fault signal (ADCH_ERROR) sent to the host is set to 0. Accordingly, the host stops reading the A / D sampling channel data at position 0. In this platform design, readable registers can realize the retransmission of incorrect values. If 10 repeated samples are incorrect, the channel fault is marked, and the faulty channel acquisition is cut off in subsequent state machine polling.

[0032] In some embodiments, the external input signal is subjected to signal delay and anti-shake processing after entering the FPGA to eliminate glitches.

[0033] In this embodiment, the output signals include platform mode status signal (STATE_COND[1:0]), platform initialization completion signal (INIT_COMPLETE), A / D channel control signal (AD_CHC[12:1]), A / D channel fault signal (ADCH_ERROR), A / D sampling selection signal (AD_CS), A / D sampling start signal (AD_RC), etc.

[0034] During the initialization process, the mode recognition and initialization unit initializes the internal registers and state machine of the platform, and cross-links the functional modules and interfaces according to the mode selection.

[0035] In some embodiments, the analog circuit control module includes 64 readable registers (DATA[X], where X=1...64), each 32 bits wide, to store the sampled values ​​of 64 analog channels. These 64 readable registers are periodically updated, with the update period configurable via the bus interface. The analog circuit signals enable control of 64 analog channels, data transmission waiting, and resampling of error values.

[0036] In some embodiments, the frequency channel acquisition module includes eight readable registers (FRE[X], X=1...8), each 32 bits wide, to record the final calculated values ​​of the eight frequency channels. Frequency channel acquisition can convert the eight-channel frequency signals into digital quantities, and implement pulse interference prevention sliding window filtering on a single channel.

[0037] In some embodiments, the serial bus interface of the platform integrates an RS232 controller. In addition, the serial bus can achieve automatic transmission rate negotiation in any mode.

[0038] In some embodiments, the parallel bus interface of the platform has a parallel bus clock of 66 MHz, a data bit width of 32 bits, and an address bit width of 27 bits.

[0039] In some embodiments, the single channel of the frequency channel acquisition module continuously acquires 16 consecutive frequency values, performs sliding window filtering on the 16 frequency values, and outputs the final frequency value to a readable register through the sliding window filtering algorithm. The specific operation method is to delete the maximum and minimum values ​​of the 16 values ​​to eliminate signal jitter. The final frequency during the 16 sampling periods is f = 14 / (1 / f1+1 / f2+.....1 / f 14 ).

[0040] like Figure 1 As shown, Figure 1 A schematic diagram of the platform's system architecture is provided. After the reset signal (RST) is released, the platform's mode identification and initialization module initializes the analog circuit controller, frequency channel acquisition module, and interfaces based on the platform's mode selection signal (MODE_SEL[1:0]). During platform operation, the system can be switched based on the mode switch signal (MCHAN). During this switching process, the platform enters a stopped state and resumes operation after the state switch is complete.

[0041] like Figure 2 As shown, Figure 2 A schematic diagram of the platform's mode initialization and state switching is provided. The initialization and conversion input signals are MODE_SEL[1:0] and MCHAN. When the mode selection signal (MODE_SEL[1:0] = 00) is in MODE1, when MODE_SEL[1:0] = 01, it is MODE2, and when MODE_SEL[1:0] = 10, it is MODE3. After the signal is established, the corresponding initialization actions are performed on each module. After platform initialization is complete, the INIT_COMPLETE signal is enabled. During system state switching, MCHAN defaults to a high level. After 100ms of a low level, the system enters the sequential mode switching phase, with the modes switching in the order: MODE1 > MODE2 > MODE3. After 200ms of a low level, the system enters the reverse mode switching phase, with the modes switching in the reverse order: MODE3 > MODE2 > MODE1. Similarly, during the mode switching process, the platform enters the stopped state. After the switch is complete, the platform mode status signal (STATE_COND[1:0]) is enabled to notify the host of the platform's current mode.

[0042] The working modes of the FPGA-based digital signal processing platform of the embodiment of the present invention include:

[0043] (1) MODE1: In this state, the host is connected to the platform parallel interface. The host accesses the A / D channel control module register, frequency acquisition channel register, platform status register, channel fault register, etc. through the parallel interface. At the same time, the host can access the serial slave device through parallel-to-serial protocol conversion.

[0044] (2) MODE2: In this state, the host is connected to the platform serial interface. The host accesses the A / D channel control module register, frequency acquisition channel register, platform status register, channel fault register, etc. through the serial interface. At the same time, the host can access the parallel slave device through serial-to-parallel protocol conversion.

[0045] (3) MODE3: In this state, the host is connected to the serial interface and parallel interface of the platform, and can simultaneously implement platform internal data access interaction through the serial interface or parallel interface, achieving dual redundancy of data transmission. The two interfaces are mutually redundant to achieve data transmission robustness.

[0046] like Figure 2 As shown, after the MODE1 state is established, the readable registers of the analog control module and the frequency channel module are connected to the parallel bus, and the serial-to-parallel protocol conversion controller is also connected to the parallel bus. After the MODE2 state is established, the readable registers of the analog control module and the frequency channel module are connected to the serial bus, and the parallel-to-serial protocol conversion controller is also connected to the serial bus. After the MODE3 state is established, both parallel and serial bus register reads and writes are enabled. Register read arbitration is enabled. When read and write operations are simultaneously active, the arbitration criterion is: write operation > parallel bus read > serial bus read.

[0047] In this embodiment, the analog circuit control module implements analog channel control and sampling timing control. The internal channel state machine sequentially selects and controls the external 64-channel analog quantity through the A / D channel control signal (AD_CHC[12:1]). The channel state machine has a total of 64 states, and the internal conversion unit state machine is nested. The A / D sampling select signal (AD_CS) and the A / D sampling start signal (AD_RC) serve as the output signals of the conversion unit state machine. After the channel switching is stable, the conversion is started and the conversion value is read and written to the readable register. If the host reads the value continuously with errors, an A / D channel fault signal (ADCH_ERROR) is issued, and the channel conversion state machine is automatically terminated accordingly.

[0048] To meet the high safety and efficiency requirements of products, the analog unit and frequency channel output values ​​in this embodiment of the present invention can be reported via either a parallel bus or a serial bus. The serial bus port can transmit via RS232, and the platform can auto-negotiate the rate during RS232 reception. Therefore, it is suitable for both serial and parallel data communication scenarios, with the platform implementing different initialization modes based on the application scenario. This strategy simplifies the hardware structure and improves system flexibility and compatibility.

[0049] The embodiment of the present invention provides an FPGA-based airborne computer signal processing data access strategy, which can be applied to host access scenarios of serial / parallel buses and to time-sharing operations of airborne mechatronic system interfaces. It has certain unified significance on the airborne computer signal processing platform of the mechatronic system and has certain flexibility in design, application and use.

[0050] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A digital signal processing platform based on FPGA, characterized in that: include: An analog circuit control module, a frequency channel acquisition module, and a pattern recognition and initialization unit. The analog circuit control module is used to implement switching and conversion control of analog channels, and the frequency channel acquisition module is used for frequency acquisition and conversion to implement status monitoring of the airborne auxiliary power unit. The analog circuit control module and the frequency channel acquisition module are respectively connected to the pattern recognition and initialization unit. The mode recognition and initialization unit is connected to an external input signal and is used to recognize the external input signal and initialize the platform. The external input signal includes a platform mode selection signal. The mode recognition and initialization unit is respectively connected to an external parallel bus interface and a serial bus interface. The mode recognition and initialization unit is also respectively connected to the parallel bus interface and the serial bus interface through a serial-parallel protocol conversion control module. The platform mode selection signal includes a parallel bus connection mode signal, a serial bus connection mode signal, and a serial and parallel bus connection mode signal. The mode identification and initialization unit is used to determine the current platform operating mode according to the platform mode selection signal; when the platform mode selection signal is a parallel bus connection mode signal, the external host accesses the analog circuit control module and the frequency channel acquisition module through the parallel bus interface, or accesses the slave device connected to the serial bus interface through the serial-parallel protocol conversion control module; when the platform mode selection signal is a serial bus connection mode signal, the external host accesses the analog circuit control module and the frequency channel acquisition module through the serial bus interface, or accesses the slave device connected to the parallel bus interface through the serial-parallel protocol conversion control module; when the platform mode selection signal is a serial and parallel bus connection mode signal, the external host realizes platform internal data access interaction through the serial bus interface and the parallel bus interface, thereby realizing dual redundancy of data transmission.

2. The FPGA-based digital signal processing platform according to claim 1, characterized in that: The external input signal also includes a platform mode switching signal. When the mode recognition and initialization unit receives the platform mode switching signal, it switches the current platform working mode. During the process of switching the platform working mode, the platform enters a stop working state and resumes working after the mode switching is completed.

3. The FPGA-based digital signal processing platform according to claim 1, characterized in that: The external input signal also includes a platform reset signal. When the mode recognition and initialization unit receives the platform reset signal, it initializes the analog circuit control module, the frequency channel acquisition module, the parallel bus interface, the serial bus interface and the serial-parallel protocol conversion control module respectively.

4. The FPGA-based digital signal processing platform according to claim 1, characterized in that: The analog circuit control module is provided with 64 readable registers, each of which has a width of 32 bits, so as to store the sampled values ​​of the 64 analog channels.

5. The FPGA-based digital signal processing platform according to claim 1, characterized in that: The frequency channel acquisition module is provided with 8 readable registers, each of which has a width of 32 bits, to record the final calculated values ​​of the 8 frequency channels.

6. The FPGA-based digital signal processing platform according to claim 5, characterized in that: The single channel of the frequency channel acquisition module continuously acquires 16 adjacent frequency values, performs sliding window filtering on the 16 frequency values, and outputs the final frequency value to a readable register through a sliding window filtering algorithm.

7. The FPGA-based digital signal processing platform according to claim 1, characterized in that: The serial bus interface integrates an RS232 controller.

8. The FPGA-based digital signal processing platform according to claim 1, characterized in that: The parallel bus interface has a bus clock frequency of 66 MHz, a data bit width of 32 bits, and an address bit width of 27 bits.

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