Digital low dropout regulator

Abstract

The present disclosure relates to a digital low dropout regulator for receiving a reference voltage and generating an output voltage, comprising: a comparison circuit configured to receive the reference voltage, receive a feedback voltage, the feedback voltage dependent on the output voltage, compare the reference voltage and the feedback voltage, generate an error signal dependent on a comparison between the reference voltage and the feedback voltage; a first digital-to-analog converter configured to be operable in a panic mode, where the first digital-to-analog converter is configured to receive the error signal, generate a first DAC code signal based on the error signal within a first time period, the output voltage dependent on the first DAC code signal, and generate a second DAC code signal based on the second time period. And calculating an average value of the generated first DAC code signal during at least a portion of the first time period, setting the first DAC code signal as the calculated average value; and the panic circuit is configured to detect when the feedback voltage exceeds a first threshold value or drops to be lower than a second threshold value, and when the feedback voltage exceeds the first threshold value or drops to be lower than the second threshold value, the first digital-to-analog converter is controlled to work in a panic mode.

Description

[0001] The present disclosure relates to a digital low dropout regulator (LDO). In particular, the present disclosure relates to a digital LDO that can operate during a panic condition.

[0002] background

[0003] FIG. 1( a ) shows a digital LDO 100 known in the prior art (Jun Liu et al., A Fully-Synthesizable 0.6V Digital LDO with Dual-Loop Control using Digital Standard Cells, 2016 14th IEEE International Conference on New Circuits and Systems (NEWCAS), Vancouver, BC, Canada, 2016, pp. 1-4).

[0004] LDO 100 includes a main comparator 102; shift registers 104, 106; a counter 108; a buffer 110; transistors 112, 114, 116, 118; a panic circuit 120 including comparators 122, 124 and a logic block 126; a clock circuit 128 including a multiplexer 130 and a frequency scaler 132; and a capacitor Co having an equivalent series resistance (ESR) Ro.

[0005] The LDO 100 uses a coarse digital-to-analog converter (DAC) 134 and a fine DAC 136 , each driven by an up-down counter 104 , 106 and a clocking scheme 128 that times the response to a “panic” detected by a window comparator provided by the panic circuit 120 .

[0006] The main control loop is a single comparator 102 (or 1-bit ADC) that compares the feedback voltage VFB derived from the output voltage VLDO with the target voltage VREF.

[0007] The operation of the up-down counters 104, 106 acts as an integrating function of the error signal CMP, so that the stability of the loop depends on the zeroing of the external decoupling capacitor Co, which has an ESR denoted by Ro.

[0008] When a “panic” is detected, i.e., the output voltage VLDO has exceeded the range defined by the window comparator 120, the coarse up-down counter 104 and the fine up-down counter 106 are clocked at the full clock speed CLK, and the output current is ramped towards a new target value (up or down) under the control of the main comparator output CMP.

[0009] Since the output of the DAC 134, 136 is essentially a current source provided by the transistors 112, 114, 116, 118, the output voltage VLDO is the integral of this current, so the control is 90° phase shifted relative to the output voltage VLDO. Typically, the result is a limit cycle of the DAC code. Since the capacitor Co has a certain ESR (denoted by Ro), the amplitude of the limit cycling period is reduced to a stable state. However, the "panic" mode fast timing is one timing cycle, which is 32 clock cycles in this example. When the "panic" fast timing times out, the fine loop 136 operates at 1 / 32 of the clock speed.

[0010] The coarse DAC output and fine DAC output are controlled using a current mirror scheme. This has two benefits:

[0011] 1. It aligns the switching operation and the dynamics of the LDO and makes the performance as expected.

[0012] 2. It reduces the PSRR sensitivity of the output stage.

[0013] FIG1( b) is a schematic diagram of a current mirror scheme 138 for controlling coarse and fine DAC outputs as known in the prior art (Xiangyu Mao et al., A 1.2-A Calibration-Free Hybrid LDO With In-Loop Quantization and Auxiliary Constant Current Control Achieving High Accuracy and Fast DVS, IEEE Transactions on Circuits and Systems-I: General Papers, Vol. 69, No. 11, November 2022).

[0014] The current mirror scheme 138 includes a transistor 140 , a current source 142 , a capacitor 144 , an amplifier 146 , and an absorption buffer 148 .

[0015] Overview

[0016] It is desirable to provide a digital LDO having reduced limit cycling at the end of fast clock cycles compared to known systems.

[0017] According to a first aspect of the present disclosure, there is provided a digital low dropout regulator (LDO) for receiving a reference voltage and generating an output voltage, comprising: a comparison circuit configured to receive a reference voltage, receive a feedback voltage, the feedback voltage being dependent on an output voltage, compare the reference voltage and the feedback voltage, and generate an error signal dependent on the comparison between the reference voltage and the feedback voltage; a first digital-to-analog converter configured to be capable of operating in a panic mode, wherein the first digital-to-analog converter is configured to receive an error signal, generate a first DAC code signal based on the error signal within a first time period, the output voltage being dependent on the first DAC code signal, and calculate an average value of the generated first DAC code signal during at least a portion of the first time period, and set the first DAC code signal to the calculated average value; a panic circuit configured to detect when the feedback voltage exceeds a first threshold or drops below a second threshold, and when the feedback voltage exceeds the first threshold or drops below the second threshold, control the first digital-to-analog converter to operate in the panic mode.

[0018] Optionally, the comparison circuit includes a main comparator or a 1-bit analog-to-digital converter.

[0019] Optionally, the first digital-to-analog converter comprises a first shift register configured to generate a first DAC code signal.

[0020] Optionally, the first shift register comprises an up-down counter.

[0021] Optionally, the first digital-to-analog converter includes a plurality of first current sources, wherein each first current source is used as 1 bit of the first DAC code signal.

[0022] Optionally, each first current source comprises a first transistor.

[0023] Optionally, the first shift register comprises a plurality of outputs, each output being associated with a single bit of the first DAC code signal and coupled to a gate of one of the plurality of first transistors.

[0024] Optionally, the first digital-to-analog converter comprises a plurality of first buffer circuits, and each output is coupled to a gate of one of the plurality of first transistors via the buffer circuit.

[0025] Optionally, each first buffer circuit includes a first inverter.

[0026] Optionally, the digital LDO includes an output capacitor having an equivalent series resistance, and the first DAC signal is provided to the output capacitor to generate the output voltage.

[0027] Optionally, the first time period is a duration during which the first digital-to-analog converter operates in the panic mode.

[0028] Optionally, the first digital-to-analog converter is configured to calculate an average value of the generated first DAC code signal by measuring a peak value of the generated first DAC code signal, measuring a valley value of the generated first DAC code signal, adding the peak value and the valley value and dividing the sum of the peak value and the valley value by 2.

[0029] Optionally, a peak value of the generated first DAC code signal is measured during a falling edge of the error signal and / or a valley value of the generated first DAC code signal is measured during a rising edge of the error signal.

[0030] Optionally, the peak value is measured during a last falling edge of the error signal before the end of the first time period, and / or the valley value is measured during a last rising edge of the error signal before the end of the first time period.

[0031] Optionally, the panic circuit is configured to output a panic signal in response to detecting that the feedback voltage exceeds a first threshold or drops below a second threshold, the panic signal being used to switch the first digital-to-analog converter to a panic mode.

[0032] Optionally, the panic circuit comprises a first comparator configured to compare the feedback voltage with a first threshold and a second comparator configured to compare the feedback voltage with a second threshold.

[0033] Optionally, the panic circuit comprises a logic circuit configured to receive the outputs of the first comparator and the second comparator and to provide a panic signal in response to the first comparator output and the second comparator output indicating that the feedback voltage has exceeded the first threshold or has fallen below the second threshold.

[0034] Optionally, the digital LDO comprises a counter circuit configured to receive the panic signal and the error signal, wherein the first digital-to-analog converter comprises a first shift register configured to generate the first DAC code signal, and the counter circuit is further configured to increment the first shift register during the first time period.

[0035] Optionally, the first time period is a duration during which the first digital-to-analog converter operates in the panic mode.

[0036] Optionally, the digital LDO comprises a clock circuit configured to provide a clock signal to the comparison circuit.

[0037] Optionally, the first time period is a duration that the first digital-to-analog converter operates in a panic mode, and the clock circuit is configured to operate in a fast mode by providing a clock signal at a first frequency during the panic mode, and to operate in a slow mode by providing a clock signal at a second frequency when not in the panic mode, the second frequency being less than the first frequency.

[0038] Optionally, the clock circuit includes a multiplexer and a frequency scaling unit for receiving an input clock signal, the clock circuit is configured to provide the input clock signal as the clock signal during a fast mode, and the frequency scaling unit is configured to reduce the frequency of the input clock signal when generating the clock signal during a slow mode.

[0039] Optionally, the digital LDO comprises a second digital-to-analog converter configured to receive the error signal and generate a second DAC code signal based on the error signal, the output voltage depending on the second DAC code signal.

[0040] Optionally, the first digital-to-analog converter provides coarse control of the output voltage and the second digital-to-analog converter provides fine control of the output voltage.

[0041] Optionally, the second digital-to-analog converter comprises a second shift register configured to generate a second DAC code signal.

[0042] Optionally, the second shift register comprises an up-down counter.

[0043] Optionally, the second digital-to-analog converter includes a plurality of second current sources, wherein each second current source is used as 1 bit of the second DAC code signal.

[0044] Optionally, each second current source comprises a second transistor.

[0045] Optionally, the second shift register comprises a plurality of outputs, each output being associated with a single bit of the second DAC code signal and coupled to a gate of one of the plurality of second current sources.

[0046] Optionally, the second digital-to-analog converter comprises a plurality of second buffer circuits, and each output is coupled to a gate of one of the plurality of second current sources via the buffer circuit.

[0047] Optionally, each second buffer circuit includes a second inverter.

[0048] Optionally, the digital LDO includes an output capacitor having an equivalent series resistance, and the first DAC signal and the second DAC signal are provided to the output capacitor to generate an output voltage.

[0049] Optionally, the panic circuit is configured to output a panic signal in response to detecting that the feedback voltage exceeds a first threshold or drops below a second threshold, the panic signal being used to switch the first digital-to-analog converter to a panic mode.

[0050] Optionally, the panic circuit comprises a first comparator configured to compare the feedback voltage with a first threshold and a second comparator configured to compare the feedback voltage with a second threshold.

[0051] Optionally, the panic circuit comprises a logic circuit configured to receive the outputs of the first comparator and the second comparator and to provide a panic signal in response to the first comparator output and the second comparator output indicating that the feedback voltage has exceeded the first threshold or has fallen below the second threshold.

[0052] Optionally, the digital LDO includes a counter circuit configured to receive the panic signal and the error signal, wherein the first digital-to-analog converter includes a first shift register configured to generate a first DAC code signal, the second digital-to-analog converter includes a second shift register configured to generate a second DAC code signal, and the counter circuit is further configured to increment the first shift register and the second shift register.

[0053] Optionally, the digital LDO comprises a clock circuit configured to provide a clock signal to the comparison circuit.

[0054] Optionally, the first time period is a duration that the first digital-to-analog converter operates in a panic mode, and the clock circuit is configured to operate in a fast mode by providing a clock signal at a first frequency during the panic mode, and to operate in a slow mode by providing a clock signal at a second frequency when not in the panic mode, the second frequency being less than the first frequency.

[0055] Optionally, the clock circuit includes a multiplexer and a frequency scaling unit for receiving an input clock signal, the clock circuit is configured to provide the input clock signal as the clock signal during a fast mode, and the frequency scaling unit is configured to reduce the frequency of the input clock signal when generating the clock signal during a slow mode.

[0056] Optionally, the second digital-to-analog converter is configured to generate the second DAC code signal using a clock signal provided during a slow operating mode of the clock circuit.

[0057] According to a second aspect of the present disclosure, there is provided a method for receiving a reference voltage and generating an output voltage using a digital low dropout regulator, the digital low dropout regulator comprising a comparison circuit, a first digital-to-analog converter and a panic circuit, the method comprising: receiving a reference voltage at the comparison circuit, receiving a feedback voltage at the comparison circuit, the feedback voltage depending on the output voltage, comparing the reference voltage and the feedback voltage using the comparison circuit, generating an error signal depending on the comparison between the reference voltage and the feedback voltage using the comparison circuit, receiving the error signal at a first digital-to-analog converter operating in a panic mode, generating a first DAC code signal based on the error signal within a first time period using the first digital-to-analog converter operating in the panic mode, the output voltage depending on the first DAC code signal, calculating an average value of the generated first DAC code signal during at least a portion of the first time period using the first digital-to-analog converter operating in the panic mode, setting the first DAC code signal to the calculated average value using the first digital-to-analog converter operating in the panic mode, detecting when the feedback voltage exceeds a first threshold or drops below a second threshold using the panic circuit, and controlling the first digital-to-analog converter to operate in the panic mode using the panic circuit when the feedback voltage exceeds the first threshold or drops below the second threshold.

[0058] It is to be understood that the method of the second aspect may include the features set out in the first aspect, and may be combined with other features as described herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] The present disclosure is described in more detail below by way of example and with reference to the accompanying drawings, in which:

[0061] FIG. 1( a ) shows a digital LDO known in the prior art, and FIG. 1( b ) is a schematic diagram of a current mirror scheme known in the prior art for controlling coarse and fine DAC outputs;

[0062] FIG. 2( a ) is a schematic diagram of a digital low dropout regulator (LDO) according to a first embodiment of the present disclosure, and FIG. 2( b ) is a schematic diagram of a digital LDO according to a second embodiment of the present disclosure;

[0063] FIG. 3( a ) is a schematic diagram of an LDO according to a third embodiment of the present disclosure, and FIG. 3( b ) is a schematic diagram of an LDO according to a fourth embodiment of the present disclosure;

[0064] Figure 4 is a schematic diagram of a digital LDO according to a fifth embodiment of the present disclosure;

[0065] FIG. 5( a ) is a schematic diagram of a digital LDO according to a sixth embodiment of the present disclosure, and FIG. 5( b ) is a schematic diagram of an exemplary specific implementation of a clock circuit;

[0066] Figure 6is a schematic diagram of a digital LDO according to a seventh embodiment of the present disclosure;

[0067] Figure 7 is a schematic diagram of a digital LDO according to an eighth embodiment of the present disclosure;

[0068] Figure 8 It is shown Figure 7 timing diagram of simulation results of actual implementation of LDO; and

[0069] Fig. 9 is a flow chart showing an algorithm for capturing minimum and maximum DAC code signal values ​​when the LDO is operating in "fast" mode.

[0070] Detailed Description

[0071] FIG2( a ) is a schematic diagram of a digital low dropout regulator (LDO) 200 according to a first embodiment of the present disclosure. In operation, the LDO 200 receives a reference voltage Vref and generates and outputs a voltage Vout. The LDO 200 includes a comparison circuit 202 , a digital-to-analog converter 204 , and a panic circuit 206 .

[0072] During operation of the LDO 200, the comparison circuit 202 receives a reference voltage Vref and a feedback voltage Vfb. The feedback voltage Vfb depends on the output voltage Vout.

[0073] In a specific embodiment, the feedback voltage Vfb may be the output voltage Vout, where the output voltage Vout is coupled to an input terminal of the comparison circuit 202 .

[0074] In another specific embodiment, the feedback voltage Vfb may be generated based on the output voltage Vout, such that the feedback voltage Vfb is responsive to changes in the output voltage Vout. For example, the feedback voltage Vfb may be generated by providing the output voltage Vout to a voltage divider, the output of which is coupled to an input terminal of the comparison circuit 202. In such an example, the feedback voltage Vfb is a portion of the output voltage Vout, which may be necessary to reduce the voltage provided to the comparison circuit 202 to a suitable operating level.

[0075] In operation, the comparison circuit 202 compares the voltages Vfb and Vref and generates an error signal 208 depending on the comparison result. In a specific embodiment, the comparison may be, for example, subtracting the reference voltage Vref from Vfb, so that the error signal 208 is equal to the feedback voltage Vfb minus the reference voltage Vref.

[0076] In a specific embodiment, the comparison circuit 202 may include a primary comparator or a 1-bit analog-to-digital converter (ADC).

[0077] The DAC 204 is configured to operate in a panic mode. When operating in the panic mode, the DAC 204 receives the error signal 208 and generates a DAC code signal 210 for a time period. The output voltage Vout depends on the DAC code signal 210.

[0078] The time period may be the duration of the operation of the DAC 204 in the panic mode. After the time period has elapsed, the DAC 204 may stop operating in the panic mode and may, for example, switch to the normal operating mode. Before entering the panic mode, the DAC 204 may operate in the normal operating mode.

[0079] The DAC 204 is configured to calculate an average voltage of the DAC code signal 210 during at least a portion of the time period. The DAC 204 is also configured to set the DAC code signal 210 to the calculated average value.

[0080] For example, when DAC 204 is operating in panic mode, DAC code signal 210 may change periodically. This may indicate the limit cycle period discussed previously. To overcome this problem, DAC 204 determines an average value of DAC code signal 210 over at least a portion of the time period that DAC 204 is operating in panic mode, and then sets DAC code signal 210 to the average value, thereby stopping the oscillation.

[0081] The DAC 204 may be configured to calculate an average value of the DAC code signal 210 by measuring the peak and valley values ​​of the DAC code signal 210 , adding the peak and valley values, and then dividing the sum by two.

[0082] The peak value can be measured by the DAC 204 during the falling edge of the error signal 208, because the falling edge indicates that the DAC code signal 210 switches from a rising signal to a falling signal. The valley value can be measured by the DAC 204 during the rising edge of the error signal 208, because the rising edge indicates that the DAC code signal 210 switches from a falling signal to a rising signal.

[0083] The peak value may be measured during the last falling edge of the error signal 208 before the end of the time period. The valley value may be measured during the last rising edge of the error signal 208 before the end of the time period.

[0084] During operation, when the DAC 204 detects that the feedback voltage Vfb exceeds the first threshold or drops below the second threshold, the panic circuit 206 controls the DAC 204 to operate in the panic mode. Therefore, when the panic circuit 206 detects that the value of the feedback voltage Vfb is outside the range surrounded by the first threshold and the second threshold, the panic circuit 206 effectively "switches" the DAC 204 into the panic mode.

[0085] The panic circuit 206 may output a panic signal 212 in response to the feedback voltage Vfb moving outside of a range surrounded by a threshold value, wherein the panic signal 212 is used to switch the DAC 204 to a panic mode.

[0086] FIG2( b) is a schematic diagram of a digital LDO 214 according to a second embodiment of the present disclosure. LDO 214 shares features with LDO 200 and additionally includes a DAC 216. In this embodiment, DAC 216 receives error signal 208 and generates a DAC code signal 218 based on error signal 208, and the output voltage Vout depends on the DAC code signals 210, 218. DAC 204 can provide coarse control of the output voltage Vout, such as provided by DAC 134 of FIG1 (a). DAC 216 can provide fine control of the output voltage Vout, such as provided by DAC 136 of FIG1 (b).

[0087] 3( a ) is a schematic diagram of an LDO 300 according to a third embodiment of the present disclosure. The LDO 300 shares features with the LDO 200 . In this embodiment, the DAC 204 includes a shift register 301 configured to generate a DAC code signal 210 .

[0088] A shift register is a digital circuit that incrementally shifts data from one storage location to another. A shift register may include an up-down counter that may, for example, be used to count up or down, with the output of the shift register indicating whether the currently stored value is incrementing or decrementing during operation.

[0089] In this embodiment, the shift register 301 provides a plurality of outputs 303 , each of which has a binary value during operation and which collectively form the DAC code signal 210 .

[0090] FIG3( b) is a schematic diagram of an LDO 302 according to a fourth embodiment of the present disclosure. The DAC 204 includes current sources 304, 306, each of which is used as one bit of the DAC code signal 210. In the present embodiment, two current sources 304, 306 are shown. However, it should be understood that in other embodiments, the DAC 204 may include more than two current sources, each of which is used as one bit of the DAC code signal 210. Each of the current sources 304, 306 may include a transistor. In the present embodiment, the current source 304 includes a transistor 305, and the current source 306 includes a transistor 307.

[0091] Each output 303 is associated with a single bit of the DAC code signal 210 and is coupled to the gate of one of the transistors 305 , 307 .

[0092] DAC 204 includes buffer circuits 310, 312, wherein each output 303 is coupled to a gate via one of the buffer circuits 310, 312. Buffer circuits 310, 312 may each include an inverter. In this embodiment, buffer circuit 310 includes inverter 311, and buffer circuit 312 includes inverter 313.

[0093] LDO 302 may include an output capacitor Co having an equivalent series resistance (ESR) Ro, wherein DAC signal 210 is provided to output capacitor Co to generate output voltage Vout. It should be noted that the resistor symbol represented by Ro is the ESR of capacitor Co and is therefore not a separate physical component implemented within the circuit.

[0094] Figure 4 is a schematic diagram of a digital LDO 400 according to a fifth embodiment of the present disclosure. LDO 400 shares features with LDO 300. However, it should be understood that the features of LDO 400 may be implemented with any digital LDO system described herein, according to the understanding of a skilled person.

[0095] In this embodiment, the panic circuit 206 includes two comparators 402 and 404. The comparator 402 receives the feedback voltage Vfb and compares the feedback voltage Vfb with a first threshold (provided by the reference voltage Vref1). The comparator 404 receives the feedback voltage Vfb and compares the feedback voltage Vfb with a second threshold (provided by the reference voltage Vref2).

[0096] Panic circuit 206 may also include logic circuit 405 configured to receive the outputs of comparators 402 , 404 and provide panic signal 212 in response to the comparator output indicating that feedback voltage Vfb has moved outside of a voltage range encompassed by thresholds provided by Vref1 and Vref2 .

[0097] LDO 400 may also include a counter circuit 406 configured to receive panic signal 212. Counter circuit 406 may also receive error signal 208. During operation, counter circuit 406 is configured to increment shift register 301 during the time period. As previously described, the time period may be the duration of time that DAC 204 operates in panic mode.

[0098] For example, when the comparators 402, 404 detect that the feedback voltage Vfb is outside the operating window defined by the thresholds provided by Vref1, Vref2, the logic circuit 405 responds by providing the panic signal 212 to the counter circuit 406. For example, when a load transient occurs that causes an undesirable change in the output voltage Vout, the feedback voltage Vfb may move outside the operating window. The counter circuit 406 then increments the shift register 301, thereby incrementing the DAC code signal 210 to restore the output voltage Vout to the expected value defined by the reference voltage Vref.

[0099] 5(a) is a schematic diagram of an LDO 500 according to a sixth embodiment of the present disclosure. LDO 500 shares features with LDO 200. However, it should be understood that the features of LDO 500 may be implemented with any digital LDO system described herein, according to the understanding of a skilled person.

[0100] In the present embodiment, LDO 500 includes a clock circuit 502 configured to provide a clock signal 504 to comparison circuit 202. Clock circuit 502 can be configured to operate in a fast mode by providing clock signal 504 at a first frequency during panic mode, and to operate in a slow mode by providing clock signal 504 at a second frequency when not in panic mode. The second frequency is less than the first frequency.

[0101] 5( b) is a schematic diagram of an exemplary implementation of a clock circuit 502. The clock circuit 502 includes a multiplexer 506 for receiving an input clock signal 508 and a frequency scaling unit 510. The clock circuit 502 is configured to provide the input clock signal 508 as the clock signal 504 during the fast mode, and the frequency scaling unit 510 is configured to reduce the frequency of the input clock signal 508 when generating the clock signal 504 during the slow mode.

[0102] Figure 6 6 is a schematic diagram of a digital LDO 600 according to a seventh embodiment of the present disclosure. In this example, the DAC 216 includes a shift register 602 for generating a DAC signal 604. The shift register 602 may include an up-down counter. The DAC 216 may include a plurality of current sources, and two current sources 606, 608 are provided in the current embodiment. The current sources 606, 608 are each used as 1 bit of the DAC code signal 604. Each current source 606, 608 includes a transistor 607, 609.

[0103] The shift register 602 may include a plurality of outputs 603 , each associated with a single bit of the DAC code signal 604 and coupled to a gate of one of a plurality of current sources 606 , 608 .

[0104] DAC 216 may include a plurality of buffer circuits 610, 612, with each output 603 coupled to the gate of one of current sources 606, 608 via one of the buffer circuits 610, 612. Each of the buffer circuits 610, 612 may include an inverter 614,616.

[0105] In this embodiment, both DAC code signals 210 , 604 are provided to the output capacitor Co to generate the output voltage Vout.

[0106] It should be understood that in certain embodiments, the panic circuit 206 may be implemented as Figure 4 As described, and LDO 600 may include counter circuit 406, such as Figure 4 As described. The counter circuit 406 can increment the two shift registers 301, 602. In addition, a clock circuit 502 that functions as described with respect to FIG. 5(a) can be provided. The DAC 216 can generate the DAC code signal 604 using, for example, a clock signal 504 provided during the slow operating mode. In summary, for a specific embodiment of the LDO 600, during the fast operating mode of the clock circuit 502 (during the panic mode of the DAC 204), the DAC 204 is configured to calculate the average value of the DAC code signal 210 by measuring the peak and valley values ​​of the DAC code signal 210, adding the peak and valley values, and then dividing the sum by 2. The time period during which the fast mode is effective can be referred to as a "fast" clock cycle. The work of determining the average value can be performed at the end of the fast clock cycle, and the average value is calculated using the last maximum and minimum values ​​of the DAC code signal 210 that occurred during the fast clock cycle. Then, the DAC 204 sets the DAC code signal 210 to the calculated average value, thereby providing fast recovery and fast settling to a steady-state output when a transient load is applied.

[0107] Figure 7 is a schematic diagram of a digital LDO 700 according to an eighth embodiment of the present disclosure. The digital LDO 700 includes the following components:

[0108] Clocked comparator (as previously described, associated with comparator circuit 202). During operation, clocked comparator 202 compares a target "vref" voltage (previously labeled Vref) to an output "vout" voltage (previously labeled Vout) and generates a "comp" signal (previously referred to as error signal 208) that is used by a coarse up-down counter (associated with the specific embodiment of shift register 301) and a fine up-down counter (associated with the specific embodiment of shift register 602).

[0109] Panic comparators (depending on the specific implementation of the panic circuit 206). These panic comparators form window comparators and provide outputs indicating whether the output voltage vout is too high "toohi" or too low "toolo". These outputs are used to form a "panic".

[0110] • Shift_counter_coarse (described previously with respect to shift register 301). In the present embodiment, this is a 4-bit up-down counter that controls the large coarse step DAC 204. In the current embodiment, each bit 304, 306 of the DAC 204 is a 10 mA current source, ie, 0 to 150 mA output.

[0111] Shift_counter_fine (described previously with respect to shift register 602). In this embodiment, this is a 5-bit up-down counter that controls the small fine step DAC 216. Each bit 606, 608 of the DAC 216 is a 750 μA current source, i.e., a 0 to 23.23 mA output. The fine DAC 216 is scaled to approximately 2.2 times the coarse step size. When the up-down counter 602 reaches a limit (31 or 0), it instructs the coarse counter 204 to increment ("inc") or decrement ("dec") so that it remains within its controllable region. For example, when the upper limit of 31 is reached, the coarse DAC 204 increments by 10 mA, causing the fine DAC to subtract the nearest 9.25 mA, or 12 codes, causing the next output current to increase by 1 fine DAC 216 step size of 0.75 mA. This allows the control loop to adapt to slowly changing loads without triggering a "panic".

[0112] Clock_control (previously described with respect to clock circuit 502). In this embodiment, clock circuit 502 controls the duration of the panic mode signal ("fast" and "fine") by gating the clock ("gate") every 16 cycles, allowing the "fine" mode to run at 1 / 16 of the clock speed, and divides the system clock for the slower fine control mode.

[0113] Detection. This is a telemetry block that uses the coarse DAC code and fine DAC code ("qq" and "qqfine") to warn and indicate when the output current reaches the maximum value ("warn" and "limit"). It is also possible to measure the output current using an IIR filter and DAC code.

[0114] Overshoot detection. This is a RS latch-triggered pull-down resistor that is used when VOUT is above the "toohi" threshold. If the load current drops (e.g. to zero), this is an effective mechanism to discharge the output capacitor Co. In another embodiment, it can also be used to discharge the output when the LDO is turned off.

[0115] Figure 8 It is shown Figure 7 The timing diagram of the simulation results of the actual implementation of LDO 700 is shown in Figure 1. Figure 8 8, the error signal 208 (trace 800), the "toohi" signal (trace 802), the "toolo" signal (trace 804), the panic signal 212 (trace 806), the "fast" signal (trace 808), the "fine" signal (trace 810), the increment "inc" signal (trace 812), the decrement "dec" signal (trace 814), the "warning" signal (trace 816), the "limit" signal (trace 818), the output voltage vout (trace 820), and the DAC code signal 210 (trace 822) are shown.

[0116] It should be understood that when the "fast" signal is in a high state, the DAC 204 operates in panic mode. When the system detects a "panic", the "fast" signal indicates that the CLK is operating at full speed, and the up-down counter 301 is controlled by the comparator 202. This allows the output current to adjust to transient load changes, but in prior art systems (e.g., as shown in FIG. 1(a)), the stability of the system results in a limit cycle period of the DAC code signal 210, such as occurs from t1 to t2.

[0117] In this embodiment, and with reference to Figure 7 , the clock control 502 indicates "fast" for the following conditions:

[0118] 1.5 comparator edges (as shown in trace 800) + 31 additional clock cycles

[0119] 2. For less than 5 comparator edges (as shown by trace 800), a maximum of 127 clock cycles.

[0120] When the "fast" signal is indicated, the maximum and minimum values ​​of each up-down counter 301 value are captured. This is accomplished by capturing the values ​​on the rising (minimum) and falling (maximum) edges of the comparator "comp" signal (error signal 208 discussed previously).

[0121] At the end of the "fast" period, the average is set to the "best guess" of the desired DAC code signal 210. This is given by:

[0122] QQ = (max + min) / 2 (1)

[0123] Wherein, QQ is the DAC code signal 210, and max represents the peak value of the DAC code signal 210 before the panic mode ends ( Figure 8 ), and min represents the valley of the DAC code signal 210 before the panic mode ends ( Figure 8 point P2).

[0124] Equation (1) uses integer math, so dividing by 2 is a right shift of 1. For example, if max = 12 and min = 5, then:

[0125] QQ = (12 + 5) / 2 = 8 (2)

[0126] An advantage of the technique described herein is that it can reduce and / or eliminate the coarse DAC limit cycle period, which causes the output to settle to a stable state more quickly for inherently unstable loop stability criteria.

[0127] Figure 8 The simulation results presented show a "panic" event where the coarse counter ramps up and then ramps down based on the COMP signal (trace 800). The "fast" signal lasts for 5 COMP edges + 31 clocks.

[0128] For the last limit cycle before the "fast" signal goes low, the values ​​are max = 7 (at point P1) and min = 3 (at point P2). This results in the value DAC signal 210 being after P2 and set to 5 according to equation (1).

[0129] Fig. 9 is a flow chart showing an algorithm for capturing the minimum and maximum DAC code signal 210 values ​​when the LDO 700 is operating in the "fast" mode. This is accomplished by Figure 8 The simulation results presented in show the general algorithmic representation of the process.

[0130] Below is example C code for a coarse DAC up-down counter according to an embodiment of the disclosure.

[0131]

[0132]

[0133]

[0134] The following part of the C-code above can be used to find the qq min / max value on the comparator edge:

[0135]

[0136] The following portion of the C-code above can be used to apply a median current at the falling edge in "fast" mode:

[0137]

[0138] It should be understood that common reference numerals and common variables between the figures represent common features.

[0139] Various improvements and modifications may be made to the above without departing from the scope of the present disclosure.

[0140] This disclosure provides the following:

[0141] Clause 1. A digital low dropout regulator (LDO) for receiving a reference voltage and generating an output voltage, comprising:

[0142] A comparison circuit, the comparison circuit being configured to:

[0143] i) receiving the reference voltage;

[0144] ii) receiving a feedback voltage, wherein the feedback voltage depends on the output voltage;

[0145] iii) comparing the reference voltage and the feedback voltage; and

[0146] iv) generating an error signal, said error signal being dependent on a comparison between said reference voltage and said feedback voltage;

[0147] a first digital-to-analog converter, the first digital-to-analog converter being configured to be capable of operating in a panic mode, wherein the first digital-to-analog converter is configured to:

[0148] i) receiving the error signal;

[0149] ii) generating a first DAC code signal based on the error signal during a first time period, the output voltage depending on the first DAC code signal; and

[0150] iii) calculating an average value of the generated first DAC code signal during at least a portion of the first time period; and

[0151] iv) setting the first DAC code signal to the calculated average value;

[0152] A panic circuit, the panic circuit being configured to:

[0153] i) detecting when the feedback voltage exceeds a first threshold or drops below a second threshold; and

[0154] ii) when the feedback voltage exceeds the first threshold or drops below the second threshold, controlling the first digital-to-analog converter to operate in the panic mode.

[0155] Clause 2. The digital LDO of Clause 1, wherein the first digital-to-analog converter comprises a first shift register configured to generate the first DAC code signal.

[0156] Clause 3. The digital LDO of clause 2, wherein the first digital-to-analog converter comprises a plurality of first current sources, wherein each of the first current sources serves as 1 bit of the first DAC code signal.

[0157] Clause 4. The digital LDO of clause 3, wherein each first current source comprises a first transistor.

[0158] Clause 5. The digital LDO of Clause 4, wherein the first shift register comprises a plurality of outputs, each output being associated with a single bit of the first DAC code signal and coupled to a gate of one of the plurality of first transistors.

[0159] Clause 6. The digital LDO of Clause 5, wherein the first digital-to-analog converter comprises a plurality of first buffer circuits, each output being coupled to a gate of one of the plurality of first transistors via one buffer circuit.

[0160] Clause 7. The digital LDO of Clause 1, wherein the first time period is a duration for which the first digital-to-analog converter operates in the panic mode.

[0161] Clause 8. The digital LDO of clause 1, wherein the first digital-to-analog converter is configured to calculate an average value of the generated first DAC code signal by:

[0162] measuring a peak value of the generated first DAC code signal;

[0163] measuring a valley value of the generated first DAC code signal; and

[0164] The peak value and the valley value are added, and the sum of the peak value and the valley value is divided by two.

[0165] Clause 9. The digital LDO of Clause 8, wherein the peak value of the generated first DAC code signal is measured during a falling edge of the error signal and / or the valley value of the generated first DAC code signal is measured during a rising edge of the error signal.

[0166] Clause 10. The digital LDO of clause 9, wherein the peak value is measured during a last falling edge of the error signal before the end of the first time period, and / or the valley value is measured during a last rising edge of the error signal before the end of the first time period.

[0167] Clause 11. The digital LDO of Clause 1, wherein the panic circuit is configured to output a panic signal in response to detecting that the feedback voltage exceeds the first threshold or drops below the second threshold, the panic signal being used to switch the first digital-to-analog converter to the panic mode.

[0168] Clause 12. The digital LDO of Clause 11, wherein the panic circuit comprises a first comparator configured to compare the feedback voltage with the first threshold and a second comparator configured to compare the feedback voltage with the second threshold.

[0169] Clause 13. The digital LDO of clause 12, wherein the panic circuit comprises a logic circuit configured to receive the outputs of the first comparator and the second comparator and to provide the panic signal in response to the first comparator output and the second comparator output indicating that the feedback voltage has exceeded the first threshold or has fallen below the second threshold.

[0170] Clause 14. The digital LDO of clause 11, comprising:

[0171] a counter circuit configured to receive the panic signal and the error signal; wherein:

[0172] The first digital-to-analog converter comprises a first shift register configured to generate the first DAC code signal; and

[0173] The counter circuit is also configured to increment the first shift register during the first time period.

[0174] Clause 15. The digital LDO of Clause 1, comprising a clock circuit configured to provide a clock signal to the comparison circuit.

[0175] Clause 16. The digital LDO of clause 15, wherein:

[0176] The first time period is a duration for which the first digital-to-analog converter operates in the panic mode;

[0177] The clock circuit is configured to:

[0178] i) operating in a fast mode during the panic mode by providing the clock signal at a first frequency; and ii) operating in a slow mode when not in the panic mode by providing the clock signal at a second frequency,

[0179] The second frequency is lower than the first frequency.

[0180] Clause 17. The digital LDO of clause 16, wherein:

[0181] The clock circuit includes a multiplexer and a frequency scaling unit for receiving an input clock signal;

[0182] The clock circuit is configured to provide the input clock signal as the clock signal during the fast mode; and

[0183] The frequency scaling unit is configured to reduce a frequency of the input clock signal when generating the clock signal during the slow mode.

[0184] Clause 18. The digital LDO of clause 1, comprising a second digital-to-analog converter configured to:

[0185] i) receiving the error signal; and

[0186] ii) generating a second DAC code signal based on the error signal, the output voltage depending on the second DAC code signal.

[0187] Clause 19. The digital LDO of clause 18, wherein the first digital-to-analog converter provides coarse control of the output voltage and the second digital-to-analog converter provides fine control of the output voltage.

[0188] Clause 20. A method of receiving a reference voltage and generating an output voltage using a digital low dropout regulator, the digital low dropout regulator comprising a comparison circuit, a first digital-to-analog converter, and a panic circuit, the method comprising:

[0189] receiving the reference voltage at the comparison circuit;

[0190] receiving a feedback voltage at the comparison circuit, the feedback voltage being dependent on the output voltage;

[0191] Comparing the reference voltage and the feedback voltage using the comparison circuit;

[0192] generating an error signal using the comparison circuit, the error signal being dependent on a comparison between the reference voltage and the feedback voltage;

[0193] receiving the error signal at the first digital-to-analog converter, the first digital-to-analog converter operating in a panic mode;

[0194] generating a first DAC code signal based on the error signal during a first time period using the first digital-to-analog converter operating in the panic mode, the output voltage depending on the first DAC code signal;

[0195] calculating, using the first digital-to-analog converter operating in the panic mode, an average value of the generated first DAC code signal during at least a portion of the first time period;

[0196] using the first digital-to-analog converter operating in the panic mode, setting the first DAC code signal to the calculated average value;

[0197] using the panic circuit to detect when the feedback voltage exceeds a first threshold or drops below a second threshold; and

[0198] When the feedback voltage exceeds the first threshold or drops below the second threshold, the panic circuit is used to control the first digital-to-analog converter to operate in the panic mode.

Claims

1. A digital low dropout regulator LDO for receiving a reference voltage and generating an output voltage, comprising: A comparison circuit, the comparison circuit being configured to: i) receiving the reference voltage; ii) receiving a feedback voltage, wherein the feedback voltage depends on the output voltage; iii) comparing the reference voltage and the feedback voltage; as well as iv) generating an error signal, said error signal being dependent on a comparison between said reference voltage and said feedback voltage; a first digital-to-analog converter, the first digital-to-analog converter being configured to be capable of operating in a panic mode, wherein the first digital-to-analog converter is configured to: i) receiving the error signal; ii) generating a first DAC code signal based on the error signal during a first time period, the output voltage depending on the first DAC code signal; as well as iii) calculating an average value of the generated first DAC code signal during at least a portion of the first time period; and iv) setting the first DAC code signal to the calculated average value; A panic circuit, the panic circuit being configured to: i) detecting when the feedback voltage exceeds a first threshold or drops below a second threshold; as well as ii) when the feedback voltage exceeds the first threshold or drops below the second threshold, controlling the first digital-to-analog converter to operate in the panic mode.

2. The digital LDO according to claim 1, wherein: The first digital-to-analog converter includes a first shift register configured to generate the first DAC code signal.

3. The digital LDO according to claim 2, wherein: The first digital-to-analog converter includes a plurality of first current sources, wherein each of the first current sources is used as 1 bit of the first DAC code signal.

4. The digital LDO according to claim 3, wherein: Each first current source includes a first transistor.

5. The digital LDO according to claim 4, wherein: The first shift register includes a plurality of outputs, each output being associated with a single bit of the first DAC code signal and coupled to a gate of one of the plurality of first transistors.

6. A digital LDO according to any preceding claim, wherein The first digital-to-analog converter is configured to calculate an average value of the generated first DAC code signal by: measuring a peak value of the generated first DAC code signal; measuring a valley value of the generated first DAC code signal; as well as The peak value and the valley value are added, and the sum of the peak value and the valley value is divided by two.

7. The digital LDO according to claim 6, wherein: The peak value of the generated first DAC code signal is measured during a falling edge of the error signal and / or the valley value of the generated first DAC code signal is measured during a rising edge of the error signal.

8. The digital LDO according to claim 7, wherein: The peak value is measured during a last falling edge of the error signal before the end of the first time period, and / or the valley value is measured during a last rising edge of the error signal before the end of the first time period.

9. The digital LDO according to any one of claims 1 to 5, wherein: The panic circuit is configured to output a panic signal in response to detecting that the feedback voltage exceeds the first threshold or drops below the second threshold, the panic signal being used to switch the first digital-to-analog converter to the panic mode.

10. The digital LDO according to claim 9, comprising: a counter circuit configured to receive the panic signal and the error signal; wherein: The first digital-to-analog converter comprises a first shift register configured to generate the first DAC code signal; and The counter circuit is also configured to increment the first shift register during the first time period.

11. The digital LDO according to any one of claims 1 to 5, comprising a clock circuit configured to provide a clock signal to the comparison circuit.

12. The digital LDO of claim 11, wherein: The first time period is a duration for which the first digital-to-analog converter operates in the panic mode; The clock circuit is configured to: i) operating in a fast mode during the panic mode by providing the clock signal at a first frequency; as well as ii) operating in a slow mode when not in the panic mode by providing the clock signal at a second frequency, The second frequency is lower than the first frequency.

13. The digital LDO according to any one of claims 1 to 5, comprising a second digital-to-analog converter, wherein the second digital-to-analog converter is configured to: i) receiving the error signal; and ii) generating a second DAC code signal based on the error signal, the output voltage depending on the second DAC code signal.

14. A method for receiving a reference voltage and generating an output voltage using a digital low voltage dropout regulator, the digital low voltage dropout regulator comprising a comparison circuit, a first digital-to-analog converter and a panic circuit, the method comprising: receiving the reference voltage at the comparison circuit; receiving a feedback voltage at the comparison circuit, the feedback voltage being dependent on the output voltage; Comparing the reference voltage and the feedback voltage using the comparison circuit; generating an error signal using the comparison circuit, the error signal being dependent on a comparison between the reference voltage and the feedback voltage; receiving the error signal at the first digital-to-analog converter, the first digital-to-analog converter operating in a panic mode; generating a first DAC code signal based on the error signal during a first time period using the first digital-to-analog converter operating in the panic mode, the output voltage depending on the first DAC code signal; calculating, using the first digital-to-analog converter operating in the panic mode, an average value of the generated first DAC code signal during at least a portion of the first time period; using the first digital-to-analog converter operating in the panic mode, setting the first DAC code signal to the calculated average value; using the panic circuit to detect when the feedback voltage exceeds a first threshold or drops below a second threshold; as well as When the feedback voltage exceeds the first threshold or drops below the second threshold, the panic circuit is used to control the first digital-to-analog converter to operate in the panic mode.

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